blob: f4893efe8da74d12bfec85e0265e85caf4392cf4 [file] [log] [blame]
Tony Xief6118cc2016-01-15 17:17:32 +08001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Tony Xief6118cc2016-01-15 17:17:32 +08005 */
6
7#include <arch_helpers.h>
8#include <assert.h>
9#include <bakery_lock.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010010#include <bl31.h>
Tony Xief6118cc2016-01-15 17:17:32 +080011#include <debug.h>
12#include <delay_timer.h>
Derek Basehoree13bc542017-02-24 14:31:36 +080013#include <dfs.h>
Tony Xief6118cc2016-01-15 17:17:32 +080014#include <errno.h>
Derek Basehore2707c3d2018-01-23 17:18:57 -080015#include <gicv3.h>
Caesar Wanga5dc64d2016-05-25 19:04:47 +080016#include <gpio.h>
Xing Zheng93280b72016-10-26 21:25:26 +080017#include <m0_ctl.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010018#include <mmio.h>
Caesar Wanga5dc64d2016-05-25 19:04:47 +080019#include <plat_params.h>
Tony Xief6118cc2016-01-15 17:17:32 +080020#include <plat_private.h>
Isla Mitchelle3631462017-07-14 10:46:32 +010021#include <platform.h>
22#include <platform_def.h>
23#include <pmu.h>
24#include <pmu_com.h>
25#include <pwm.h>
Tony Xief6118cc2016-01-15 17:17:32 +080026#include <rk3399_def.h>
Xing Zheng22a98712017-02-24 14:56:41 +080027#include <secure.h>
Tony Xief6118cc2016-01-15 17:17:32 +080028#include <soc.h>
Lin Huang88dd1232017-05-16 16:40:46 +080029#include <string.h>
Caesar Wang5339d182016-10-27 01:13:34 +080030#include <suspend.h>
Tony Xief6118cc2016-01-15 17:17:32 +080031
Tony Xie42e113e2016-07-16 11:16:51 +080032DEFINE_BAKERY_LOCK(rockchip_pd_lock);
33
Caesar Wang59e41b52016-04-10 14:11:07 +080034static uint32_t cpu_warm_boot_addr;
Lin Huang88dd1232017-05-16 16:40:46 +080035static char store_sram[SRAM_BIN_LIMIT + SRAM_TEXT_LIMIT + SRAM_DATA_LIMIT];
Caesar Wangbedba012018-01-30 09:11:24 +080036static uint32_t store_cru[CRU_SDIO0_CON1 / 4 + 1];
Lin Huang2c60b5f2017-05-18 18:04:25 +080037static uint32_t store_usbphy0[7];
38static uint32_t store_usbphy1[7];
39static uint32_t store_grf_io_vsel;
40static uint32_t store_grf_soc_con0;
41static uint32_t store_grf_soc_con1;
42static uint32_t store_grf_soc_con2;
43static uint32_t store_grf_soc_con3;
44static uint32_t store_grf_soc_con4;
45static uint32_t store_grf_soc_con7;
46static uint32_t store_grf_ddrc_con[4];
47static uint32_t store_wdt0[2];
48static uint32_t store_wdt1[2];
Derek Basehore2707c3d2018-01-23 17:18:57 -080049static gicv3_dist_ctx_t dist_ctx;
50static gicv3_redist_ctx_t rdist_ctx;
Caesar Wang59e41b52016-04-10 14:11:07 +080051
Tony Xief6118cc2016-01-15 17:17:32 +080052/*
53 * There are two ways to powering on or off on core.
54 * 1) Control it power domain into on or off in PMU_PWRDN_CON reg,
55 * it is core_pwr_pd mode
56 * 2) Enable the core power manage in PMU_CORE_PM_CON reg,
57 * then, if the core enter into wfi, it power domain will be
58 * powered off automatically. it is core_pwr_wfi or core_pwr_wfi_int mode
59 * so we need core_pm_cfg_info to distinguish which method be used now.
60 */
61
62static uint32_t core_pm_cfg_info[PLATFORM_CORE_COUNT]
63#if USE_COHERENT_MEM
64__attribute__ ((section("tzfw_coherent_mem")))
65#endif
66;/* coheront */
67
Tony Xie42e113e2016-07-16 11:16:51 +080068static void pmu_bus_idle_req(uint32_t bus, uint32_t state)
69{
70 uint32_t bus_id = BIT(bus);
71 uint32_t bus_req;
72 uint32_t wait_cnt = 0;
73 uint32_t bus_state, bus_ack;
74
75 if (state)
76 bus_req = BIT(bus);
77 else
78 bus_req = 0;
79
80 mmio_clrsetbits_32(PMU_BASE + PMU_BUS_IDLE_REQ, bus_id, bus_req);
81
82 do {
83 bus_state = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) & bus_id;
84 bus_ack = mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK) & bus_id;
Derek Basehore1d605f72018-01-23 16:24:43 -080085 if (bus_state == bus_req && bus_ack == bus_req)
86 break;
87
Tony Xie42e113e2016-07-16 11:16:51 +080088 wait_cnt++;
Derek Basehore1d605f72018-01-23 16:24:43 -080089 udelay(1);
90 } while (wait_cnt < MAX_WAIT_COUNT);
Tony Xie42e113e2016-07-16 11:16:51 +080091
92 if (bus_state != bus_req || bus_ack != bus_req) {
93 INFO("%s:st=%x(%x)\n", __func__,
94 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST),
95 bus_state);
96 INFO("%s:st=%x(%x)\n", __func__,
97 mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ACK),
98 bus_ack);
99 }
Tony Xie42e113e2016-07-16 11:16:51 +0800100}
101
102struct pmu_slpdata_s pmu_slpdata;
103
Derek Basehore9b7a1a62018-01-23 16:02:27 -0800104static void qos_restore(void)
Tony Xie42e113e2016-07-16 11:16:51 +0800105{
106 if (pmu_power_domain_st(PD_GPU) == pmu_pd_on)
107 RESTORE_QOS(pmu_slpdata.gpu_qos, GPU);
108 if (pmu_power_domain_st(PD_ISP0) == pmu_pd_on) {
109 RESTORE_QOS(pmu_slpdata.isp0_m0_qos, ISP0_M0);
110 RESTORE_QOS(pmu_slpdata.isp0_m1_qos, ISP0_M1);
111 }
112 if (pmu_power_domain_st(PD_ISP1) == pmu_pd_on) {
113 RESTORE_QOS(pmu_slpdata.isp1_m0_qos, ISP1_M0);
114 RESTORE_QOS(pmu_slpdata.isp1_m1_qos, ISP1_M1);
115 }
116 if (pmu_power_domain_st(PD_VO) == pmu_pd_on) {
117 RESTORE_QOS(pmu_slpdata.vop_big_r, VOP_BIG_R);
118 RESTORE_QOS(pmu_slpdata.vop_big_w, VOP_BIG_W);
119 RESTORE_QOS(pmu_slpdata.vop_little, VOP_LITTLE);
120 }
121 if (pmu_power_domain_st(PD_HDCP) == pmu_pd_on)
122 RESTORE_QOS(pmu_slpdata.hdcp_qos, HDCP);
123 if (pmu_power_domain_st(PD_GMAC) == pmu_pd_on)
124 RESTORE_QOS(pmu_slpdata.gmac_qos, GMAC);
125 if (pmu_power_domain_st(PD_CCI) == pmu_pd_on) {
126 RESTORE_QOS(pmu_slpdata.cci_m0_qos, CCI_M0);
127 RESTORE_QOS(pmu_slpdata.cci_m1_qos, CCI_M1);
128 }
129 if (pmu_power_domain_st(PD_SD) == pmu_pd_on)
130 RESTORE_QOS(pmu_slpdata.sdmmc_qos, SDMMC);
131 if (pmu_power_domain_st(PD_EMMC) == pmu_pd_on)
132 RESTORE_QOS(pmu_slpdata.emmc_qos, EMMC);
133 if (pmu_power_domain_st(PD_SDIOAUDIO) == pmu_pd_on)
134 RESTORE_QOS(pmu_slpdata.sdio_qos, SDIO);
135 if (pmu_power_domain_st(PD_GIC) == pmu_pd_on)
136 RESTORE_QOS(pmu_slpdata.gic_qos, GIC);
137 if (pmu_power_domain_st(PD_RGA) == pmu_pd_on) {
138 RESTORE_QOS(pmu_slpdata.rga_r_qos, RGA_R);
139 RESTORE_QOS(pmu_slpdata.rga_w_qos, RGA_W);
140 }
141 if (pmu_power_domain_st(PD_IEP) == pmu_pd_on)
142 RESTORE_QOS(pmu_slpdata.iep_qos, IEP);
143 if (pmu_power_domain_st(PD_USB3) == pmu_pd_on) {
144 RESTORE_QOS(pmu_slpdata.usb_otg0_qos, USB_OTG0);
145 RESTORE_QOS(pmu_slpdata.usb_otg1_qos, USB_OTG1);
146 }
147 if (pmu_power_domain_st(PD_PERIHP) == pmu_pd_on) {
148 RESTORE_QOS(pmu_slpdata.usb_host0_qos, USB_HOST0);
149 RESTORE_QOS(pmu_slpdata.usb_host1_qos, USB_HOST1);
150 RESTORE_QOS(pmu_slpdata.perihp_nsp_qos, PERIHP_NSP);
151 }
152 if (pmu_power_domain_st(PD_PERILP) == pmu_pd_on) {
153 RESTORE_QOS(pmu_slpdata.dmac0_qos, DMAC0);
154 RESTORE_QOS(pmu_slpdata.dmac1_qos, DMAC1);
155 RESTORE_QOS(pmu_slpdata.dcf_qos, DCF);
156 RESTORE_QOS(pmu_slpdata.crypto0_qos, CRYPTO0);
157 RESTORE_QOS(pmu_slpdata.crypto1_qos, CRYPTO1);
158 RESTORE_QOS(pmu_slpdata.perilp_nsp_qos, PERILP_NSP);
159 RESTORE_QOS(pmu_slpdata.perilpslv_nsp_qos, PERILPSLV_NSP);
160 RESTORE_QOS(pmu_slpdata.peri_cm1_qos, PERI_CM1);
161 }
162 if (pmu_power_domain_st(PD_VDU) == pmu_pd_on)
163 RESTORE_QOS(pmu_slpdata.video_m0_qos, VIDEO_M0);
164 if (pmu_power_domain_st(PD_VCODEC) == pmu_pd_on) {
165 RESTORE_QOS(pmu_slpdata.video_m1_r_qos, VIDEO_M1_R);
166 RESTORE_QOS(pmu_slpdata.video_m1_w_qos, VIDEO_M1_W);
167 }
168}
169
Derek Basehore9b7a1a62018-01-23 16:02:27 -0800170static void qos_save(void)
Tony Xie42e113e2016-07-16 11:16:51 +0800171{
172 if (pmu_power_domain_st(PD_GPU) == pmu_pd_on)
173 SAVE_QOS(pmu_slpdata.gpu_qos, GPU);
174 if (pmu_power_domain_st(PD_ISP0) == pmu_pd_on) {
175 SAVE_QOS(pmu_slpdata.isp0_m0_qos, ISP0_M0);
176 SAVE_QOS(pmu_slpdata.isp0_m1_qos, ISP0_M1);
177 }
178 if (pmu_power_domain_st(PD_ISP1) == pmu_pd_on) {
179 SAVE_QOS(pmu_slpdata.isp1_m0_qos, ISP1_M0);
180 SAVE_QOS(pmu_slpdata.isp1_m1_qos, ISP1_M1);
181 }
182 if (pmu_power_domain_st(PD_VO) == pmu_pd_on) {
183 SAVE_QOS(pmu_slpdata.vop_big_r, VOP_BIG_R);
184 SAVE_QOS(pmu_slpdata.vop_big_w, VOP_BIG_W);
185 SAVE_QOS(pmu_slpdata.vop_little, VOP_LITTLE);
186 }
187 if (pmu_power_domain_st(PD_HDCP) == pmu_pd_on)
188 SAVE_QOS(pmu_slpdata.hdcp_qos, HDCP);
189 if (pmu_power_domain_st(PD_GMAC) == pmu_pd_on)
190 SAVE_QOS(pmu_slpdata.gmac_qos, GMAC);
191 if (pmu_power_domain_st(PD_CCI) == pmu_pd_on) {
192 SAVE_QOS(pmu_slpdata.cci_m0_qos, CCI_M0);
193 SAVE_QOS(pmu_slpdata.cci_m1_qos, CCI_M1);
194 }
195 if (pmu_power_domain_st(PD_SD) == pmu_pd_on)
196 SAVE_QOS(pmu_slpdata.sdmmc_qos, SDMMC);
197 if (pmu_power_domain_st(PD_EMMC) == pmu_pd_on)
198 SAVE_QOS(pmu_slpdata.emmc_qos, EMMC);
199 if (pmu_power_domain_st(PD_SDIOAUDIO) == pmu_pd_on)
200 SAVE_QOS(pmu_slpdata.sdio_qos, SDIO);
201 if (pmu_power_domain_st(PD_GIC) == pmu_pd_on)
202 SAVE_QOS(pmu_slpdata.gic_qos, GIC);
203 if (pmu_power_domain_st(PD_RGA) == pmu_pd_on) {
204 SAVE_QOS(pmu_slpdata.rga_r_qos, RGA_R);
205 SAVE_QOS(pmu_slpdata.rga_w_qos, RGA_W);
206 }
207 if (pmu_power_domain_st(PD_IEP) == pmu_pd_on)
208 SAVE_QOS(pmu_slpdata.iep_qos, IEP);
209 if (pmu_power_domain_st(PD_USB3) == pmu_pd_on) {
210 SAVE_QOS(pmu_slpdata.usb_otg0_qos, USB_OTG0);
211 SAVE_QOS(pmu_slpdata.usb_otg1_qos, USB_OTG1);
212 }
213 if (pmu_power_domain_st(PD_PERIHP) == pmu_pd_on) {
214 SAVE_QOS(pmu_slpdata.usb_host0_qos, USB_HOST0);
215 SAVE_QOS(pmu_slpdata.usb_host1_qos, USB_HOST1);
216 SAVE_QOS(pmu_slpdata.perihp_nsp_qos, PERIHP_NSP);
217 }
218 if (pmu_power_domain_st(PD_PERILP) == pmu_pd_on) {
219 SAVE_QOS(pmu_slpdata.dmac0_qos, DMAC0);
220 SAVE_QOS(pmu_slpdata.dmac1_qos, DMAC1);
221 SAVE_QOS(pmu_slpdata.dcf_qos, DCF);
222 SAVE_QOS(pmu_slpdata.crypto0_qos, CRYPTO0);
223 SAVE_QOS(pmu_slpdata.crypto1_qos, CRYPTO1);
224 SAVE_QOS(pmu_slpdata.perilp_nsp_qos, PERILP_NSP);
225 SAVE_QOS(pmu_slpdata.perilpslv_nsp_qos, PERILPSLV_NSP);
226 SAVE_QOS(pmu_slpdata.peri_cm1_qos, PERI_CM1);
227 }
228 if (pmu_power_domain_st(PD_VDU) == pmu_pd_on)
229 SAVE_QOS(pmu_slpdata.video_m0_qos, VIDEO_M0);
230 if (pmu_power_domain_st(PD_VCODEC) == pmu_pd_on) {
231 SAVE_QOS(pmu_slpdata.video_m1_r_qos, VIDEO_M1_R);
232 SAVE_QOS(pmu_slpdata.video_m1_w_qos, VIDEO_M1_W);
233 }
234}
235
236static int pmu_set_power_domain(uint32_t pd_id, uint32_t pd_state)
237{
238 uint32_t state;
239
240 if (pmu_power_domain_st(pd_id) == pd_state)
241 goto out;
242
243 if (pd_state == pmu_pd_on)
244 pmu_power_domain_ctr(pd_id, pd_state);
245
246 state = (pd_state == pmu_pd_off) ? BUS_IDLE : BUS_ACTIVE;
247
248 switch (pd_id) {
249 case PD_GPU:
250 pmu_bus_idle_req(BUS_ID_GPU, state);
251 break;
252 case PD_VIO:
253 pmu_bus_idle_req(BUS_ID_VIO, state);
254 break;
255 case PD_ISP0:
256 pmu_bus_idle_req(BUS_ID_ISP0, state);
257 break;
258 case PD_ISP1:
259 pmu_bus_idle_req(BUS_ID_ISP1, state);
260 break;
261 case PD_VO:
262 pmu_bus_idle_req(BUS_ID_VOPB, state);
263 pmu_bus_idle_req(BUS_ID_VOPL, state);
264 break;
265 case PD_HDCP:
266 pmu_bus_idle_req(BUS_ID_HDCP, state);
267 break;
268 case PD_TCPD0:
269 break;
270 case PD_TCPD1:
271 break;
272 case PD_GMAC:
273 pmu_bus_idle_req(BUS_ID_GMAC, state);
274 break;
275 case PD_CCI:
276 pmu_bus_idle_req(BUS_ID_CCIM0, state);
277 pmu_bus_idle_req(BUS_ID_CCIM1, state);
278 break;
279 case PD_SD:
280 pmu_bus_idle_req(BUS_ID_SD, state);
281 break;
282 case PD_EMMC:
283 pmu_bus_idle_req(BUS_ID_EMMC, state);
284 break;
285 case PD_EDP:
286 pmu_bus_idle_req(BUS_ID_EDP, state);
287 break;
288 case PD_SDIOAUDIO:
289 pmu_bus_idle_req(BUS_ID_SDIOAUDIO, state);
290 break;
291 case PD_GIC:
292 pmu_bus_idle_req(BUS_ID_GIC, state);
293 break;
294 case PD_RGA:
295 pmu_bus_idle_req(BUS_ID_RGA, state);
296 break;
297 case PD_VCODEC:
298 pmu_bus_idle_req(BUS_ID_VCODEC, state);
299 break;
300 case PD_VDU:
301 pmu_bus_idle_req(BUS_ID_VDU, state);
302 break;
303 case PD_IEP:
304 pmu_bus_idle_req(BUS_ID_IEP, state);
305 break;
306 case PD_USB3:
307 pmu_bus_idle_req(BUS_ID_USB3, state);
308 break;
309 case PD_PERIHP:
310 pmu_bus_idle_req(BUS_ID_PERIHP, state);
311 break;
312 default:
313 break;
314 }
315
316 if (pd_state == pmu_pd_off)
317 pmu_power_domain_ctr(pd_id, pd_state);
318
319out:
320 return 0;
321}
322
323static uint32_t pmu_powerdomain_state;
324
325static void pmu_power_domains_suspend(void)
326{
327 clk_gate_con_save();
328 clk_gate_con_disable();
329 qos_save();
330 pmu_powerdomain_state = mmio_read_32(PMU_BASE + PMU_PWRDN_ST);
331 pmu_set_power_domain(PD_GPU, pmu_pd_off);
332 pmu_set_power_domain(PD_TCPD0, pmu_pd_off);
333 pmu_set_power_domain(PD_TCPD1, pmu_pd_off);
334 pmu_set_power_domain(PD_VO, pmu_pd_off);
335 pmu_set_power_domain(PD_ISP0, pmu_pd_off);
336 pmu_set_power_domain(PD_ISP1, pmu_pd_off);
337 pmu_set_power_domain(PD_HDCP, pmu_pd_off);
338 pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_off);
339 pmu_set_power_domain(PD_GMAC, pmu_pd_off);
340 pmu_set_power_domain(PD_EDP, pmu_pd_off);
341 pmu_set_power_domain(PD_IEP, pmu_pd_off);
342 pmu_set_power_domain(PD_RGA, pmu_pd_off);
343 pmu_set_power_domain(PD_VCODEC, pmu_pd_off);
344 pmu_set_power_domain(PD_VDU, pmu_pd_off);
Lin Huang127527f2017-05-22 10:29:59 +0800345 pmu_set_power_domain(PD_USB3, pmu_pd_off);
346 pmu_set_power_domain(PD_EMMC, pmu_pd_off);
347 pmu_set_power_domain(PD_VIO, pmu_pd_off);
348 pmu_set_power_domain(PD_SD, pmu_pd_off);
349 pmu_set_power_domain(PD_PERIHP, pmu_pd_off);
Tony Xie42e113e2016-07-16 11:16:51 +0800350 clk_gate_con_restore();
351}
352
353static void pmu_power_domains_resume(void)
354{
355 clk_gate_con_save();
356 clk_gate_con_disable();
357 if (!(pmu_powerdomain_state & BIT(PD_VDU)))
358 pmu_set_power_domain(PD_VDU, pmu_pd_on);
359 if (!(pmu_powerdomain_state & BIT(PD_VCODEC)))
360 pmu_set_power_domain(PD_VCODEC, pmu_pd_on);
361 if (!(pmu_powerdomain_state & BIT(PD_RGA)))
362 pmu_set_power_domain(PD_RGA, pmu_pd_on);
363 if (!(pmu_powerdomain_state & BIT(PD_IEP)))
364 pmu_set_power_domain(PD_IEP, pmu_pd_on);
365 if (!(pmu_powerdomain_state & BIT(PD_EDP)))
366 pmu_set_power_domain(PD_EDP, pmu_pd_on);
367 if (!(pmu_powerdomain_state & BIT(PD_GMAC)))
368 pmu_set_power_domain(PD_GMAC, pmu_pd_on);
369 if (!(pmu_powerdomain_state & BIT(PD_SDIOAUDIO)))
370 pmu_set_power_domain(PD_SDIOAUDIO, pmu_pd_on);
371 if (!(pmu_powerdomain_state & BIT(PD_HDCP)))
372 pmu_set_power_domain(PD_HDCP, pmu_pd_on);
373 if (!(pmu_powerdomain_state & BIT(PD_ISP1)))
374 pmu_set_power_domain(PD_ISP1, pmu_pd_on);
375 if (!(pmu_powerdomain_state & BIT(PD_ISP0)))
376 pmu_set_power_domain(PD_ISP0, pmu_pd_on);
377 if (!(pmu_powerdomain_state & BIT(PD_VO)))
378 pmu_set_power_domain(PD_VO, pmu_pd_on);
379 if (!(pmu_powerdomain_state & BIT(PD_TCPD1)))
380 pmu_set_power_domain(PD_TCPD1, pmu_pd_on);
381 if (!(pmu_powerdomain_state & BIT(PD_TCPD0)))
382 pmu_set_power_domain(PD_TCPD0, pmu_pd_on);
383 if (!(pmu_powerdomain_state & BIT(PD_GPU)))
384 pmu_set_power_domain(PD_GPU, pmu_pd_on);
Lin Huang127527f2017-05-22 10:29:59 +0800385 if (!(pmu_powerdomain_state & BIT(PD_USB3)))
386 pmu_set_power_domain(PD_USB3, pmu_pd_on);
387 if (!(pmu_powerdomain_state & BIT(PD_EMMC)))
388 pmu_set_power_domain(PD_EMMC, pmu_pd_on);
389 if (!(pmu_powerdomain_state & BIT(PD_VIO)))
390 pmu_set_power_domain(PD_VIO, pmu_pd_on);
391 if (!(pmu_powerdomain_state & BIT(PD_SD)))
392 pmu_set_power_domain(PD_SD, pmu_pd_on);
393 if (!(pmu_powerdomain_state & BIT(PD_PERIHP)))
394 pmu_set_power_domain(PD_PERIHP, pmu_pd_on);
Tony Xie42e113e2016-07-16 11:16:51 +0800395 qos_restore();
396 clk_gate_con_restore();
397}
398
Caesar Wang51d3c102017-06-19 14:02:52 +0800399void rk3399_flush_l2_b(void)
Caesar Wang59e41b52016-04-10 14:11:07 +0800400{
401 uint32_t wait_cnt = 0;
402
403 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B));
404 dsb();
405
Caesar Wang51d3c102017-06-19 14:02:52 +0800406 /*
407 * The Big cluster flush L2 cache took ~4ms by default, give 10ms for
408 * the enough margin.
409 */
Caesar Wang59e41b52016-04-10 14:11:07 +0800410 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) &
411 BIT(L2_FLUSHDONE_CLUSTER_B))) {
412 wait_cnt++;
Caesar Wang51d3c102017-06-19 14:02:52 +0800413 udelay(10);
414 if (wait_cnt == 10000 / 10)
415 WARN("L2 cache flush on suspend took longer than 10ms\n");
Caesar Wang59e41b52016-04-10 14:11:07 +0800416 }
417
418 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(L2_FLUSH_REQ_CLUSTER_B));
419}
420
421static void pmu_scu_b_pwrdn(void)
422{
423 uint32_t wait_cnt = 0;
424
425 if ((mmio_read_32(PMU_BASE + PMU_PWRDN_ST) &
426 (BIT(PMU_A72_B0_PWRDWN_ST) | BIT(PMU_A72_B1_PWRDWN_ST))) !=
427 (BIT(PMU_A72_B0_PWRDWN_ST) | BIT(PMU_A72_B1_PWRDWN_ST))) {
428 ERROR("%s: not all cpus is off\n", __func__);
429 return;
430 }
431
Caesar Wang51d3c102017-06-19 14:02:52 +0800432 rk3399_flush_l2_b();
Caesar Wang59e41b52016-04-10 14:11:07 +0800433
434 mmio_setbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG));
435
436 while (!(mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST) &
437 BIT(STANDBY_BY_WFIL2_CLUSTER_B))) {
438 wait_cnt++;
Derek Basehore1d605f72018-01-23 16:24:43 -0800439 udelay(1);
Tony Xie42e113e2016-07-16 11:16:51 +0800440 if (wait_cnt >= MAX_WAIT_COUNT)
Caesar Wang59e41b52016-04-10 14:11:07 +0800441 ERROR("%s:wait cluster-b l2(%x)\n", __func__,
442 mmio_read_32(PMU_BASE + PMU_CORE_PWR_ST));
443 }
444}
445
446static void pmu_scu_b_pwrup(void)
447{
448 mmio_clrbits_32(PMU_BASE + PMU_SFT_CON, BIT(ACINACTM_CLUSTER_B_CFG));
449}
450
Tony Xief6118cc2016-01-15 17:17:32 +0800451static inline uint32_t get_cpus_pwr_domain_cfg_info(uint32_t cpu_id)
452{
Sandrine Bailleuxbd1a3742016-05-05 10:04:15 +0100453 assert(cpu_id < PLATFORM_CORE_COUNT);
Tony Xief6118cc2016-01-15 17:17:32 +0800454 return core_pm_cfg_info[cpu_id];
455}
456
457static inline void set_cpus_pwr_domain_cfg_info(uint32_t cpu_id, uint32_t value)
458{
Sandrine Bailleuxbd1a3742016-05-05 10:04:15 +0100459 assert(cpu_id < PLATFORM_CORE_COUNT);
Tony Xief6118cc2016-01-15 17:17:32 +0800460 core_pm_cfg_info[cpu_id] = value;
461#if !USE_COHERENT_MEM
462 flush_dcache_range((uintptr_t)&core_pm_cfg_info[cpu_id],
463 sizeof(uint32_t));
464#endif
465}
466
467static int cpus_power_domain_on(uint32_t cpu_id)
468{
469 uint32_t cfg_info;
470 uint32_t cpu_pd = PD_CPUL0 + cpu_id;
471 /*
472 * There are two ways to powering on or off on core.
473 * 1) Control it power domain into on or off in PMU_PWRDN_CON reg
474 * 2) Enable the core power manage in PMU_CORE_PM_CON reg,
475 * then, if the core enter into wfi, it power domain will be
476 * powered off automatically.
477 */
478
479 cfg_info = get_cpus_pwr_domain_cfg_info(cpu_id);
480
481 if (cfg_info == core_pwr_pd) {
482 /* disable core_pm cfg */
483 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
484 CORES_PM_DISABLE);
485 /* if the cores have be on, power off it firstly */
486 if (pmu_power_domain_st(cpu_pd) == pmu_pd_on) {
487 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), 0);
488 pmu_power_domain_ctr(cpu_pd, pmu_pd_off);
489 }
490
491 pmu_power_domain_ctr(cpu_pd, pmu_pd_on);
492 } else {
493 if (pmu_power_domain_st(cpu_pd) == pmu_pd_on) {
494 WARN("%s: cpu%d is not in off,!\n", __func__, cpu_id);
495 return -EINVAL;
496 }
497
498 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
499 BIT(core_pm_sft_wakeup_en));
Caesar Wang59e41b52016-04-10 14:11:07 +0800500 dsb();
Tony Xief6118cc2016-01-15 17:17:32 +0800501 }
502
503 return 0;
504}
505
506static int cpus_power_domain_off(uint32_t cpu_id, uint32_t pd_cfg)
507{
508 uint32_t cpu_pd;
509 uint32_t core_pm_value;
510
511 cpu_pd = PD_CPUL0 + cpu_id;
512 if (pmu_power_domain_st(cpu_pd) == pmu_pd_off)
513 return 0;
514
515 if (pd_cfg == core_pwr_pd) {
516 if (check_cpu_wfie(cpu_id, CKECK_WFEI_MSK))
517 return -EINVAL;
518
519 /* disable core_pm cfg */
520 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
521 CORES_PM_DISABLE);
522
523 set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg);
524 pmu_power_domain_ctr(cpu_pd, pmu_pd_off);
525 } else {
526 set_cpus_pwr_domain_cfg_info(cpu_id, pd_cfg);
527
528 core_pm_value = BIT(core_pm_en);
529 if (pd_cfg == core_pwr_wfi_int)
530 core_pm_value |= BIT(core_pm_int_wakeup_en);
531 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
532 core_pm_value);
Caesar Wang59e41b52016-04-10 14:11:07 +0800533 dsb();
Tony Xief6118cc2016-01-15 17:17:32 +0800534 }
535
536 return 0;
537}
538
Tony Xie42e113e2016-07-16 11:16:51 +0800539static inline void clst_pwr_domain_suspend(plat_local_state_t lvl_state)
540{
541 uint32_t cpu_id = plat_my_core_pos();
542 uint32_t pll_id, clst_st_msk, clst_st_chk_msk, pmu_st;
543
544 assert(cpu_id < PLATFORM_CORE_COUNT);
545
Tony Xie6d7d93c2016-09-02 11:13:38 -0700546 if (lvl_state == PLAT_MAX_OFF_STATE) {
Tony Xie42e113e2016-07-16 11:16:51 +0800547 if (cpu_id < PLATFORM_CLUSTER0_CORE_COUNT) {
548 pll_id = ALPLL_ID;
549 clst_st_msk = CLST_L_CPUS_MSK;
550 } else {
551 pll_id = ABPLL_ID;
552 clst_st_msk = CLST_B_CPUS_MSK <<
553 PLATFORM_CLUSTER0_CORE_COUNT;
554 }
555
556 clst_st_chk_msk = clst_st_msk & ~(BIT(cpu_id));
557
558 pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST);
559
560 pmu_st &= clst_st_msk;
561
562 if (pmu_st == clst_st_chk_msk) {
563 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3),
564 PLL_SLOW_MODE);
565
566 clst_warmboot_data[pll_id] = PMU_CLST_RET;
567
568 pmu_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST);
569 pmu_st &= clst_st_msk;
570 if (pmu_st == clst_st_chk_msk)
571 return;
572 /*
573 * it is mean that others cpu is up again,
574 * we must resume the cfg at once.
575 */
576 mmio_write_32(CRU_BASE + CRU_PLL_CON(pll_id, 3),
577 PLL_NOMAL_MODE);
578 clst_warmboot_data[pll_id] = 0;
579 }
580 }
581}
582
583static int clst_pwr_domain_resume(plat_local_state_t lvl_state)
584{
585 uint32_t cpu_id = plat_my_core_pos();
586 uint32_t pll_id, pll_st;
587
588 assert(cpu_id < PLATFORM_CORE_COUNT);
589
Tony Xie6d7d93c2016-09-02 11:13:38 -0700590 if (lvl_state == PLAT_MAX_OFF_STATE) {
Tony Xie42e113e2016-07-16 11:16:51 +0800591 if (cpu_id < PLATFORM_CLUSTER0_CORE_COUNT)
592 pll_id = ALPLL_ID;
593 else
594 pll_id = ABPLL_ID;
595
596 pll_st = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, 3)) >>
597 PLL_MODE_SHIFT;
598
599 if (pll_st != NORMAL_MODE) {
600 WARN("%s: clst (%d) is in error mode (%d)\n",
601 __func__, pll_id, pll_st);
602 return -1;
603 }
604 }
605
606 return 0;
607}
608
Tony Xief6118cc2016-01-15 17:17:32 +0800609static void nonboot_cpus_off(void)
610{
611 uint32_t boot_cpu, cpu;
612
613 boot_cpu = plat_my_core_pos();
614
615 /* turn off noboot cpus */
616 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++) {
617 if (cpu == boot_cpu)
618 continue;
619 cpus_power_domain_off(cpu, core_pwr_pd);
620 }
621}
622
tony.xie422d51c2017-03-01 11:05:17 +0800623int rockchip_soc_cores_pwr_dm_on(unsigned long mpidr, uint64_t entrypoint)
Tony Xief6118cc2016-01-15 17:17:32 +0800624{
625 uint32_t cpu_id = plat_core_pos_by_mpidr(mpidr);
626
Sandrine Bailleuxbd1a3742016-05-05 10:04:15 +0100627 assert(cpu_id < PLATFORM_CORE_COUNT);
Tony Xief6118cc2016-01-15 17:17:32 +0800628 assert(cpuson_flags[cpu_id] == 0);
629 cpuson_flags[cpu_id] = PMU_CPU_HOTPLUG;
630 cpuson_entry_point[cpu_id] = entrypoint;
631 dsb();
632
633 cpus_power_domain_on(cpu_id);
634
tony.xie422d51c2017-03-01 11:05:17 +0800635 return PSCI_E_SUCCESS;
Tony Xief6118cc2016-01-15 17:17:32 +0800636}
637
tony.xie422d51c2017-03-01 11:05:17 +0800638int rockchip_soc_cores_pwr_dm_off(void)
Tony Xief6118cc2016-01-15 17:17:32 +0800639{
640 uint32_t cpu_id = plat_my_core_pos();
641
642 cpus_power_domain_off(cpu_id, core_pwr_wfi);
643
tony.xie422d51c2017-03-01 11:05:17 +0800644 return PSCI_E_SUCCESS;
Tony Xief6118cc2016-01-15 17:17:32 +0800645}
646
tony.xie422d51c2017-03-01 11:05:17 +0800647int rockchip_soc_hlvl_pwr_dm_off(uint32_t lvl,
648 plat_local_state_t lvl_state)
Tony Xie42e113e2016-07-16 11:16:51 +0800649{
650 switch (lvl) {
651 case MPIDR_AFFLVL1:
652 clst_pwr_domain_suspend(lvl_state);
653 break;
654 default:
655 break;
656 }
657
tony.xie422d51c2017-03-01 11:05:17 +0800658 return PSCI_E_SUCCESS;
Tony Xie42e113e2016-07-16 11:16:51 +0800659}
660
tony.xie422d51c2017-03-01 11:05:17 +0800661int rockchip_soc_cores_pwr_dm_suspend(void)
Tony Xief6118cc2016-01-15 17:17:32 +0800662{
663 uint32_t cpu_id = plat_my_core_pos();
664
Sandrine Bailleuxbd1a3742016-05-05 10:04:15 +0100665 assert(cpu_id < PLATFORM_CORE_COUNT);
Tony Xief6118cc2016-01-15 17:17:32 +0800666 assert(cpuson_flags[cpu_id] == 0);
667 cpuson_flags[cpu_id] = PMU_CPU_AUTO_PWRDN;
Tony Xie42e113e2016-07-16 11:16:51 +0800668 cpuson_entry_point[cpu_id] = plat_get_sec_entrypoint();
Tony Xief6118cc2016-01-15 17:17:32 +0800669 dsb();
670
671 cpus_power_domain_off(cpu_id, core_pwr_wfi_int);
672
tony.xie422d51c2017-03-01 11:05:17 +0800673 return PSCI_E_SUCCESS;
Tony Xief6118cc2016-01-15 17:17:32 +0800674}
675
tony.xie422d51c2017-03-01 11:05:17 +0800676int rockchip_soc_hlvl_pwr_dm_suspend(uint32_t lvl, plat_local_state_t lvl_state)
Tony Xie42e113e2016-07-16 11:16:51 +0800677{
678 switch (lvl) {
679 case MPIDR_AFFLVL1:
680 clst_pwr_domain_suspend(lvl_state);
681 break;
682 default:
683 break;
684 }
685
tony.xie422d51c2017-03-01 11:05:17 +0800686 return PSCI_E_SUCCESS;
Tony Xie42e113e2016-07-16 11:16:51 +0800687}
688
tony.xie422d51c2017-03-01 11:05:17 +0800689int rockchip_soc_cores_pwr_dm_on_finish(void)
Tony Xief6118cc2016-01-15 17:17:32 +0800690{
691 uint32_t cpu_id = plat_my_core_pos();
692
Tony Xie42e113e2016-07-16 11:16:51 +0800693 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id),
694 CORES_PM_DISABLE);
tony.xie422d51c2017-03-01 11:05:17 +0800695 return PSCI_E_SUCCESS;
Tony Xie42e113e2016-07-16 11:16:51 +0800696}
697
tony.xie422d51c2017-03-01 11:05:17 +0800698int rockchip_soc_hlvl_pwr_dm_on_finish(uint32_t lvl,
699 plat_local_state_t lvl_state)
Tony Xie42e113e2016-07-16 11:16:51 +0800700{
701 switch (lvl) {
702 case MPIDR_AFFLVL1:
703 clst_pwr_domain_resume(lvl_state);
704 break;
705 default:
706 break;
707 }
Tony Xief6118cc2016-01-15 17:17:32 +0800708
tony.xie422d51c2017-03-01 11:05:17 +0800709 return PSCI_E_SUCCESS;
Tony Xief6118cc2016-01-15 17:17:32 +0800710}
711
tony.xie422d51c2017-03-01 11:05:17 +0800712int rockchip_soc_cores_pwr_dm_resume(void)
Tony Xief6118cc2016-01-15 17:17:32 +0800713{
714 uint32_t cpu_id = plat_my_core_pos();
715
Tony Xief6118cc2016-01-15 17:17:32 +0800716 /* Disable core_pm */
717 mmio_write_32(PMU_BASE + PMU_CORE_PM_CON(cpu_id), CORES_PM_DISABLE);
718
tony.xie422d51c2017-03-01 11:05:17 +0800719 return PSCI_E_SUCCESS;
Tony Xief6118cc2016-01-15 17:17:32 +0800720}
721
tony.xie422d51c2017-03-01 11:05:17 +0800722int rockchip_soc_hlvl_pwr_dm_resume(uint32_t lvl, plat_local_state_t lvl_state)
Tony Xie42e113e2016-07-16 11:16:51 +0800723{
724 switch (lvl) {
725 case MPIDR_AFFLVL1:
726 clst_pwr_domain_resume(lvl_state);
727 default:
728 break;
729 }
730
tony.xie422d51c2017-03-01 11:05:17 +0800731 return PSCI_E_SUCCESS;
Tony Xie42e113e2016-07-16 11:16:51 +0800732}
733
Caesar Wang34d18d32016-08-25 06:29:46 +0800734/**
735 * init_pmu_counts - Init timing counts in the PMU register area
736 *
737 * At various points when we power up or down parts of the system we need
738 * a delay to wait for power / clocks to become stable. The PMU has counters
739 * to help software do the delay properly. Basically, it works like this:
740 * - Software sets up counter values
741 * - When software turns on something in the PMU, the counter kicks off
742 * - The hardware sets a bit automatically when the counter has finished and
743 * software knows that the initialization is done.
744 *
745 * It's software's job to setup these counters. The hardware power on default
746 * for these settings is conservative, setting everything to 0x5dc0
747 * (750 ms in 32 kHz counts or 1 ms in 24 MHz counts).
748 *
749 * Note that some of these counters are only really used at suspend/resume
750 * time (for instance, that's the only time we turn off/on the oscillator) and
751 * others are used during normal runtime (like turning on/off a CPU or GPU) but
752 * it doesn't hurt to init everything at boot.
753 *
754 * Also note that these counters can run off the 32 kHz clock or the 24 MHz
755 * clock. While the 24 MHz clock can give us more precision, it's not always
Caesar Wange67b1de2016-08-17 17:22:10 -0700756 * available (like when we turn the oscillator off at sleep time). The
757 * pmu_use_lf (lf: low freq) is available in power mode. Current understanding
758 * is that counts work like this:
Caesar Wang34d18d32016-08-25 06:29:46 +0800759 * IF (pmu_use_lf == 0) || (power_mode_en == 0)
760 * use the 24M OSC for counts
761 * ELSE
762 * use the 32K OSC for counts
763 *
764 * Notes:
765 * - There is a separate bit for the PMU called PMU_24M_EN_CFG. At the moment
766 * we always keep that 0. This apparently choose between using the PLL as
767 * the source for the PMU vs. the 24M clock. If we ever set it to 1 we
768 * should consider how it affects these counts (if at all).
769 * - The power_mode_en is documented to auto-clear automatically when we leave
770 * "power mode". That's why most clocks are on 24M. Only timings used when
771 * in "power mode" are 32k.
772 * - In some cases the kernel may override these counts.
773 *
774 * The PMU_STABLE_CNT / PMU_OSC_CNT / PMU_PLLLOCK_CNT are important CNTs
775 * in power mode, we need to ensure that they are available.
776 */
777static void init_pmu_counts(void)
778{
779 /* COUNTS FOR INSIDE POWER MODE */
780
781 /*
782 * From limited testing, need PMU stable >= 2ms, but go overkill
783 * and choose 30 ms to match testing on past SoCs. Also let
784 * OSC have 30 ms for stabilization.
785 */
786 mmio_write_32(PMU_BASE + PMU_STABLE_CNT, CYCL_32K_CNT_MS(30));
787 mmio_write_32(PMU_BASE + PMU_OSC_CNT, CYCL_32K_CNT_MS(30));
788
789 /* Unclear what these should be; try 3 ms */
790 mmio_write_32(PMU_BASE + PMU_WAKEUP_RST_CLR_CNT, CYCL_32K_CNT_MS(3));
791
792 /* Unclear what this should be, but set the default explicitly */
793 mmio_write_32(PMU_BASE + PMU_TIMEOUT_CNT, 0x5dc0);
794
795 /* COUNTS FOR OUTSIDE POWER MODE */
796
797 /* Put something sorta conservative here until we know better */
798 mmio_write_32(PMU_BASE + PMU_PLLLOCK_CNT, CYCL_24M_CNT_MS(3));
799 mmio_write_32(PMU_BASE + PMU_DDRIO_PWRON_CNT, CYCL_24M_CNT_MS(1));
800 mmio_write_32(PMU_BASE + PMU_CENTER_PWRDN_CNT, CYCL_24M_CNT_MS(1));
801 mmio_write_32(PMU_BASE + PMU_CENTER_PWRUP_CNT, CYCL_24M_CNT_MS(1));
802
803 /*
Lin Huang88dd1232017-05-16 16:40:46 +0800804 * when we enable PMU_CLR_PERILP, it will shut down the SRAM, but
805 * M0 code run in SRAM, and we need it to check whether cpu enter
806 * FSM status, so we must wait M0 finish their code and enter WFI,
807 * then we can shutdown SRAM, according FSM order:
808 * ST_NORMAL->..->ST_SCU_L_PWRDN->..->ST_CENTER_PWRDN->ST_PERILP_PWRDN
809 * we can add delay when shutdown ST_SCU_L_PWRDN to guarantee M0 get
810 * the FSM status and enter WFI, then enable PMU_CLR_PERILP.
811 */
812 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRDN_CNT, CYCL_24M_CNT_MS(5));
813 mmio_write_32(PMU_BASE + PMU_SCU_L_PWRUP_CNT, CYCL_24M_CNT_US(1));
814
815 /*
Caesar Wang34d18d32016-08-25 06:29:46 +0800816 * Set CPU/GPU to 1 us.
817 *
818 * NOTE: Even though ATF doesn't configure the GPU we'll still setup
819 * counts here. After all ATF controls all these other bits and also
820 * chooses which clock these counters use.
821 */
Caesar Wang34d18d32016-08-25 06:29:46 +0800822 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRDN_CNT, CYCL_24M_CNT_US(1));
823 mmio_write_32(PMU_BASE + PMU_SCU_B_PWRUP_CNT, CYCL_24M_CNT_US(1));
824 mmio_write_32(PMU_BASE + PMU_GPU_PWRDN_CNT, CYCL_24M_CNT_US(1));
825 mmio_write_32(PMU_BASE + PMU_GPU_PWRUP_CNT, CYCL_24M_CNT_US(1));
826}
827
Caesar Wang5339d182016-10-27 01:13:34 +0800828static uint32_t clk_ddrc_save;
829
Tony Xief6118cc2016-01-15 17:17:32 +0800830static void sys_slp_config(void)
831{
832 uint32_t slp_mode_cfg = 0;
833
Caesar Wang5339d182016-10-27 01:13:34 +0800834 /* keep enabling clk_ddrc_bpll_src_en gate for DDRC */
835 clk_ddrc_save = mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(3));
836 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3), WMSK_BIT(1));
837
838 prepare_abpll_for_ddrctrl();
839 sram_func_set_ddrctl_pll(ABPLL_ID);
840
Tony Xie42e113e2016-07-16 11:16:51 +0800841 mmio_write_32(GRF_BASE + GRF_SOC_CON4, CCI_FORCE_WAKEUP);
Caesar Wang59e41b52016-04-10 14:11:07 +0800842 mmio_write_32(PMU_BASE + PMU_CCI500_CON,
843 BIT_WITH_WMSK(PMU_CLR_PREQ_CCI500_HW) |
844 BIT_WITH_WMSK(PMU_CLR_QREQ_CCI500_HW) |
845 BIT_WITH_WMSK(PMU_QGATING_CCI500_CFG));
846
847 mmio_write_32(PMU_BASE + PMU_ADB400_CON,
848 BIT_WITH_WMSK(PMU_CLR_CORE_L_HW) |
849 BIT_WITH_WMSK(PMU_CLR_CORE_L_2GIC_HW) |
850 BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW));
851
Caesar Wang59e41b52016-04-10 14:11:07 +0800852 slp_mode_cfg = BIT(PMU_PWR_MODE_EN) |
Lin Huang127527f2017-05-22 10:29:59 +0800853 BIT(PMU_INPUT_CLAMP_EN) |
Caesar Wang59e41b52016-04-10 14:11:07 +0800854 BIT(PMU_POWER_OFF_REQ_CFG) |
855 BIT(PMU_CPU0_PD_EN) |
856 BIT(PMU_L2_FLUSH_EN) |
857 BIT(PMU_L2_IDLE_EN) |
Tony Xie42e113e2016-07-16 11:16:51 +0800858 BIT(PMU_SCU_PD_EN) |
859 BIT(PMU_CCI_PD_EN) |
860 BIT(PMU_CLK_CORE_SRC_GATE_EN) |
Tony Xie42e113e2016-07-16 11:16:51 +0800861 BIT(PMU_ALIVE_USE_LF) |
862 BIT(PMU_SREF0_ENTER_EN) |
863 BIT(PMU_SREF1_ENTER_EN) |
864 BIT(PMU_DDRC0_GATING_EN) |
865 BIT(PMU_DDRC1_GATING_EN) |
866 BIT(PMU_DDRIO0_RET_EN) |
Lin Huang127527f2017-05-22 10:29:59 +0800867 BIT(PMU_DDRIO0_RET_DE_REQ) |
Tony Xie42e113e2016-07-16 11:16:51 +0800868 BIT(PMU_DDRIO1_RET_EN) |
Lin Huang127527f2017-05-22 10:29:59 +0800869 BIT(PMU_DDRIO1_RET_DE_REQ) |
Tony Xie42e113e2016-07-16 11:16:51 +0800870 BIT(PMU_DDRIO_RET_HW_DE_REQ) |
Caesar Wang5339d182016-10-27 01:13:34 +0800871 BIT(PMU_CENTER_PD_EN) |
Lin Huang88dd1232017-05-16 16:40:46 +0800872 BIT(PMU_PERILP_PD_EN) |
873 BIT(PMU_CLK_PERILP_SRC_GATE_EN) |
Tony Xie42e113e2016-07-16 11:16:51 +0800874 BIT(PMU_PLL_PD_EN) |
875 BIT(PMU_CLK_CENTER_SRC_GATE_EN) |
876 BIT(PMU_OSC_DIS) |
877 BIT(PMU_PMU_USE_LF);
Caesar Wang59e41b52016-04-10 14:11:07 +0800878
Tony Xie42e113e2016-07-16 11:16:51 +0800879 mmio_setbits_32(PMU_BASE + PMU_WKUP_CFG4, BIT(PMU_GPIO_WKUP_EN));
Tony Xief6118cc2016-01-15 17:17:32 +0800880 mmio_write_32(PMU_BASE + PMU_PWRMODE_CON, slp_mode_cfg);
Caesar Wang59e41b52016-04-10 14:11:07 +0800881
Caesar Wangfbaa3602016-08-09 08:15:44 +0800882 mmio_write_32(PMU_BASE + PMU_PLL_CON, PLL_PD_HW);
883 mmio_write_32(PMUGRF_BASE + PMUGRF_SOC_CON0, EXTERNAL_32K);
884 mmio_write_32(PMUGRF_BASE, IOMUX_CLK_32K); /* 32k iomux */
885}
886
Tony Xie42e113e2016-07-16 11:16:51 +0800887static void set_hw_idle(uint32_t hw_idle)
888{
889 mmio_setbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle);
890}
891
892static void clr_hw_idle(uint32_t hw_idle)
893{
894 mmio_clrbits_32(PMU_BASE + PMU_BUS_CLR, hw_idle);
Tony Xief6118cc2016-01-15 17:17:32 +0800895}
896
Caesar Wang5045a1c2016-09-10 02:47:53 +0800897static uint32_t iomux_status[12];
898static uint32_t pull_mode_status[12];
899static uint32_t gpio_direction[3];
900static uint32_t gpio_2_4_clk_gate;
901
902static void suspend_apio(void)
903{
904 struct apio_info *suspend_apio;
905 int i;
906
907 suspend_apio = plat_get_rockchip_suspend_apio();
908
909 if (!suspend_apio)
910 return;
911
912 /* save gpio2 ~ gpio4 iomux and pull mode */
913 for (i = 0; i < 12; i++) {
914 iomux_status[i] = mmio_read_32(GRF_BASE +
915 GRF_GPIO2A_IOMUX + i * 4);
916 pull_mode_status[i] = mmio_read_32(GRF_BASE +
917 GRF_GPIO2A_P + i * 4);
918 }
919
920 /* store gpio2 ~ gpio4 clock gate state */
921 gpio_2_4_clk_gate = (mmio_read_32(CRU_BASE + CRU_CLKGATE_CON(31)) >>
922 PCLK_GPIO2_GATE_SHIFT) & 0x07;
923
924 /* enable gpio2 ~ gpio4 clock gate */
925 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
926 BITS_WITH_WMASK(0, 0x07, PCLK_GPIO2_GATE_SHIFT));
927
928 /* save gpio2 ~ gpio4 direction */
929 gpio_direction[0] = mmio_read_32(GPIO2_BASE + 0x04);
930 gpio_direction[1] = mmio_read_32(GPIO3_BASE + 0x04);
931 gpio_direction[2] = mmio_read_32(GPIO4_BASE + 0x04);
932
933 /* apio1 charge gpio3a0 ~ gpio3c7 */
934 if (suspend_apio->apio1) {
935
936 /* set gpio3a0 ~ gpio3c7 iomux to gpio */
937 mmio_write_32(GRF_BASE + GRF_GPIO3A_IOMUX,
938 REG_SOC_WMSK | GRF_IOMUX_GPIO);
939 mmio_write_32(GRF_BASE + GRF_GPIO3B_IOMUX,
940 REG_SOC_WMSK | GRF_IOMUX_GPIO);
941 mmio_write_32(GRF_BASE + GRF_GPIO3C_IOMUX,
942 REG_SOC_WMSK | GRF_IOMUX_GPIO);
943
944 /* set gpio3a0 ~ gpio3c7 pull mode to pull none */
945 mmio_write_32(GRF_BASE + GRF_GPIO3A_P, REG_SOC_WMSK | 0);
946 mmio_write_32(GRF_BASE + GRF_GPIO3B_P, REG_SOC_WMSK | 0);
947 mmio_write_32(GRF_BASE + GRF_GPIO3C_P, REG_SOC_WMSK | 0);
948
949 /* set gpio3a0 ~ gpio3c7 to input */
950 mmio_clrbits_32(GPIO3_BASE + 0x04, 0x00ffffff);
951 }
952
953 /* apio2 charge gpio2a0 ~ gpio2b4 */
954 if (suspend_apio->apio2) {
955
956 /* set gpio2a0 ~ gpio2b4 iomux to gpio */
957 mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX,
958 REG_SOC_WMSK | GRF_IOMUX_GPIO);
959 mmio_write_32(GRF_BASE + GRF_GPIO2B_IOMUX,
960 REG_SOC_WMSK | GRF_IOMUX_GPIO);
961
962 /* set gpio2a0 ~ gpio2b4 pull mode to pull none */
963 mmio_write_32(GRF_BASE + GRF_GPIO2A_P, REG_SOC_WMSK | 0);
964 mmio_write_32(GRF_BASE + GRF_GPIO2B_P, REG_SOC_WMSK | 0);
965
966 /* set gpio2a0 ~ gpio2b4 to input */
967 mmio_clrbits_32(GPIO2_BASE + 0x04, 0x00001fff);
968 }
969
970 /* apio3 charge gpio2c0 ~ gpio2d4*/
971 if (suspend_apio->apio3) {
972
973 /* set gpio2a0 ~ gpio2b4 iomux to gpio */
974 mmio_write_32(GRF_BASE + GRF_GPIO2C_IOMUX,
975 REG_SOC_WMSK | GRF_IOMUX_GPIO);
976 mmio_write_32(GRF_BASE + GRF_GPIO2D_IOMUX,
977 REG_SOC_WMSK | GRF_IOMUX_GPIO);
978
979 /* set gpio2c0 ~ gpio2d4 pull mode to pull none */
980 mmio_write_32(GRF_BASE + GRF_GPIO2C_P, REG_SOC_WMSK | 0);
981 mmio_write_32(GRF_BASE + GRF_GPIO2D_P, REG_SOC_WMSK | 0);
982
983 /* set gpio2c0 ~ gpio2d4 to input */
984 mmio_clrbits_32(GPIO2_BASE + 0x04, 0x1fff0000);
985 }
986
987 /* apio4 charge gpio4c0 ~ gpio4c7, gpio4d0 ~ gpio4d6 */
988 if (suspend_apio->apio4) {
989
990 /* set gpio4c0 ~ gpio4d6 iomux to gpio */
991 mmio_write_32(GRF_BASE + GRF_GPIO4C_IOMUX,
992 REG_SOC_WMSK | GRF_IOMUX_GPIO);
993 mmio_write_32(GRF_BASE + GRF_GPIO4D_IOMUX,
994 REG_SOC_WMSK | GRF_IOMUX_GPIO);
995
996 /* set gpio4c0 ~ gpio4d6 pull mode to pull none */
997 mmio_write_32(GRF_BASE + GRF_GPIO4C_P, REG_SOC_WMSK | 0);
998 mmio_write_32(GRF_BASE + GRF_GPIO4D_P, REG_SOC_WMSK | 0);
999
1000 /* set gpio4c0 ~ gpio4d6 to input */
1001 mmio_clrbits_32(GPIO4_BASE + 0x04, 0x7fff0000);
1002 }
1003
1004 /* apio5 charge gpio3d0 ~ gpio3d7, gpio4a0 ~ gpio4a7*/
1005 if (suspend_apio->apio5) {
1006 /* set gpio3d0 ~ gpio4a7 iomux to gpio */
1007 mmio_write_32(GRF_BASE + GRF_GPIO3D_IOMUX,
1008 REG_SOC_WMSK | GRF_IOMUX_GPIO);
1009 mmio_write_32(GRF_BASE + GRF_GPIO4A_IOMUX,
1010 REG_SOC_WMSK | GRF_IOMUX_GPIO);
1011
1012 /* set gpio3d0 ~ gpio4a7 pull mode to pull none */
1013 mmio_write_32(GRF_BASE + GRF_GPIO3D_P, REG_SOC_WMSK | 0);
1014 mmio_write_32(GRF_BASE + GRF_GPIO4A_P, REG_SOC_WMSK | 0);
1015
1016 /* set gpio4c0 ~ gpio4d6 to input */
1017 mmio_clrbits_32(GPIO3_BASE + 0x04, 0xff000000);
1018 mmio_clrbits_32(GPIO4_BASE + 0x04, 0x000000ff);
1019 }
1020}
1021
1022static void resume_apio(void)
1023{
1024 struct apio_info *suspend_apio;
1025 int i;
1026
1027 suspend_apio = plat_get_rockchip_suspend_apio();
1028
1029 if (!suspend_apio)
1030 return;
1031
1032 for (i = 0; i < 12; i++) {
1033 mmio_write_32(GRF_BASE + GRF_GPIO2A_P + i * 4,
1034 REG_SOC_WMSK | pull_mode_status[i]);
1035 mmio_write_32(GRF_BASE + GRF_GPIO2A_IOMUX + i * 4,
1036 REG_SOC_WMSK | iomux_status[i]);
1037 }
1038
1039 /* set gpio2 ~ gpio4 direction back to store value */
1040 mmio_write_32(GPIO2_BASE + 0x04, gpio_direction[0]);
1041 mmio_write_32(GPIO3_BASE + 0x04, gpio_direction[1]);
1042 mmio_write_32(GPIO4_BASE + 0x04, gpio_direction[2]);
1043
1044 /* set gpio2 ~ gpio4 clock gate back to store value */
1045 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
1046 BITS_WITH_WMASK(gpio_2_4_clk_gate, 0x07,
1047 PCLK_GPIO2_GATE_SHIFT));
1048}
1049
Caesar Wangef180072016-09-10 02:43:15 +08001050static void suspend_gpio(void)
1051{
1052 struct gpio_info *suspend_gpio;
1053 uint32_t count;
1054 int i;
1055
1056 suspend_gpio = plat_get_rockchip_suspend_gpio(&count);
1057
1058 for (i = 0; i < count; i++) {
1059 gpio_set_value(suspend_gpio[i].index, suspend_gpio[i].polarity);
1060 gpio_set_direction(suspend_gpio[i].index, GPIO_DIR_OUT);
1061 udelay(1);
1062 }
1063}
1064
1065static void resume_gpio(void)
1066{
1067 struct gpio_info *suspend_gpio;
1068 uint32_t count;
1069 int i;
1070
1071 suspend_gpio = plat_get_rockchip_suspend_gpio(&count);
1072
1073 for (i = count - 1; i >= 0; i--) {
1074 gpio_set_value(suspend_gpio[i].index,
1075 !suspend_gpio[i].polarity);
1076 gpio_set_direction(suspend_gpio[i].index, GPIO_DIR_OUT);
1077 udelay(1);
1078 }
1079}
1080
Xing Zheng93280b72016-10-26 21:25:26 +08001081static void m0_configure_suspend(void)
Caesar Wangbb228622016-10-12 01:47:51 +08001082{
Xing Zheng93280b72016-10-26 21:25:26 +08001083 /* set PARAM to M0_FUNC_SUSPEND */
1084 mmio_write_32(M0_PARAM_ADDR + PARAM_M0_FUNC, M0_FUNC_SUSPEND);
Caesar Wangbb228622016-10-12 01:47:51 +08001085}
1086
Lin Huang88dd1232017-05-16 16:40:46 +08001087void sram_save(void)
1088{
1089 size_t text_size = (char *)&__bl31_sram_text_real_end -
1090 (char *)&__bl31_sram_text_start;
1091 size_t data_size = (char *)&__bl31_sram_data_real_end -
1092 (char *)&__bl31_sram_data_start;
1093 size_t incbin_size = (char *)&__sram_incbin_real_end -
1094 (char *)&__sram_incbin_start;
1095
1096 memcpy(&store_sram[0], &__bl31_sram_text_start, text_size);
1097 memcpy(&store_sram[text_size], &__bl31_sram_data_start, data_size);
1098 memcpy(&store_sram[text_size + data_size], &__sram_incbin_start,
1099 incbin_size);
1100}
1101
1102void sram_restore(void)
1103{
1104 size_t text_size = (char *)&__bl31_sram_text_real_end -
1105 (char *)&__bl31_sram_text_start;
1106 size_t data_size = (char *)&__bl31_sram_data_real_end -
1107 (char *)&__bl31_sram_data_start;
1108 size_t incbin_size = (char *)&__sram_incbin_real_end -
1109 (char *)&__sram_incbin_start;
1110
1111 memcpy(&__bl31_sram_text_start, &store_sram[0], text_size);
1112 memcpy(&__bl31_sram_data_start, &store_sram[text_size], data_size);
1113 memcpy(&__sram_incbin_start, &store_sram[text_size + data_size],
1114 incbin_size);
1115}
1116
Lin Huang5a5c2bb2017-06-16 10:43:40 +08001117struct uart_debug {
1118 uint32_t uart_dll;
1119 uint32_t uart_dlh;
1120 uint32_t uart_ier;
1121 uint32_t uart_fcr;
1122 uint32_t uart_mcr;
1123 uint32_t uart_lcr;
1124};
1125
1126#define UART_DLL 0x00
1127#define UART_DLH 0x04
1128#define UART_IER 0x04
1129#define UART_FCR 0x08
1130#define UART_LCR 0x0c
1131#define UART_MCR 0x10
1132#define UARTSRR 0x88
1133
1134#define UART_RESET BIT(0)
1135#define UARTFCR_FIFOEN BIT(0)
1136#define RCVR_FIFO_RESET BIT(1)
1137#define XMIT_FIFO_RESET BIT(2)
1138#define DIAGNOSTIC_MODE BIT(4)
1139#define UARTLCR_DLAB BIT(7)
1140
1141static struct uart_debug uart_save;
1142
1143void suspend_uart(void)
1144{
1145 uart_save.uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
1146 uart_save.uart_ier = mmio_read_32(PLAT_RK_UART_BASE + UART_IER);
1147 uart_save.uart_mcr = mmio_read_32(PLAT_RK_UART_BASE + UART_MCR);
1148 mmio_write_32(PLAT_RK_UART_BASE + UART_LCR,
1149 uart_save.uart_lcr | UARTLCR_DLAB);
1150 uart_save.uart_dll = mmio_read_32(PLAT_RK_UART_BASE + UART_DLL);
1151 uart_save.uart_dlh = mmio_read_32(PLAT_RK_UART_BASE + UART_DLH);
1152 mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
1153}
1154
1155void resume_uart(void)
1156{
1157 uint32_t uart_lcr;
1158
1159 mmio_write_32(PLAT_RK_UART_BASE + UARTSRR,
1160 XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET);
1161
1162 uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
1163 mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, DIAGNOSTIC_MODE);
1164 mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_lcr | UARTLCR_DLAB);
1165 mmio_write_32(PLAT_RK_UART_BASE + UART_DLL, uart_save.uart_dll);
1166 mmio_write_32(PLAT_RK_UART_BASE + UART_DLH, uart_save.uart_dlh);
1167 mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
1168 mmio_write_32(PLAT_RK_UART_BASE + UART_IER, uart_save.uart_ier);
1169 mmio_write_32(PLAT_RK_UART_BASE + UART_FCR, UARTFCR_FIFOEN);
1170 mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, uart_save.uart_mcr);
1171}
1172
Lin Huang2c60b5f2017-05-18 18:04:25 +08001173void save_usbphy(void)
1174{
1175 store_usbphy0[0] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL0);
1176 store_usbphy0[1] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL2);
1177 store_usbphy0[2] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL3);
1178 store_usbphy0[3] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL12);
1179 store_usbphy0[4] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL13);
1180 store_usbphy0[5] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL15);
1181 store_usbphy0[6] = mmio_read_32(GRF_BASE + GRF_USBPHY0_CTRL16);
1182
1183 store_usbphy1[0] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL0);
1184 store_usbphy1[1] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL2);
1185 store_usbphy1[2] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL3);
1186 store_usbphy1[3] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL12);
1187 store_usbphy1[4] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL13);
1188 store_usbphy1[5] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL15);
1189 store_usbphy1[6] = mmio_read_32(GRF_BASE + GRF_USBPHY1_CTRL16);
1190}
1191
1192void restore_usbphy(void)
1193{
1194 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL0,
1195 REG_SOC_WMSK | store_usbphy0[0]);
1196 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL2,
1197 REG_SOC_WMSK | store_usbphy0[1]);
1198 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL3,
1199 REG_SOC_WMSK | store_usbphy0[2]);
1200 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL12,
1201 REG_SOC_WMSK | store_usbphy0[3]);
1202 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL13,
1203 REG_SOC_WMSK | store_usbphy0[4]);
1204 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL15,
1205 REG_SOC_WMSK | store_usbphy0[5]);
1206 mmio_write_32(GRF_BASE + GRF_USBPHY0_CTRL16,
1207 REG_SOC_WMSK | store_usbphy0[6]);
1208
1209 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL0,
1210 REG_SOC_WMSK | store_usbphy1[0]);
1211 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL2,
1212 REG_SOC_WMSK | store_usbphy1[1]);
1213 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL3,
1214 REG_SOC_WMSK | store_usbphy1[2]);
1215 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL12,
1216 REG_SOC_WMSK | store_usbphy1[3]);
1217 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL13,
1218 REG_SOC_WMSK | store_usbphy1[4]);
1219 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL15,
1220 REG_SOC_WMSK | store_usbphy1[5]);
1221 mmio_write_32(GRF_BASE + GRF_USBPHY1_CTRL16,
1222 REG_SOC_WMSK | store_usbphy1[6]);
1223}
1224
1225void grf_register_save(void)
1226{
1227 int i;
1228
1229 store_grf_soc_con0 = mmio_read_32(GRF_BASE + GRF_SOC_CON(0));
1230 store_grf_soc_con1 = mmio_read_32(GRF_BASE + GRF_SOC_CON(1));
1231 store_grf_soc_con2 = mmio_read_32(GRF_BASE + GRF_SOC_CON(2));
1232 store_grf_soc_con3 = mmio_read_32(GRF_BASE + GRF_SOC_CON(3));
1233 store_grf_soc_con4 = mmio_read_32(GRF_BASE + GRF_SOC_CON(4));
1234 store_grf_soc_con7 = mmio_read_32(GRF_BASE + GRF_SOC_CON(7));
1235
1236 for (i = 0; i < 4; i++)
1237 store_grf_ddrc_con[i] =
1238 mmio_read_32(GRF_BASE + GRF_DDRC0_CON0 + i * 4);
1239
1240 store_grf_io_vsel = mmio_read_32(GRF_BASE + GRF_IO_VSEL);
1241}
1242
1243void grf_register_restore(void)
1244{
1245 int i;
1246
1247 mmio_write_32(GRF_BASE + GRF_SOC_CON(0),
1248 REG_SOC_WMSK | store_grf_soc_con0);
1249 mmio_write_32(GRF_BASE + GRF_SOC_CON(1),
1250 REG_SOC_WMSK | store_grf_soc_con1);
1251 mmio_write_32(GRF_BASE + GRF_SOC_CON(2),
1252 REG_SOC_WMSK | store_grf_soc_con2);
1253 mmio_write_32(GRF_BASE + GRF_SOC_CON(3),
1254 REG_SOC_WMSK | store_grf_soc_con3);
1255 mmio_write_32(GRF_BASE + GRF_SOC_CON(4),
1256 REG_SOC_WMSK | store_grf_soc_con4);
1257 mmio_write_32(GRF_BASE + GRF_SOC_CON(7),
1258 REG_SOC_WMSK | store_grf_soc_con7);
1259
1260 for (i = 0; i < 4; i++)
1261 mmio_write_32(GRF_BASE + GRF_DDRC0_CON0 + i * 4,
1262 REG_SOC_WMSK | store_grf_ddrc_con[i]);
1263
1264 mmio_write_32(GRF_BASE + GRF_IO_VSEL, REG_SOC_WMSK | store_grf_io_vsel);
1265}
1266
1267void cru_register_save(void)
1268{
1269 int i;
1270
1271 for (i = 0; i <= CRU_SDIO0_CON1; i = i + 4)
1272 store_cru[i / 4] = mmio_read_32(CRU_BASE + i);
1273}
1274
1275void cru_register_restore(void)
1276{
1277 int i;
1278
1279 for (i = 0; i <= CRU_SDIO0_CON1; i = i + 4) {
1280
1281 /*
1282 * since DPLL, CRU_CLKSEL_CON6 have been restore in
1283 * dmc_resume, ABPLL will resote later, so skip them
1284 */
1285 if ((i == CRU_CLKSEL_CON6) ||
1286 (i >= CRU_PLL_CON(ABPLL_ID, 0) &&
1287 i <= CRU_PLL_CON(DPLL_ID, 5)))
1288 continue;
1289
1290 if ((i == CRU_PLL_CON(ALPLL_ID, 2)) ||
1291 (i == CRU_PLL_CON(CPLL_ID, 2)) ||
1292 (i == CRU_PLL_CON(GPLL_ID, 2)) ||
1293 (i == CRU_PLL_CON(NPLL_ID, 2)) ||
1294 (i == CRU_PLL_CON(VPLL_ID, 2)))
1295 mmio_write_32(CRU_BASE + i, store_cru[i / 4]);
1296 /*
1297 * CRU_GLB_CNT_TH and CRU_CLKSEL_CON97~CRU_CLKSEL_CON107
1298 * not need do high 16bit mask
1299 */
1300 else if ((i > 0x27c && i < 0x2b0) || (i == 0x508))
1301 mmio_write_32(CRU_BASE + i, store_cru[i / 4]);
1302 else
1303 mmio_write_32(CRU_BASE + i,
1304 REG_SOC_WMSK | store_cru[i / 4]);
1305 }
1306}
1307
1308void wdt_register_save(void)
1309{
1310 int i;
1311
1312 for (i = 0; i < 2; i++) {
1313 store_wdt0[i] = mmio_read_32(WDT0_BASE + i * 4);
1314 store_wdt1[i] = mmio_read_32(WDT1_BASE + i * 4);
1315 }
1316}
1317
1318void wdt_register_restore(void)
1319{
1320 int i;
1321
1322 for (i = 0; i < 2; i++) {
1323 mmio_write_32(WDT0_BASE + i * 4, store_wdt0[i]);
1324 mmio_write_32(WDT1_BASE + i * 4, store_wdt1[i]);
1325 }
1326}
1327
tony.xie422d51c2017-03-01 11:05:17 +08001328int rockchip_soc_sys_pwr_dm_suspend(void)
Tony Xief6118cc2016-01-15 17:17:32 +08001329{
Tony Xie42e113e2016-07-16 11:16:51 +08001330 uint32_t wait_cnt = 0;
1331 uint32_t status = 0;
1332
Derek Basehoree13bc542017-02-24 14:31:36 +08001333 ddr_prepare_for_sys_suspend();
Lin Huang1f8fdeb2017-05-17 16:14:37 +08001334 dmc_suspend();
Caesar Wang5339d182016-10-27 01:13:34 +08001335 pmu_scu_b_pwrdn();
1336
Derek Basehore2707c3d2018-01-23 17:18:57 -08001337 gicv3_rdistif_save(plat_my_core_pos(), &rdist_ctx);
1338 gicv3_distif_save(&dist_ctx);
1339
Lin Huang2c60b5f2017-05-18 18:04:25 +08001340 /* need to save usbphy before shutdown PERIHP PD */
1341 save_usbphy();
1342
Tony Xie42e113e2016-07-16 11:16:51 +08001343 pmu_power_domains_suspend();
1344 set_hw_idle(BIT(PMU_CLR_CENTER1) |
1345 BIT(PMU_CLR_ALIVE) |
1346 BIT(PMU_CLR_MSCH0) |
1347 BIT(PMU_CLR_MSCH1) |
1348 BIT(PMU_CLR_CCIM0) |
1349 BIT(PMU_CLR_CCIM1) |
1350 BIT(PMU_CLR_CENTER) |
Lin Huang88dd1232017-05-16 16:40:46 +08001351 BIT(PMU_CLR_PERILP) |
1352 BIT(PMU_CLR_PERILPM0) |
Tony Xie42e113e2016-07-16 11:16:51 +08001353 BIT(PMU_CLR_GIC));
Lin Huang127527f2017-05-22 10:29:59 +08001354 set_pmu_rsthold();
Tony Xief6118cc2016-01-15 17:17:32 +08001355 sys_slp_config();
Caesar Wangbb228622016-10-12 01:47:51 +08001356
Xing Zheng93280b72016-10-26 21:25:26 +08001357 m0_configure_suspend();
1358 m0_start();
Caesar Wangbb228622016-10-12 01:47:51 +08001359
Tony Xief6118cc2016-01-15 17:17:32 +08001360 pmu_sgrf_rst_hld();
Caesar Wang59e41b52016-04-10 14:11:07 +08001361
Xing Zheng22a98712017-02-24 14:56:41 +08001362 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
Lin Huang30e43392017-05-04 16:02:45 +08001363 ((uintptr_t)&pmu_cpuson_entrypoint >>
1364 CPU_BOOT_ADDR_ALIGN) | CPU_BOOT_ADDR_WMASK);
Caesar Wang59e41b52016-04-10 14:11:07 +08001365
Caesar Wang59e41b52016-04-10 14:11:07 +08001366 mmio_write_32(PMU_BASE + PMU_ADB400_CON,
1367 BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) |
1368 BIT_WITH_WMSK(PMU_PWRDWN_REQ_CORE_B_SW) |
1369 BIT_WITH_WMSK(PMU_PWRDWN_REQ_GIC2_CORE_B_SW));
1370 dsb();
Tony Xie42e113e2016-07-16 11:16:51 +08001371 status = BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST) |
1372 BIT(PMU_PWRDWN_REQ_CORE_B_SW_ST) |
1373 BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST);
1374 while ((mmio_read_32(PMU_BASE +
1375 PMU_ADB400_ST) & status) != status) {
1376 wait_cnt++;
1377 if (wait_cnt >= MAX_WAIT_COUNT) {
1378 ERROR("%s:wait cluster-b l2(%x)\n", __func__,
1379 mmio_read_32(PMU_BASE + PMU_ADB400_ST));
1380 panic();
1381 }
Derek Basehore1d605f72018-01-23 16:24:43 -08001382 udelay(1);
Tony Xie42e113e2016-07-16 11:16:51 +08001383 }
Caesar Wang59e41b52016-04-10 14:11:07 +08001384 mmio_setbits_32(PMU_BASE + PMU_PWRDN_CON, BIT(PMU_SCU_B_PWRDWN_EN));
Caesar Wang5339d182016-10-27 01:13:34 +08001385
Caesar Wang813a89a2016-11-04 21:13:01 +08001386 secure_watchdog_disable();
1387
Caesar Wange67b1de2016-08-17 17:22:10 -07001388 /*
1389 * Disabling PLLs/PWM/DVFS is approaching WFI which is
1390 * the last steps in suspend.
1391 */
Caesar Wanged6b9a52016-08-11 02:11:45 +08001392 disable_dvfs_plls();
1393 disable_pwms();
1394 disable_nodvfs_plls();
Caesar Wangbb228622016-10-12 01:47:51 +08001395
Caesar Wang5045a1c2016-09-10 02:47:53 +08001396 suspend_apio();
Caesar Wangef180072016-09-10 02:43:15 +08001397 suspend_gpio();
Lin Huang5a5c2bb2017-06-16 10:43:40 +08001398 suspend_uart();
Lin Huang2c60b5f2017-05-18 18:04:25 +08001399 grf_register_save();
1400 cru_register_save();
1401 wdt_register_save();
Lin Huang88dd1232017-05-16 16:40:46 +08001402 sram_save();
Lin Huang2c60b5f2017-05-18 18:04:25 +08001403 plat_rockchip_save_gpio();
1404
Tony Xief6118cc2016-01-15 17:17:32 +08001405 return 0;
1406}
1407
tony.xie422d51c2017-03-01 11:05:17 +08001408int rockchip_soc_sys_pwr_dm_resume(void)
Tony Xief6118cc2016-01-15 17:17:32 +08001409{
Tony Xie42e113e2016-07-16 11:16:51 +08001410 uint32_t wait_cnt = 0;
1411 uint32_t status = 0;
1412
Lin Huang2c60b5f2017-05-18 18:04:25 +08001413 plat_rockchip_restore_gpio();
1414 wdt_register_restore();
1415 cru_register_restore();
1416 grf_register_restore();
Lin Huang5a5c2bb2017-06-16 10:43:40 +08001417 resume_uart();
Caesar Wang5045a1c2016-09-10 02:47:53 +08001418 resume_apio();
Caesar Wangef180072016-09-10 02:43:15 +08001419 resume_gpio();
Caesar Wanged6b9a52016-08-11 02:11:45 +08001420 enable_nodvfs_plls();
1421 enable_pwms();
1422 /* PWM regulators take time to come up; give 300us to be safe. */
1423 udelay(300);
1424 enable_dvfs_plls();
Tony Xie42e113e2016-07-16 11:16:51 +08001425
Xing Zheng22a98712017-02-24 14:56:41 +08001426 secure_watchdog_enable();
Lin Huangb162fb42017-06-14 17:24:29 +08001427 secure_sgrf_init();
1428 secure_sgrf_ddr_rgn_init();
Caesar Wang813a89a2016-11-04 21:13:01 +08001429
Caesar Wang5339d182016-10-27 01:13:34 +08001430 /* restore clk_ddrc_bpll_src_en gate */
1431 mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(3),
1432 BITS_WITH_WMASK(clk_ddrc_save, 0xff, 0));
1433
Caesar Wange67b1de2016-08-17 17:22:10 -07001434 /*
1435 * The wakeup status is not cleared by itself, we need to clear it
1436 * manually. Otherwise we will alway query some interrupt next time.
1437 *
1438 * NOTE: If the kernel needs to query this, we might want to stash it
1439 * somewhere.
1440 */
1441 mmio_write_32(PMU_BASE + PMU_WAKEUP_STATUS, 0xffffffff);
Caesar Wange67b1de2016-08-17 17:22:10 -07001442 mmio_write_32(PMU_BASE + PMU_WKUP_CFG4, 0x00);
1443
Xing Zheng22a98712017-02-24 14:56:41 +08001444 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
Caesar Wang59e41b52016-04-10 14:11:07 +08001445 (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) |
1446 CPU_BOOT_ADDR_WMASK);
1447
Caesar Wang59e41b52016-04-10 14:11:07 +08001448 mmio_write_32(PMU_BASE + PMU_CCI500_CON,
1449 WMSK_BIT(PMU_CLR_PREQ_CCI500_HW) |
1450 WMSK_BIT(PMU_CLR_QREQ_CCI500_HW) |
1451 WMSK_BIT(PMU_QGATING_CCI500_CFG));
Tony Xie42e113e2016-07-16 11:16:51 +08001452 dsb();
1453 mmio_clrbits_32(PMU_BASE + PMU_PWRDN_CON,
1454 BIT(PMU_SCU_B_PWRDWN_EN));
Caesar Wang59e41b52016-04-10 14:11:07 +08001455
1456 mmio_write_32(PMU_BASE + PMU_ADB400_CON,
Tony Xie42e113e2016-07-16 11:16:51 +08001457 WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW) |
1458 WMSK_BIT(PMU_PWRDWN_REQ_CORE_B_SW) |
1459 WMSK_BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW) |
Caesar Wang59e41b52016-04-10 14:11:07 +08001460 WMSK_BIT(PMU_CLR_CORE_L_HW) |
1461 WMSK_BIT(PMU_CLR_CORE_L_2GIC_HW) |
1462 WMSK_BIT(PMU_CLR_GIC2_CORE_L_HW));
1463
Tony Xie42e113e2016-07-16 11:16:51 +08001464 status = BIT(PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST) |
1465 BIT(PMU_PWRDWN_REQ_CORE_B_SW_ST) |
1466 BIT(PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST);
Caesar Wang59e41b52016-04-10 14:11:07 +08001467
Tony Xie42e113e2016-07-16 11:16:51 +08001468 while ((mmio_read_32(PMU_BASE +
1469 PMU_ADB400_ST) & status)) {
1470 wait_cnt++;
1471 if (wait_cnt >= MAX_WAIT_COUNT) {
1472 ERROR("%s:wait cluster-b l2(%x)\n", __func__,
1473 mmio_read_32(PMU_BASE + PMU_ADB400_ST));
1474 panic();
1475 }
Derek Basehore1d605f72018-01-23 16:24:43 -08001476 udelay(1);
Tony Xie42e113e2016-07-16 11:16:51 +08001477 }
Caesar Wang59e41b52016-04-10 14:11:07 +08001478
Caesar Wangc7aaa782016-08-09 07:53:41 +08001479 pmu_sgrf_rst_hld_release();
Caesar Wang59e41b52016-04-10 14:11:07 +08001480 pmu_scu_b_pwrup();
Tony Xie42e113e2016-07-16 11:16:51 +08001481 pmu_power_domains_resume();
Caesar Wang5339d182016-10-27 01:13:34 +08001482
Caesar Wang5339d182016-10-27 01:13:34 +08001483 restore_abpll();
Lin Huang127527f2017-05-22 10:29:59 +08001484 restore_pmu_rsthold();
Tony Xie42e113e2016-07-16 11:16:51 +08001485 clr_hw_idle(BIT(PMU_CLR_CENTER1) |
1486 BIT(PMU_CLR_ALIVE) |
1487 BIT(PMU_CLR_MSCH0) |
1488 BIT(PMU_CLR_MSCH1) |
1489 BIT(PMU_CLR_CCIM0) |
1490 BIT(PMU_CLR_CCIM1) |
1491 BIT(PMU_CLR_CENTER) |
Lin Huang88dd1232017-05-16 16:40:46 +08001492 BIT(PMU_CLR_PERILP) |
1493 BIT(PMU_CLR_PERILPM0) |
Tony Xie42e113e2016-07-16 11:16:51 +08001494 BIT(PMU_CLR_GIC));
Caesar Wanga8216ab2016-09-13 11:15:00 +08001495
Derek Basehore2707c3d2018-01-23 17:18:57 -08001496 gicv3_distif_init_restore(&dist_ctx);
1497 gicv3_rdistif_init_restore(plat_my_core_pos(), &rdist_ctx);
Caesar Wanga8216ab2016-09-13 11:15:00 +08001498 plat_rockchip_gic_cpuif_enable();
Xing Zheng93280b72016-10-26 21:25:26 +08001499 m0_stop();
Caesar Wangbb228622016-10-12 01:47:51 +08001500
Lin Huang2c60b5f2017-05-18 18:04:25 +08001501 restore_usbphy();
1502
Derek Basehoree13bc542017-02-24 14:31:36 +08001503 ddr_prepare_for_sys_resume();
1504
Tony Xief6118cc2016-01-15 17:17:32 +08001505 return 0;
1506}
1507
tony.xie422d51c2017-03-01 11:05:17 +08001508void __dead2 rockchip_soc_soft_reset(void)
Caesar Wanga5dc64d2016-05-25 19:04:47 +08001509{
1510 struct gpio_info *rst_gpio;
1511
Caesar Wangef180072016-09-10 02:43:15 +08001512 rst_gpio = plat_get_rockchip_gpio_reset();
Caesar Wanga5dc64d2016-05-25 19:04:47 +08001513
1514 if (rst_gpio) {
1515 gpio_set_direction(rst_gpio->index, GPIO_DIR_OUT);
1516 gpio_set_value(rst_gpio->index, rst_gpio->polarity);
1517 } else {
1518 soc_global_soft_reset();
1519 }
1520
1521 while (1)
1522 ;
1523}
1524
tony.xie422d51c2017-03-01 11:05:17 +08001525void __dead2 rockchip_soc_system_off(void)
Caesar Wangd1b9d2d2016-05-25 19:05:19 +08001526{
1527 struct gpio_info *poweroff_gpio;
1528
Caesar Wangef180072016-09-10 02:43:15 +08001529 poweroff_gpio = plat_get_rockchip_gpio_poweroff();
Caesar Wangd1b9d2d2016-05-25 19:05:19 +08001530
1531 if (poweroff_gpio) {
1532 /*
1533 * if use tsadc over temp pin(GPIO1A6) as shutdown gpio,
1534 * need to set this pin iomux back to gpio function
1535 */
1536 if (poweroff_gpio->index == TSADC_INT_PIN) {
1537 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO1A_IOMUX,
1538 GPIO1A6_IOMUX);
1539 }
1540 gpio_set_direction(poweroff_gpio->index, GPIO_DIR_OUT);
1541 gpio_set_value(poweroff_gpio->index, poweroff_gpio->polarity);
1542 } else {
1543 WARN("Do nothing when system off\n");
1544 }
1545
1546 while (1)
1547 ;
1548}
1549
Lin Huang30e43392017-05-04 16:02:45 +08001550void rockchip_plat_mmu_el3(void)
1551{
1552 size_t sram_size;
1553
1554 /* sram.text size */
1555 sram_size = (char *)&__bl31_sram_text_end -
1556 (char *)&__bl31_sram_text_start;
1557 mmap_add_region((unsigned long)&__bl31_sram_text_start,
1558 (unsigned long)&__bl31_sram_text_start,
1559 sram_size, MT_MEMORY | MT_RO | MT_SECURE);
1560
1561 /* sram.data size */
1562 sram_size = (char *)&__bl31_sram_data_end -
1563 (char *)&__bl31_sram_data_start;
1564 mmap_add_region((unsigned long)&__bl31_sram_data_start,
1565 (unsigned long)&__bl31_sram_data_start,
1566 sram_size, MT_MEMORY | MT_RW | MT_SECURE);
1567
1568 sram_size = (char *)&__bl31_sram_stack_end -
1569 (char *)&__bl31_sram_stack_start;
1570 mmap_add_region((unsigned long)&__bl31_sram_stack_start,
1571 (unsigned long)&__bl31_sram_stack_start,
1572 sram_size, MT_MEMORY | MT_RW | MT_SECURE);
1573
1574 sram_size = (char *)&__sram_incbin_end - (char *)&__sram_incbin_start;
1575 mmap_add_region((unsigned long)&__sram_incbin_start,
1576 (unsigned long)&__sram_incbin_start,
1577 sram_size, MT_NON_CACHEABLE | MT_RW | MT_SECURE);
1578}
1579
Tony Xief6118cc2016-01-15 17:17:32 +08001580void plat_rockchip_pmu_init(void)
1581{
1582 uint32_t cpu;
1583
1584 rockchip_pd_lock_init();
Tony Xief6118cc2016-01-15 17:17:32 +08001585
Caesar Wang59e41b52016-04-10 14:11:07 +08001586 /* register requires 32bits mode, switch it to 32 bits */
1587 cpu_warm_boot_addr = (uint64_t)platform_cpu_warmboot;
1588
Tony Xief6118cc2016-01-15 17:17:32 +08001589 for (cpu = 0; cpu < PLATFORM_CORE_COUNT; cpu++)
1590 cpuson_flags[cpu] = 0;
1591
Tony Xie42e113e2016-07-16 11:16:51 +08001592 for (cpu = 0; cpu < PLATFORM_CLUSTER_COUNT; cpu++)
1593 clst_warmboot_data[cpu] = 0;
1594
Tony Xie42e113e2016-07-16 11:16:51 +08001595 /* config cpu's warm boot address */
Xing Zheng22a98712017-02-24 14:56:41 +08001596 mmio_write_32(SGRF_BASE + SGRF_SOC_CON(1),
Caesar Wang59e41b52016-04-10 14:11:07 +08001597 (cpu_warm_boot_addr >> CPU_BOOT_ADDR_ALIGN) |
Tony Xief6118cc2016-01-15 17:17:32 +08001598 CPU_BOOT_ADDR_WMASK);
Tony Xie42e113e2016-07-16 11:16:51 +08001599 mmio_write_32(PMU_BASE + PMU_NOC_AUTO_ENA, NOC_AUTO_ENABLE);
Tony Xief6118cc2016-01-15 17:17:32 +08001600
Caesar Wang3e8548b2016-08-25 06:31:32 +08001601 /*
1602 * Enable Schmitt trigger for better 32 kHz input signal, which is
1603 * important for suspend/resume reliability among other things.
1604 */
1605 mmio_write_32(PMUGRF_BASE + PMUGRF_GPIO0A_SMT, GPIO0A0_SMT_ENABLE);
1606
Caesar Wang34d18d32016-08-25 06:29:46 +08001607 init_pmu_counts();
1608
Tony Xief6118cc2016-01-15 17:17:32 +08001609 nonboot_cpus_off();
Caesar Wang59e41b52016-04-10 14:11:07 +08001610
Tony Xief6118cc2016-01-15 17:17:32 +08001611 INFO("%s(%d): pd status %x\n", __func__, __LINE__,
1612 mmio_read_32(PMU_BASE + PMU_PWRDN_ST));
1613}