rockchip/rk3399: set ddr clock source back to dpll when ddr resume
when logic power rail shutdown, CRU register will back to reset
value, ddr use abpll as clock source when do suspend, we need to save
and dpll value in pmusram, then set back these ddr clock back to dpll
when dddr resume.
Change-Id: I95dc0173649e8515859cfa46b40a606e0cc2fe3f
Signed-off-by: Lin Huang <hl@rock-chips.com>
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c
index 635dda6..d97b046 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c
@@ -1138,7 +1138,7 @@
uint32_t status = 0;
ddr_prepare_for_sys_suspend();
- dmc_save();
+ dmc_suspend();
pmu_scu_b_pwrdn();
pmu_power_domains_suspend();
@@ -1269,8 +1269,6 @@
pmu_scu_b_pwrup();
pmu_power_domains_resume();
- restore_dpll();
- sram_func_set_ddrctl_pll(DPLL_ID);
restore_abpll();
clr_hw_idle(BIT(PMU_CLR_CENTER1) |