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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +00002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handleyed6ff952014-05-14 17:44:19 +01007#include <platform_def.h>
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +00008#include <xlat_tables_defs.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
10OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
11OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000012ENTRY(bl1_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010013
14MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010015 ROM (rx): ORIGIN = BL1_RO_BASE, LENGTH = BL1_RO_LIMIT - BL1_RO_BASE
16 RAM (rwx): ORIGIN = BL1_RW_BASE, LENGTH = BL1_RW_LIMIT - BL1_RW_BASE
Achin Gupta4f6ad662013-10-25 09:08:21 +010017}
18
19SECTIONS
20{
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010021 . = BL1_RO_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000022 ASSERT(. == ALIGN(PAGE_SIZE),
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010023 "BL1_RO_BASE address is not aligned on a page boundary.")
24
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010025#if SEPARATE_CODE_AND_RODATA
26 .text . : {
27 __TEXT_START__ = .;
28 *bl1_entrypoint.o(.text*)
29 *(.text*)
30 *(.vectors)
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000031 . = NEXT(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010032 __TEXT_END__ = .;
33 } >ROM
34
35 .rodata . : {
36 __RODATA_START__ = .;
37 *(.rodata*)
38
39 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
40 . = ALIGN(8);
41 __PARSER_LIB_DESCS_START__ = .;
42 KEEP(*(.img_parser_lib_descs))
43 __PARSER_LIB_DESCS_END__ = .;
44
45 /*
46 * Ensure 8-byte alignment for cpu_ops so that its fields are also
47 * aligned. Also ensure cpu_ops inclusion.
48 */
49 . = ALIGN(8);
50 __CPU_OPS_START__ = .;
51 KEEP(*(cpu_ops))
52 __CPU_OPS_END__ = .;
53
54 /*
55 * No need to pad out the .rodata section to a page boundary. Next is
56 * the .data section, which can mapped in ROM with the same memory
57 * attributes as the .rodata section.
58 */
59 __RODATA_END__ = .;
60 } >ROM
61#else
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010062 ro . : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000063 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000064 *bl1_entrypoint.o(.text*)
65 *(.text*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000066 *(.rodata*)
Soby Mathewc704cbc2014-08-14 11:33:56 +010067
Juan Castillo8e55d932015-04-02 09:48:16 +010068 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
69 . = ALIGN(8);
70 __PARSER_LIB_DESCS_START__ = .;
71 KEEP(*(.img_parser_lib_descs))
72 __PARSER_LIB_DESCS_END__ = .;
73
Soby Mathewc704cbc2014-08-14 11:33:56 +010074 /*
75 * Ensure 8-byte alignment for cpu_ops so that its fields are also
76 * aligned. Also ensure cpu_ops inclusion.
77 */
78 . = ALIGN(8);
79 __CPU_OPS_START__ = .;
80 KEEP(*(cpu_ops))
81 __CPU_OPS_END__ = .;
82
Achin Guptab739f222014-01-18 16:50:09 +000083 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000084 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +010085 } >ROM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010086#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +010087
Soby Mathewc704cbc2014-08-14 11:33:56 +010088 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
89 "cpu_ops not defined for this platform.")
90
Douglas Raillard306593d2017-02-24 18:14:15 +000091 . = BL1_RW_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000092 ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE),
Douglas Raillard306593d2017-02-24 18:14:15 +000093 "BL1_RW_BASE address is not aligned on a page boundary.")
94
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000095 /*
96 * The .data section gets copied from ROM to RAM at runtime.
Douglas Raillard306593d2017-02-24 18:14:15 +000097 * Its LMA should be 16-byte aligned to allow efficient copying of 16-bytes
98 * aligned regions in it.
Sandrine Bailleuxf7488062014-05-22 15:21:35 +010099 * Its VMA must be page-aligned as it marks the first read/write page.
Douglas Raillard306593d2017-02-24 18:14:15 +0000100 *
101 * It must be placed at a lower address than the stacks if the stack
102 * protector is enabled. Alternatively, the .data.stack_protector_canary
103 * section can be placed independently of the main .data section.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000104 */
Sandrine Bailleuxf7488062014-05-22 15:21:35 +0100105 .data . : ALIGN(16) {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100106 __DATA_RAM_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +0000107 *(.data*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000108 __DATA_RAM_END__ = .;
109 } >RAM AT>ROM
Achin Gupta4f6ad662013-10-25 09:08:21 +0100110
Sandrine Bailleuxf7488062014-05-22 15:21:35 +0100111 stacks . (NOLOAD) : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000112 __STACKS_START__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100113 *(tzfw_normal_stacks)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000114 __STACKS_END__ = .;
115 } >RAM
116
117 /*
118 * The .bss section gets initialised to 0 at runtime.
Douglas Raillard21362a92016-12-02 13:51:54 +0000119 * Its base address should be 16-byte aligned for better performance of the
120 * zero-initialization code.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000121 */
122 .bss : ALIGN(16) {
123 __BSS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +0000124 *(.bss*)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000125 *(COMMON)
126 __BSS_END__ = .;
127 } >RAM
Achin Gupta4f6ad662013-10-25 09:08:21 +0100128
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000129 /*
Achin Guptaa0cd9892014-02-09 13:30:38 +0000130 * The xlat_table section is for full, aligned page tables (4K).
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000131 * Removing them from .bss avoids forcing 4K alignment on
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +0000132 * the .bss section. The tables are initialized to zero by the translation
133 * tables library.
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000134 */
135 xlat_table (NOLOAD) : {
136 *(xlat_table)
137 } >RAM
138
Soby Mathew2ae20432015-01-08 18:02:44 +0000139#if USE_COHERENT_MEM
Jeenu Viswambharan74cbb832014-02-17 17:26:51 +0000140 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000141 * The base address of the coherent memory section must be page-aligned (4K)
142 * to guarantee that the coherent data are stored on their own pages and
143 * are not mixed with normal data. This is required to set up the correct
144 * memory attributes for the coherent data page tables.
145 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000146 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000147 __COHERENT_RAM_START__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100148 *(tzfw_coherent_mem)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000149 __COHERENT_RAM_END_UNALIGNED__ = .;
150 /*
151 * Memory page(s) mapped to this section will be marked
152 * as device memory. No other unexpected data must creep in.
153 * Ensure the rest of the current memory page is unused.
154 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000155 . = NEXT(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000156 __COHERENT_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100157 } >RAM
Soby Mathew2ae20432015-01-08 18:02:44 +0000158#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100159
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000160 __BL1_RAM_START__ = ADDR(.data);
161 __BL1_RAM_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100162
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000163 __DATA_ROM_START__ = LOADADDR(.data);
164 __DATA_SIZE__ = SIZEOF(.data);
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100165
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100166 /*
167 * The .data section is the last PROGBITS section so its end marks the end
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100168 * of BL1's actual content in Trusted ROM.
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100169 */
Sandrine Bailleux6c2daed2016-06-15 13:53:50 +0100170 __BL1_ROM_END__ = __DATA_ROM_START__ + __DATA_SIZE__;
171 ASSERT(__BL1_ROM_END__ <= BL1_RO_LIMIT,
172 "BL1's ROM content has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100173
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000174 __BSS_SIZE__ = SIZEOF(.bss);
175
Soby Mathew2ae20432015-01-08 18:02:44 +0000176#if USE_COHERENT_MEM
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000177 __COHERENT_RAM_UNALIGNED_SIZE__ =
178 __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
Soby Mathew2ae20432015-01-08 18:02:44 +0000179#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100180
Sandrine Bailleux6c8b3592014-05-22 15:28:26 +0100181 ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
Achin Gupta4f6ad662013-10-25 09:08:21 +0100182}