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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diazcbccdbf2019-01-21 11:53:29 +00002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
9#include <common/debug.h>
10#include <drivers/arm/cci.h>
11#include <drivers/arm/ccn.h>
12#include <drivers/arm/gicv2.h>
13#include <lib/mmio.h>
14#include <lib/xlat_tables/xlat_tables_compat.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000015#include <plat/arm/common/arm_config.h>
16#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <plat/common/platform.h>
Antonio Nino Diaza320ecd2019-01-15 14:19:50 +000018#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <services/secure_partition.h>
20
Roberto Vargas2ca18d92018-02-12 12:36:17 +000021#include "fvp_private.h"
Achin Gupta4f6ad662013-10-25 09:08:21 +010022
Achin Gupta1fa7eb62015-11-03 14:18:34 +000023/* Defines for GIC Driver build time selection */
24#define FVP_GICV2 1
25#define FVP_GICV3 2
Achin Gupta1fa7eb62015-11-03 14:18:34 +000026
Achin Gupta4f6ad662013-10-25 09:08:21 +010027/*******************************************************************************
Dan Handley2b6b5742015-03-19 19:17:53 +000028 * arm_config holds the characteristics of the differences between the three FVP
29 * platforms (Base, A53_A57 & Foundation). It will be populated during cold boot
Vikram Kanigirifbb13012016-02-15 11:54:14 +000030 * at each boot stage by the primary before enabling the MMU (to allow
31 * interconnect configuration) & used thereafter. Each BL will have its own copy
32 * to allow independent operation.
Achin Gupta4f6ad662013-10-25 09:08:21 +010033 ******************************************************************************/
Dan Handley2b6b5742015-03-19 19:17:53 +000034arm_config_t arm_config;
Soby Mathewb08bc042014-09-03 17:48:44 +010035
36#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
37 DEVICE0_SIZE, \
38 MT_DEVICE | MT_RW | MT_SECURE)
39
40#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
41 DEVICE1_SIZE, \
42 MT_DEVICE | MT_RW | MT_SECURE)
43
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010044/*
45 * Need to be mapped with write permissions in order to set a new non-volatile
46 * counter value.
47 */
Juan Castillo31a68f02015-04-14 12:49:03 +010048#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
49 DEVICE2_SIZE, \
Antonio Nino Diaz9d602fe2016-05-20 14:14:16 +010050 MT_DEVICE | MT_RW | MT_SECURE)
Juan Castillo31a68f02015-04-14 12:49:03 +010051
Jon Medhurstb1eb0932014-02-26 16:27:53 +000052/*
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +010053 * Table of memory regions for various BL stages to map using the MMU.
Roberto Vargas344ff022018-10-19 16:44:18 +010054 * This doesn't include Trusted SRAM as setup_page_tables() already takes care
55 * of mapping it.
Sandrine Bailleux889ca032016-06-14 17:01:00 +010056 *
57 * The flash needs to be mapped as writable in order to erase the FIP's Table of
58 * Contents in case of unrecoverable error (see plat_error_handler()).
Jon Medhurstb1eb0932014-02-26 16:27:53 +000059 */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090060#ifdef IMAGE_BL1
Dan Handley2b6b5742015-03-19 19:17:53 +000061const mmap_region_t plat_arm_mmap[] = {
62 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +010063 V2M_MAP_FLASH0_RW,
Dan Handley2b6b5742015-03-19 19:17:53 +000064 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +010065 MAP_DEVICE0,
66 MAP_DEVICE1,
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010067#if TRUSTED_BOARD_BOOT
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010068 /* To access the Root of Trust Public Key registers. */
69 MAP_DEVICE2,
70 /* Map DRAM to authenticate NS_BL2U image. */
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010071 ARM_MAP_NS_DRAM1,
72#endif
Soby Mathewb08bc042014-09-03 17:48:44 +010073 {0}
74};
75#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090076#ifdef IMAGE_BL2
Dan Handley2b6b5742015-03-19 19:17:53 +000077const mmap_region_t plat_arm_mmap[] = {
78 ARM_MAP_SHARED_RAM,
Juan Castillob6132f12015-10-06 14:01:35 +010079 V2M_MAP_FLASH0_RW,
Dan Handley2b6b5742015-03-19 19:17:53 +000080 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +010081 MAP_DEVICE0,
82 MAP_DEVICE1,
Dan Handley2b6b5742015-03-19 19:17:53 +000083 ARM_MAP_NS_DRAM1,
Roberto Vargasf8fda102017-08-08 11:27:20 +010084#ifdef AARCH64
85 ARM_MAP_DRAM2,
86#endif
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +010087#ifdef SPD_tspd
Dan Handley2b6b5742015-03-19 19:17:53 +000088 ARM_MAP_TSP_SEC_MEM,
Sandrine Bailleuxb260c3a2017-08-30 10:59:22 +010089#endif
Sandrine Bailleuxd9160a52017-05-26 15:48:10 +010090#if TRUSTED_BOARD_BOOT
91 /* To access the Root of Trust Public Key registers. */
92 MAP_DEVICE2,
Antonio Nino Diaz05f49572018-09-25 11:37:23 +010093#if !BL2_AT_EL3
John Tsichritzisc34341a2018-07-30 13:41:52 +010094 ARM_MAP_BL1_RW,
Antonio Nino Diaz05f49572018-09-25 11:37:23 +010095#endif
John Tsichritzisc34341a2018-07-30 13:41:52 +010096#endif /* TRUSTED_BOARD_BOOT */
Antonio Nino Diazcbccdbf2019-01-21 11:53:29 +000097#if ENABLE_SPM && SPM_MM
Antonio Nino Diaz7289f922017-11-09 11:34:09 +000098 ARM_SP_IMAGE_MMAP,
99#endif
Antonio Nino Diazcbccdbf2019-01-21 11:53:29 +0000100#if ENABLE_SPM && !SPM_MM
Antonio Nino Diaz840627f2018-11-27 08:36:02 +0000101 PLAT_MAP_SP_PACKAGE_MEM_RW,
102#endif
David Wang0ba499f2016-03-07 11:02:57 +0800103#if ARM_BL31_IN_DRAM
104 ARM_MAP_BL31_SEC_DRAM,
105#endif
Jens Wiklander0814c6a2017-08-25 10:07:20 +0200106#ifdef SPD_opteed
Soby Mathew874fc9e2017-09-01 13:43:50 +0100107 ARM_MAP_OPTEE_CORE_MEM,
Jens Wiklander0814c6a2017-08-25 10:07:20 +0200108 ARM_OPTEE_PAGEABLE_LOAD_MEM,
109#endif
Soby Mathewb08bc042014-09-03 17:48:44 +0100110 {0}
111};
112#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900113#ifdef IMAGE_BL2U
Yatharth Kochar3a11eda2015-10-14 15:28:11 +0100114const mmap_region_t plat_arm_mmap[] = {
115 MAP_DEVICE0,
116 V2M_MAP_IOFPGA,
117 {0}
118};
119#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900120#ifdef IMAGE_BL31
Dan Handley2b6b5742015-03-19 19:17:53 +0000121const mmap_region_t plat_arm_mmap[] = {
122 ARM_MAP_SHARED_RAM,
Soby Mathew9ca28062017-10-11 16:08:58 +0100123 ARM_MAP_EL3_TZC_DRAM,
Dan Handley2b6b5742015-03-19 19:17:53 +0000124 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +0100125 MAP_DEVICE0,
126 MAP_DEVICE1,
Roberto Vargasa1c16b62017-08-03 09:16:43 +0100127 ARM_V2M_MAP_MEM_PROTECT,
Antonio Nino Diazcbccdbf2019-01-21 11:53:29 +0000128#if ENABLE_SPM && SPM_MM
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000129 ARM_SPM_BUF_EL3_MMAP,
130#endif
Antonio Nino Diazcbccdbf2019-01-21 11:53:29 +0000131#if ENABLE_SPM && !SPM_MM
Antonio Nino Diaz840627f2018-11-27 08:36:02 +0000132 PLAT_MAP_SP_PACKAGE_MEM_RO,
133#endif
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000134 {0}
135};
136
Antonio Nino Diazcbccdbf2019-01-21 11:53:29 +0000137#if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000138const mmap_region_t plat_arm_secure_partition_mmap[] = {
139 V2M_MAP_IOFPGA_EL0, /* for the UART */
Sandrine Bailleux4808f8b2018-01-12 15:50:12 +0100140 MAP_REGION_FLAT(DEVICE0_BASE, \
141 DEVICE0_SIZE, \
142 MT_DEVICE | MT_RO | MT_SECURE | MT_USER),
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000143 ARM_SP_IMAGE_MMAP,
144 ARM_SP_IMAGE_NS_BUF_MMAP,
145 ARM_SP_IMAGE_RW_MMAP,
146 ARM_SPM_BUF_EL0_MMAP,
Soby Mathewb08bc042014-09-03 17:48:44 +0100147 {0}
148};
149#endif
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000150#endif
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900151#ifdef IMAGE_BL32
Dan Handley2b6b5742015-03-19 19:17:53 +0000152const mmap_region_t plat_arm_mmap[] = {
Soby Mathew0d268dc2016-07-11 14:13:56 +0100153#ifdef AARCH32
154 ARM_MAP_SHARED_RAM,
Joel Hutton10503cc2018-03-15 11:33:44 +0000155 ARM_V2M_MAP_MEM_PROTECT,
Soby Mathew0d268dc2016-07-11 14:13:56 +0100156#endif
Dan Handley2b6b5742015-03-19 19:17:53 +0000157 V2M_MAP_IOFPGA,
Soby Mathewb08bc042014-09-03 17:48:44 +0100158 MAP_DEVICE0,
159 MAP_DEVICE1,
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000160 {0}
161};
Soby Mathewb08bc042014-09-03 17:48:44 +0100162#endif
Jon Medhurstb1eb0932014-02-26 16:27:53 +0000163
Dan Handley2b6b5742015-03-19 19:17:53 +0000164ARM_CASSERT_MMAP
Soby Mathew13ee9682015-01-22 11:22:22 +0000165
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100166#if FVP_INTERCONNECT_DRIVER != FVP_CCN
167static const int fvp_cci400_map[] = {
168 PLAT_FVP_CCI400_CLUS0_SL_PORT,
169 PLAT_FVP_CCI400_CLUS1_SL_PORT,
170};
171
172static const int fvp_cci5xx_map[] = {
173 PLAT_FVP_CCI5XX_CLUS0_SL_PORT,
174 PLAT_FVP_CCI5XX_CLUS1_SL_PORT,
175};
176
177static unsigned int get_interconnect_master(void)
178{
179 unsigned int master;
180 u_register_t mpidr;
181
182 mpidr = read_mpidr_el1();
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000183 master = ((arm_config.flags & ARM_CONFIG_FVP_SHIFTED_AFF) != 0U) ?
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100184 MPIDR_AFFLVL2_VAL(mpidr) : MPIDR_AFFLVL1_VAL(mpidr);
185
186 assert(master < FVP_CLUSTER_COUNT);
187 return master;
188}
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000189#endif
190
Antonio Nino Diazcbccdbf2019-01-21 11:53:29 +0000191#if ENABLE_SPM && defined(IMAGE_BL31) && SPM_MM
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000192/*
193 * Boot information passed to a secure partition during initialisation. Linear
194 * indices in MP information will be filled at runtime.
195 */
196static secure_partition_mp_info_t sp_mp_info[] = {
197 [0] = {0x80000000, 0},
198 [1] = {0x80000001, 0},
199 [2] = {0x80000002, 0},
200 [3] = {0x80000003, 0},
201 [4] = {0x80000100, 0},
202 [5] = {0x80000101, 0},
203 [6] = {0x80000102, 0},
204 [7] = {0x80000103, 0},
205};
206
207const secure_partition_boot_info_t plat_arm_secure_partition_boot_info = {
208 .h.type = PARAM_SP_IMAGE_BOOT_INFO,
209 .h.version = VERSION_1,
210 .h.size = sizeof(secure_partition_boot_info_t),
211 .h.attr = 0,
212 .sp_mem_base = ARM_SP_IMAGE_BASE,
213 .sp_mem_limit = ARM_SP_IMAGE_LIMIT,
214 .sp_image_base = ARM_SP_IMAGE_BASE,
215 .sp_stack_base = PLAT_SP_IMAGE_STACK_BASE,
216 .sp_heap_base = ARM_SP_IMAGE_HEAP_BASE,
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +0100217 .sp_ns_comm_buf_base = PLAT_SP_IMAGE_NS_BUF_BASE,
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000218 .sp_shared_buf_base = PLAT_SPM_BUF_BASE,
219 .sp_image_size = ARM_SP_IMAGE_SIZE,
220 .sp_pcpu_stack_size = PLAT_SP_IMAGE_STACK_PCPU_SIZE,
221 .sp_heap_size = ARM_SP_IMAGE_HEAP_SIZE,
Ard Biesheuvel8b034fc2018-12-29 19:43:21 +0100222 .sp_ns_comm_buf_size = PLAT_SP_IMAGE_NS_BUF_SIZE,
Antonio Nino Diaz7289f922017-11-09 11:34:09 +0000223 .sp_shared_buf_size = PLAT_SPM_BUF_SIZE,
224 .num_sp_mem_regions = ARM_SP_IMAGE_NUM_MEM_REGIONS,
225 .num_cpus = PLATFORM_CORE_COUNT,
226 .mp_info = &sp_mp_info[0],
227};
228
229const struct mmap_region *plat_get_secure_partition_mmap(void *cookie)
230{
231 return plat_arm_secure_partition_mmap;
232}
233
234const struct secure_partition_boot_info *plat_get_secure_partition_boot_info(
235 void *cookie)
236{
237 return &plat_arm_secure_partition_boot_info;
238}
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100239#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100240
Achin Gupta4f6ad662013-10-25 09:08:21 +0100241/*******************************************************************************
242 * A single boot loader stack is expected to work on both the Foundation FVP
243 * models and the two flavours of the Base FVP models (AEMv8 & Cortex). The
244 * SYS_ID register provides a mechanism for detecting the differences between
245 * these platforms. This information is stored in a per-BL array to allow the
246 * code to take the correct path.Per BL platform configuration.
247 ******************************************************************************/
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100248void __init fvp_config_setup(void)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100249{
Soby Mathew8e2f2872014-08-14 12:49:05 +0100250 unsigned int rev, hbi, bld, arch, sys_id;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100251
Dan Handley2b6b5742015-03-19 19:17:53 +0000252 sys_id = mmio_read_32(V2M_SYSREGS_BASE + V2M_SYS_ID);
253 rev = (sys_id >> V2M_SYS_ID_REV_SHIFT) & V2M_SYS_ID_REV_MASK;
254 hbi = (sys_id >> V2M_SYS_ID_HBI_SHIFT) & V2M_SYS_ID_HBI_MASK;
255 bld = (sys_id >> V2M_SYS_ID_BLD_SHIFT) & V2M_SYS_ID_BLD_MASK;
256 arch = (sys_id >> V2M_SYS_ID_ARCH_SHIFT) & V2M_SYS_ID_ARCH_MASK;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100257
Andrew Thoelke960347d2014-06-26 14:27:26 +0100258 if (arch != ARCH_MODEL) {
259 ERROR("This firmware is for FVP models\n");
James Morrissey40a6f642014-02-10 14:24:36 +0000260 panic();
Andrew Thoelke960347d2014-06-26 14:27:26 +0100261 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100262
263 /*
264 * The build field in the SYS_ID tells which variant of the GIC
265 * memory is implemented by the model.
266 */
267 switch (bld) {
268 case BLD_GIC_VE_MMAP:
Soby Mathewcf022c52016-01-13 17:06:00 +0000269 ERROR("Legacy Versatile Express memory map for GIC peripheral"
270 " is not supported\n");
Achin Gupta1fa7eb62015-11-03 14:18:34 +0000271 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100272 break;
273 case BLD_GIC_A53A57_MMAP:
Achin Gupta4f6ad662013-10-25 09:08:21 +0100274 break;
275 default:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100276 ERROR("Unsupported board build %x\n", bld);
277 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100278 }
279
280 /*
281 * The hbi field in the SYS_ID is 0x020 for the Base FVP & 0x010
282 * for the Foundation FVP.
283 */
284 switch (hbi) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000285 case HBI_FOUNDATION_FVP:
Dan Handley2b6b5742015-03-19 19:17:53 +0000286 arm_config.flags = 0;
Andrew Thoelke960347d2014-06-26 14:27:26 +0100287
288 /*
289 * Check for supported revisions of Foundation FVP
290 * Allow future revisions to run but emit warning diagnostic
291 */
292 switch (rev) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000293 case REV_FOUNDATION_FVP_V2_0:
294 case REV_FOUNDATION_FVP_V2_1:
295 case REV_FOUNDATION_FVP_v9_1:
Sandrine Bailleux8b33d702016-09-22 09:46:50 +0100296 case REV_FOUNDATION_FVP_v9_6:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100297 break;
298 default:
299 WARN("Unrecognized Foundation FVP revision %x\n", rev);
300 break;
301 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100302 break;
Dan Handley2b6b5742015-03-19 19:17:53 +0000303 case HBI_BASE_FVP:
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100304 arm_config.flags |= (ARM_CONFIG_BASE_MMAP | ARM_CONFIG_HAS_TZC);
Andrew Thoelke960347d2014-06-26 14:27:26 +0100305
306 /*
307 * Check for supported revisions
308 * Allow future revisions to run but emit warning diagnostic
309 */
310 switch (rev) {
Dan Handley2b6b5742015-03-19 19:17:53 +0000311 case REV_BASE_FVP_V0:
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100312 arm_config.flags |= ARM_CONFIG_FVP_HAS_CCI400;
313 break;
314 case REV_BASE_FVP_REVC:
Isla Mitchellc7860cf2017-08-17 12:25:34 +0100315 arm_config.flags |= (ARM_CONFIG_FVP_HAS_SMMUV3 |
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100316 ARM_CONFIG_FVP_HAS_CCI5XX);
Andrew Thoelke960347d2014-06-26 14:27:26 +0100317 break;
318 default:
319 WARN("Unrecognized Base FVP revision %x\n", rev);
320 break;
321 }
Achin Gupta4f6ad662013-10-25 09:08:21 +0100322 break;
323 default:
Andrew Thoelke960347d2014-06-26 14:27:26 +0100324 ERROR("Unsupported board HBI number 0x%x\n", hbi);
325 panic();
Achin Gupta4f6ad662013-10-25 09:08:21 +0100326 }
Isla Mitchellc7860cf2017-08-17 12:25:34 +0100327
328 /*
329 * We assume that the presence of MT bit, and therefore shifted
330 * affinities, is uniform across the platform: either all CPUs, or no
331 * CPUs implement it.
332 */
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000333 if ((read_mpidr_el1() & MPIDR_MT_MASK) != 0U)
Isla Mitchellc7860cf2017-08-17 12:25:34 +0100334 arm_config.flags |= ARM_CONFIG_FVP_SHIFTED_AFF;
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100335}
Vikram Kanigiri96377452014-04-24 11:02:16 +0100336
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000337
Daniel Boulbyf45a4bb2018-09-18 13:26:03 +0100338void __init fvp_interconnect_init(void)
Vikram Kanigiri96377452014-04-24 11:02:16 +0100339{
Soby Mathew7356b1e2016-03-24 10:12:42 +0000340#if FVP_INTERCONNECT_DRIVER == FVP_CCN
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100341 if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000342 ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100343 panic();
344 }
345
346 plat_arm_interconnect_init();
347#else
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000348 uintptr_t cci_base = 0U;
349 const int *cci_map = NULL;
350 unsigned int map_size = 0U;
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100351
352 /* Initialize the right interconnect */
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000353 if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI5XX) != 0U) {
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100354 cci_base = PLAT_FVP_CCI5XX_BASE;
355 cci_map = fvp_cci5xx_map;
356 map_size = ARRAY_SIZE(fvp_cci5xx_map);
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000357 } else if ((arm_config.flags & ARM_CONFIG_FVP_HAS_CCI400) != 0U) {
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100358 cci_base = PLAT_FVP_CCI400_BASE;
359 cci_map = fvp_cci400_map;
360 map_size = ARRAY_SIZE(fvp_cci400_map);
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000361 } else {
362 return;
Soby Mathew7356b1e2016-03-24 10:12:42 +0000363 }
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100364
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000365 assert(cci_base != 0U);
366 assert(cci_map != NULL);
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100367 cci_init(cci_base, cci_map, map_size);
368#endif
Dan Handleybe234f92014-08-04 16:11:15 +0100369}
370
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000371void fvp_interconnect_enable(void)
Dan Handleybe234f92014-08-04 16:11:15 +0100372{
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100373#if FVP_INTERCONNECT_DRIVER == FVP_CCN
374 plat_arm_interconnect_enter_coherency();
375#else
376 unsigned int master;
377
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000378 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
379 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100380 master = get_interconnect_master();
381 cci_enable_snoop_dvm_reqs(master);
382 }
383#endif
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000384}
385
Vikram Kanigirifbb13012016-02-15 11:54:14 +0000386void fvp_interconnect_disable(void)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +0000387{
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100388#if FVP_INTERCONNECT_DRIVER == FVP_CCN
389 plat_arm_interconnect_exit_coherency();
390#else
391 unsigned int master;
392
Antonio Nino Diaz6971f002018-11-06 13:14:21 +0000393 if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
394 ARM_CONFIG_FVP_HAS_CCI5XX)) != 0U) {
Jeenu Viswambharan9e78b922017-07-18 15:42:50 +0100395 master = get_interconnect_master();
396 cci_disable_snoop_dvm_reqs(master);
397 }
398#endif
Vikram Kanigiri96377452014-04-24 11:02:16 +0100399}
John Tsichritzisc34341a2018-07-30 13:41:52 +0100400
Antonio Nino Diaz05f49572018-09-25 11:37:23 +0100401#if TRUSTED_BOARD_BOOT
John Tsichritzisc34341a2018-07-30 13:41:52 +0100402int plat_get_mbedtls_heap(void **heap_addr, size_t *heap_size)
403{
404 assert(heap_addr != NULL);
405 assert(heap_size != NULL);
406
407 return arm_get_mbedtls_heap(heap_addr, heap_size);
408}
409#endif