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Soby Mathew991d42c2015-06-29 16:30:12 +01001/*
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +01002 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
Soby Mathew991d42c2015-06-29 16:30:12 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soby Mathew991d42c2015-06-29 16:30:12 +01005 */
6
Soby Mathew991d42c2015-06-29 16:30:12 +01007#include <assert.h>
Soby Mathew991d42c2015-06-29 16:30:12 +01008#include <stddef.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <arch.h>
11#include <arch_helpers.h>
12#include <common/bl_common.h>
13#include <common/debug.h>
14#include <lib/el3_runtime/context_mgmt.h>
15#include <lib/el3_runtime/pubsub_events.h>
16#include <plat/common/platform.h>
17
Soby Mathew991d42c2015-06-29 16:30:12 +010018#include "psci_private.h"
19
Antonio Nino Diaz5a42b682018-07-18 11:57:21 +010020/*
21 * Helper functions for the CPU level spinlocks
22 */
23static inline void psci_spin_lock_cpu(int idx)
24{
25 spin_lock(&psci_cpu_pd_nodes[idx].cpu_lock);
26}
27
28static inline void psci_spin_unlock_cpu(int idx)
29{
30 spin_unlock(&psci_cpu_pd_nodes[idx].cpu_lock);
31}
32
Soby Mathew991d42c2015-06-29 16:30:12 +010033/*******************************************************************************
34 * This function checks whether a cpu which has been requested to be turned on
35 * is OFF to begin with.
36 ******************************************************************************/
Soby Mathew85dbf5a2015-04-07 12:16:56 +010037static int cpu_on_validate_state(aff_info_state_t aff_state)
Soby Mathew991d42c2015-06-29 16:30:12 +010038{
Soby Mathew85dbf5a2015-04-07 12:16:56 +010039 if (aff_state == AFF_STATE_ON)
Soby Mathew991d42c2015-06-29 16:30:12 +010040 return PSCI_E_ALREADY_ON;
41
Soby Mathew85dbf5a2015-04-07 12:16:56 +010042 if (aff_state == AFF_STATE_ON_PENDING)
Soby Mathew991d42c2015-06-29 16:30:12 +010043 return PSCI_E_ON_PENDING;
44
Soby Mathew85dbf5a2015-04-07 12:16:56 +010045 assert(aff_state == AFF_STATE_OFF);
Soby Mathew991d42c2015-06-29 16:30:12 +010046 return PSCI_E_SUCCESS;
47}
48
49/*******************************************************************************
Soby Mathew991d42c2015-06-29 16:30:12 +010050 * Generic handler which is called to physically power on a cpu identified by
Soby Mathew6b8b3022015-06-30 11:00:24 +010051 * its mpidr. It performs the generic, architectural, platform setup and state
52 * management to power on the target cpu e.g. it will ensure that
53 * enough information is stashed for it to resume execution in the non-secure
54 * security state.
Soby Mathew991d42c2015-06-29 16:30:12 +010055 *
Soby Mathew3a9e8bf2015-05-05 16:33:16 +010056 * The state of all the relevant power domains are changed after calling the
Soby Mathew6b8b3022015-06-30 11:00:24 +010057 * platform handler as it can return error.
Soby Mathew991d42c2015-06-29 16:30:12 +010058 ******************************************************************************/
Soby Mathew011ca182015-07-29 17:05:03 +010059int psci_cpu_on_start(u_register_t target_cpu,
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +010060 const entry_point_info_t *ep)
Soby Mathew991d42c2015-06-29 16:30:12 +010061{
62 int rc;
Soby Mathewca370502016-01-26 11:47:53 +000063 aff_info_state_t target_aff_state;
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +010064 int target_idx = plat_core_pos_by_mpidr(target_cpu);
Soby Mathew991d42c2015-06-29 16:30:12 +010065
Sandrine Bailleux6181acb2016-04-22 13:00:19 +010066 /* Calling function must supply valid input arguments */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +010067 assert(target_idx >= 0);
Sandrine Bailleux6181acb2016-04-22 13:00:19 +010068 assert(ep != NULL);
69
Soby Mathew991d42c2015-06-29 16:30:12 +010070 /*
71 * This function must only be called on platforms where the
72 * CPU_ON platform hooks have been implemented.
73 */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +010074 assert((psci_plat_pm_ops->pwr_domain_on != NULL) &&
75 (psci_plat_pm_ops->pwr_domain_on_finish != NULL));
Soby Mathew991d42c2015-06-29 16:30:12 +010076
Soby Mathew9d754f62015-04-08 17:42:06 +010077 /* Protect against multiple CPUs trying to turn ON the same target CPU */
78 psci_spin_lock_cpu(target_idx);
Soby Mathew991d42c2015-06-29 16:30:12 +010079
80 /*
Soby Mathew991d42c2015-06-29 16:30:12 +010081 * Generic management: Ensure that the cpu is off to be
82 * turned on.
David Cunado06adba22017-07-19 12:14:07 +010083 * Perform cache maintanence ahead of reading the target CPU state to
84 * ensure that the data is not stale.
85 * There is a theoretical edge case where the cache may contain stale
86 * data for the target CPU data - this can occur under the following
87 * conditions:
88 * - the target CPU is in another cluster from the current
89 * - the target CPU was the last CPU to shutdown on its cluster
90 * - the cluster was removed from coherency as part of the CPU shutdown
91 *
92 * In this case the cache maintenace that was performed as part of the
93 * target CPUs shutdown was not seen by the current CPU's cluster. And
94 * so the cache may contain stale data for the target CPU.
Soby Mathew991d42c2015-06-29 16:30:12 +010095 */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +010096 flush_cpu_data_by_index((unsigned int)target_idx,
97 psci_svc_cpu_data.aff_info_state);
Soby Mathew85dbf5a2015-04-07 12:16:56 +010098 rc = cpu_on_validate_state(psci_get_aff_info_state_by_idx(target_idx));
Soby Mathew991d42c2015-06-29 16:30:12 +010099 if (rc != PSCI_E_SUCCESS)
100 goto exit;
101
102 /*
103 * Call the cpu on handler registered by the Secure Payload Dispatcher
104 * to let it do any bookeeping. If the handler encounters an error, it's
105 * expected to assert within
106 */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100107 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on != NULL))
Soby Mathew991d42c2015-06-29 16:30:12 +0100108 psci_spd_pm->svc_on(target_cpu);
109
110 /*
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100111 * Set the Affinity info state of the target cpu to ON_PENDING.
Soby Mathewca370502016-01-26 11:47:53 +0000112 * Flush aff_info_state as it will be accessed with caches
113 * turned OFF.
Soby Mathew991d42c2015-06-29 16:30:12 +0100114 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100115 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100116 flush_cpu_data_by_index((unsigned int)target_idx,
117 psci_svc_cpu_data.aff_info_state);
Soby Mathewca370502016-01-26 11:47:53 +0000118
119 /*
120 * The cache line invalidation by the target CPU after setting the
121 * state to OFF (see psci_do_cpu_off()), could cause the update to
122 * aff_info_state to be invalidated. Retry the update if the target
123 * CPU aff_info_state is not ON_PENDING.
124 */
125 target_aff_state = psci_get_aff_info_state_by_idx(target_idx);
126 if (target_aff_state != AFF_STATE_ON_PENDING) {
127 assert(target_aff_state == AFF_STATE_OFF);
128 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_ON_PENDING);
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100129 flush_cpu_data_by_index((unsigned int)target_idx,
130 psci_svc_cpu_data.aff_info_state);
Soby Mathewca370502016-01-26 11:47:53 +0000131
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100132 assert(psci_get_aff_info_state_by_idx(target_idx) ==
133 AFF_STATE_ON_PENDING);
Soby Mathewca370502016-01-26 11:47:53 +0000134 }
Soby Mathew6b8b3022015-06-30 11:00:24 +0100135
136 /*
137 * Perform generic, architecture and platform specific handling.
138 */
Soby Mathew6b8b3022015-06-30 11:00:24 +0100139 /*
140 * Plat. management: Give the platform the current state
141 * of the target cpu to allow it to perform the necessary
142 * steps to power on.
143 */
Soby Mathew011ca182015-07-29 17:05:03 +0100144 rc = psci_plat_pm_ops->pwr_domain_on(target_cpu);
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100145 assert((rc == PSCI_E_SUCCESS) || (rc == PSCI_E_INTERN_FAIL));
Soby Mathew991d42c2015-06-29 16:30:12 +0100146
147 if (rc == PSCI_E_SUCCESS)
148 /* Store the re-entry information for the non-secure world. */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100149 cm_init_context_by_index((unsigned int)target_idx, ep);
Soby Mathewca370502016-01-26 11:47:53 +0000150 else {
Soby Mathew991d42c2015-06-29 16:30:12 +0100151 /* Restore the state on error. */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100152 psci_set_aff_info_state_by_idx(target_idx, AFF_STATE_OFF);
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100153 flush_cpu_data_by_index((unsigned int)target_idx,
154 psci_svc_cpu_data.aff_info_state);
Soby Mathewca370502016-01-26 11:47:53 +0000155 }
Soby Mathewb0082d22015-04-09 13:40:55 +0100156
Soby Mathew991d42c2015-06-29 16:30:12 +0100157exit:
Soby Mathew9d754f62015-04-08 17:42:06 +0100158 psci_spin_unlock_cpu(target_idx);
Soby Mathew991d42c2015-06-29 16:30:12 +0100159 return rc;
160}
161
162/*******************************************************************************
Soby Mathew3a9e8bf2015-05-05 16:33:16 +0100163 * The following function finish an earlier power on request. They
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100164 * are called by the common finisher routine in psci_common.c. The `state_info`
165 * is the psci_power_state from which this CPU has woken up from.
Soby Mathew991d42c2015-06-29 16:30:12 +0100166 ******************************************************************************/
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100167void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info)
Soby Mathew991d42c2015-06-29 16:30:12 +0100168{
Soby Mathew991d42c2015-06-29 16:30:12 +0100169 /*
170 * Plat. management: Perform the platform specific actions
171 * for this cpu e.g. enabling the gic or zeroing the mailbox
172 * register. The actual state of this cpu has already been
173 * changed.
174 */
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100175 psci_plat_pm_ops->pwr_domain_on_finish(state_info);
Soby Mathew991d42c2015-06-29 16:30:12 +0100176
Soby Mathew043fe9c2017-04-10 22:35:42 +0100177#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
Soby Mathew991d42c2015-06-29 16:30:12 +0100178 /*
179 * Arch. management: Enable data cache and manage stack memory
180 */
181 psci_do_pwrup_cache_maintenance();
Jeenu Viswambharan346bfd82017-01-05 11:01:02 +0000182#endif
Soby Mathew991d42c2015-06-29 16:30:12 +0100183
184 /*
185 * All the platform specific actions for turning this cpu
186 * on have completed. Perform enough arch.initialization
187 * to run in the non-secure address space.
188 */
Soby Mathewd0194872016-04-29 19:01:30 +0100189 psci_arch_setup();
Soby Mathew991d42c2015-06-29 16:30:12 +0100190
191 /*
Soby Mathew9d754f62015-04-08 17:42:06 +0100192 * Lock the CPU spin lock to make sure that the context initialization
193 * is done. Since the lock is only used in this function to create
194 * a synchronization point with cpu_on_start(), it can be released
195 * immediately.
196 */
197 psci_spin_lock_cpu(cpu_idx);
198 psci_spin_unlock_cpu(cpu_idx);
199
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100200 /* Ensure we have been explicitly woken up by another cpu */
201 assert(psci_get_aff_info_state() == AFF_STATE_ON_PENDING);
202
Soby Mathew9d754f62015-04-08 17:42:06 +0100203 /*
Soby Mathew991d42c2015-06-29 16:30:12 +0100204 * Call the cpu on finish handler registered by the Secure Payload
205 * Dispatcher to let it do any bookeeping. If the handler encounters an
206 * error, it's expected to assert within
207 */
Antonio Nino Diaz56a0e8e2018-07-16 23:19:25 +0100208 if ((psci_spd_pm != NULL) && (psci_spd_pm->svc_on_finish != NULL))
Soby Mathew991d42c2015-06-29 16:30:12 +0100209 psci_spd_pm->svc_on_finish(0);
210
Jeenu Viswambharan55e56a92017-09-22 08:32:10 +0100211 PUBLISH_EVENT(psci_cpu_on_finish);
212
Soby Mathew9d754f62015-04-08 17:42:06 +0100213 /* Populate the mpidr field within the cpu node array */
214 /* This needs to be done only once */
215 psci_cpu_pd_nodes[cpu_idx].mpidr = read_mpidr() & MPIDR_AFFINITY_MASK;
216
Soby Mathew991d42c2015-06-29 16:30:12 +0100217 /*
218 * Generic management: Now we just need to retrieve the
219 * information that we had stashed away during the cpu_on
220 * call to set this cpu on its way.
221 */
222 cm_prepare_el3_exit(NON_SECURE);
Soby Mathew991d42c2015-06-29 16:30:12 +0100223}