Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 2 | * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 8 | #include <asm_macros.S> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <bl1/bl1.h> |
| 10 | #include <common/bl_common.h> |
Yatharth Kochar | a65be2f | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 11 | #include <context.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 12 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 13 | /* ----------------------------------------------------------------------------- |
| 14 | * Very simple stackless exception handlers used by BL1. |
| 15 | * ----------------------------------------------------------------------------- |
| 16 | */ |
Sandrine Bailleux | 4d05275 | 2014-03-24 10:24:08 +0000 | [diff] [blame] | 17 | .globl bl1_exceptions |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 18 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 19 | vector_base bl1_exceptions |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 20 | |
| 21 | /* ----------------------------------------------------- |
Sandrine Bailleux | 046cd3f | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 22 | * Current EL with SP0 : 0x0 - 0x200 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 23 | * ----------------------------------------------------- |
| 24 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 25 | vector_entry SynchronousExceptionSP0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 26 | mov x0, #SYNC_EXCEPTION_SP_EL0 |
| 27 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 28 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 29 | end_vector_entry SynchronousExceptionSP0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 30 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 31 | vector_entry IrqSP0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 32 | mov x0, #IRQ_SP_EL0 |
| 33 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 34 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 35 | end_vector_entry IrqSP0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 36 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 37 | vector_entry FiqSP0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 38 | mov x0, #FIQ_SP_EL0 |
| 39 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 40 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 41 | end_vector_entry FiqSP0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 42 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 43 | vector_entry SErrorSP0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 44 | mov x0, #SERROR_SP_EL0 |
| 45 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 46 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 47 | end_vector_entry SErrorSP0 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 48 | |
| 49 | /* ----------------------------------------------------- |
Sandrine Bailleux | 046cd3f | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 50 | * Current EL with SPx: 0x200 - 0x400 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 51 | * ----------------------------------------------------- |
| 52 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 53 | vector_entry SynchronousExceptionSPx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 54 | mov x0, #SYNC_EXCEPTION_SP_ELX |
| 55 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 56 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 57 | end_vector_entry SynchronousExceptionSPx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 58 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 59 | vector_entry IrqSPx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 60 | mov x0, #IRQ_SP_ELX |
| 61 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 62 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 63 | end_vector_entry IrqSPx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 64 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 65 | vector_entry FiqSPx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 66 | mov x0, #FIQ_SP_ELX |
| 67 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 68 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 69 | end_vector_entry FiqSPx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 70 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 71 | vector_entry SErrorSPx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 72 | mov x0, #SERROR_SP_ELX |
| 73 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 74 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 75 | end_vector_entry SErrorSPx |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 76 | |
| 77 | /* ----------------------------------------------------- |
Sandrine Bailleux | 046cd3f | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 78 | * Lower EL using AArch64 : 0x400 - 0x600 |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 79 | * ----------------------------------------------------- |
| 80 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 81 | vector_entry SynchronousExceptionA64 |
Achin Gupta | ed1744e | 2014-08-04 23:13:10 +0100 | [diff] [blame] | 82 | /* Enable the SError interrupt */ |
| 83 | msr daifclr, #DAIF_ABT_BIT |
| 84 | |
Yatharth Kochar | a65be2f | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 85 | str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR] |
| 86 | |
Sandrine Bailleux | 1626946 | 2015-09-29 13:38:20 +0100 | [diff] [blame] | 87 | /* Expect only SMC exceptions */ |
Yatharth Kochar | a65be2f | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 88 | mrs x30, esr_el3 |
| 89 | ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH |
| 90 | cmp x30, #EC_AARCH64_SMC |
Sandrine Bailleux | 1626946 | 2015-09-29 13:38:20 +0100 | [diff] [blame] | 91 | b.ne unexpected_sync_exception |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 92 | |
Sandrine Bailleux | 1626946 | 2015-09-29 13:38:20 +0100 | [diff] [blame] | 93 | b smc_handler64 |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 94 | end_vector_entry SynchronousExceptionA64 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 95 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 96 | vector_entry IrqA64 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 97 | mov x0, #IRQ_AARCH64 |
| 98 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 99 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 100 | end_vector_entry IrqA64 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 101 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 102 | vector_entry FiqA64 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 103 | mov x0, #FIQ_AARCH64 |
| 104 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 105 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 106 | end_vector_entry FiqA64 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 107 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 108 | vector_entry SErrorA64 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 109 | mov x0, #SERROR_AARCH64 |
| 110 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 111 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 112 | end_vector_entry SErrorA64 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 113 | |
| 114 | /* ----------------------------------------------------- |
Sandrine Bailleux | 046cd3f | 2014-08-06 11:27:23 +0100 | [diff] [blame] | 115 | * Lower EL using AArch32 : 0x600 - 0x800 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 116 | * ----------------------------------------------------- |
| 117 | */ |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 118 | vector_entry SynchronousExceptionA32 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 119 | mov x0, #SYNC_EXCEPTION_AARCH32 |
| 120 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 121 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 122 | end_vector_entry SynchronousExceptionA32 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 123 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 124 | vector_entry IrqA32 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 125 | mov x0, #IRQ_AARCH32 |
| 126 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 127 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 128 | end_vector_entry IrqA32 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 129 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 130 | vector_entry FiqA32 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 131 | mov x0, #FIQ_AARCH32 |
| 132 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 133 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 134 | end_vector_entry FiqA32 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 135 | |
Sandrine Bailleux | 9e6ad6c | 2016-05-24 16:56:03 +0100 | [diff] [blame] | 136 | vector_entry SErrorA32 |
Jeenu Viswambharan | 65f0730 | 2014-02-07 15:50:57 +0000 | [diff] [blame] | 137 | mov x0, #SERROR_AARCH32 |
| 138 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 139 | no_ret plat_panic_handler |
Roberto Vargas | 95f30ab | 2018-04-17 11:31:43 +0100 | [diff] [blame] | 140 | end_vector_entry SErrorA32 |
Sandrine Bailleux | 1626946 | 2015-09-29 13:38:20 +0100 | [diff] [blame] | 141 | |
| 142 | |
| 143 | func smc_handler64 |
Yatharth Kochar | 71c9a5e | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 144 | |
Yatharth Kochar | a65be2f | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 145 | /* ---------------------------------------------- |
Yatharth Kochar | 71c9a5e | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 146 | * Detect if this is a RUN_IMAGE or other SMC. |
Yatharth Kochar | a65be2f | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 147 | * ---------------------------------------------- |
| 148 | */ |
Yatharth Kochar | 71c9a5e | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 149 | mov x30, #BL1_SMC_RUN_IMAGE |
| 150 | cmp x30, x0 |
| 151 | b.ne smc_handler |
| 152 | |
| 153 | /* ------------------------------------------------ |
| 154 | * Make sure only Secure world reaches here. |
| 155 | * ------------------------------------------------ |
| 156 | */ |
| 157 | mrs x30, scr_el3 |
| 158 | tst x30, #SCR_NS_BIT |
| 159 | b.ne unexpected_sync_exception |
| 160 | |
| 161 | /* ---------------------------------------------- |
| 162 | * Handling RUN_IMAGE SMC. First switch back to |
| 163 | * SP_EL0 for the C runtime stack. |
| 164 | * ---------------------------------------------- |
| 165 | */ |
Yatharth Kochar | a65be2f | 2015-10-09 18:06:13 +0100 | [diff] [blame] | 166 | ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 167 | msr spsel, #0 |
| 168 | mov sp, x30 |
| 169 | |
Sandrine Bailleux | 1626946 | 2015-09-29 13:38:20 +0100 | [diff] [blame] | 170 | /* --------------------------------------------------------------------- |
Yatharth Kochar | 5d36121 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 171 | * Pass EL3 control to next BL image. |
Yatharth Kochar | 71c9a5e | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 172 | * Here it expects X1 with the address of a entry_point_info_t |
Yatharth Kochar | 5d36121 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 173 | * structure describing the next BL image entrypoint. |
Sandrine Bailleux | 1626946 | 2015-09-29 13:38:20 +0100 | [diff] [blame] | 174 | * --------------------------------------------------------------------- |
| 175 | */ |
Sandrine Bailleux | 1626946 | 2015-09-29 13:38:20 +0100 | [diff] [blame] | 176 | mov x20, x1 |
| 177 | |
Sandrine Bailleux | 1626946 | 2015-09-29 13:38:20 +0100 | [diff] [blame] | 178 | mov x0, x20 |
Yatharth Kochar | 5d36121 | 2016-06-28 17:07:09 +0100 | [diff] [blame] | 179 | bl bl1_print_next_bl_ep_info |
Sandrine Bailleux | 1626946 | 2015-09-29 13:38:20 +0100 | [diff] [blame] | 180 | |
| 181 | ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET] |
| 182 | msr elr_el3, x0 |
| 183 | msr spsr_el3, x1 |
| 184 | ubfx x0, x1, #MODE_EL_SHIFT, #2 |
| 185 | cmp x0, #MODE_EL3 |
| 186 | b.ne unexpected_sync_exception |
| 187 | |
| 188 | bl disable_mmu_icache_el3 |
| 189 | tlbi alle3 |
Antonio Nino Diaz | eb24dff | 2018-02-19 13:53:48 +0000 | [diff] [blame] | 190 | dsb ish /* ERET implies ISB, so it is not needed here */ |
Sandrine Bailleux | 1626946 | 2015-09-29 13:38:20 +0100 | [diff] [blame] | 191 | |
Sandrine Bailleux | b7e97c4 | 2015-11-10 10:01:19 +0000 | [diff] [blame] | 192 | #if SPIN_ON_BL1_EXIT |
| 193 | bl print_debug_loop_message |
| 194 | debug_loop: |
| 195 | b debug_loop |
| 196 | #endif |
| 197 | |
Sandrine Bailleux | 87322b3 | 2015-11-10 15:01:57 +0000 | [diff] [blame] | 198 | mov x0, x20 |
Juan Castillo | d1413b2 | 2015-10-05 16:59:38 +0100 | [diff] [blame] | 199 | bl bl1_plat_prepare_exit |
| 200 | |
Sandrine Bailleux | 1626946 | 2015-09-29 13:38:20 +0100 | [diff] [blame] | 201 | ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)] |
| 202 | ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)] |
| 203 | ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)] |
| 204 | ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)] |
| 205 | eret |
| 206 | endfunc smc_handler64 |
| 207 | |
| 208 | unexpected_sync_exception: |
| 209 | mov x0, #SYNC_EXCEPTION_AARCH64 |
| 210 | bl plat_report_exception |
Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 211 | no_ret plat_panic_handler |
Yatharth Kochar | 71c9a5e | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 212 | |
| 213 | /* ----------------------------------------------------- |
| 214 | * Save Secure/Normal world context and jump to |
| 215 | * BL1 SMC handler. |
| 216 | * ----------------------------------------------------- |
| 217 | */ |
| 218 | smc_handler: |
| 219 | /* ----------------------------------------------------- |
| 220 | * Save the GP registers x0-x29. |
Antonio Nino Diaz | 3c817f4 | 2018-03-21 10:49:27 +0000 | [diff] [blame] | 221 | * TODO: Revisit to store only SMCCC specified registers. |
Yatharth Kochar | 71c9a5e | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 222 | * ----------------------------------------------------- |
| 223 | */ |
| 224 | bl save_gp_registers |
| 225 | |
| 226 | /* ----------------------------------------------------- |
Alexei Fedorov | 503bbf3 | 2019-08-13 15:17:53 +0100 | [diff] [blame] | 227 | * If Secure Cycle Counter is not disabled in MDCR_EL3 |
| 228 | * when ARMv8.5-PMU is implemented, save PMCR_EL0 and |
| 229 | * disable all event counters and cycle counter. |
| 230 | * ----------------------------------------------------- |
| 231 | */ |
| 232 | bl save_pmcr_disable_pmu |
| 233 | |
| 234 | /* ----------------------------------------------------- |
Yatharth Kochar | 71c9a5e | 2015-10-10 19:06:53 +0100 | [diff] [blame] | 235 | * Populate the parameters for the SMC handler. We |
| 236 | * already have x0-x4 in place. x5 will point to a |
| 237 | * cookie (not used now). x6 will point to the context |
| 238 | * structure (SP_EL3) and x7 will contain flags we need |
| 239 | * to pass to the handler. |
| 240 | * ----------------------------------------------------- |
| 241 | */ |
| 242 | mov x5, xzr |
| 243 | mov x6, sp |
| 244 | |
| 245 | /* ----------------------------------------------------- |
| 246 | * Restore the saved C runtime stack value which will |
| 247 | * become the new SP_EL0 i.e. EL3 runtime stack. It was |
| 248 | * saved in the 'cpu_context' structure prior to the last |
| 249 | * ERET from EL3. |
| 250 | * ----------------------------------------------------- |
| 251 | */ |
| 252 | ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP] |
| 253 | |
| 254 | /* --------------------------------------------- |
| 255 | * Switch back to SP_EL0 for the C runtime stack. |
| 256 | * --------------------------------------------- |
| 257 | */ |
| 258 | msr spsel, #0 |
| 259 | mov sp, x12 |
| 260 | |
| 261 | /* ----------------------------------------------------- |
| 262 | * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there |
| 263 | * is a world switch during SMC handling. |
| 264 | * ----------------------------------------------------- |
| 265 | */ |
| 266 | mrs x16, spsr_el3 |
| 267 | mrs x17, elr_el3 |
| 268 | mrs x18, scr_el3 |
| 269 | stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3] |
| 270 | str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3] |
| 271 | |
| 272 | /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */ |
| 273 | bfi x7, x18, #0, #1 |
| 274 | |
| 275 | /* ----------------------------------------------------- |
| 276 | * Go to BL1 SMC handler. |
| 277 | * ----------------------------------------------------- |
| 278 | */ |
| 279 | bl bl1_smc_handler |
| 280 | |
| 281 | /* ----------------------------------------------------- |
| 282 | * Do the transition to next BL image. |
| 283 | * ----------------------------------------------------- |
| 284 | */ |
| 285 | b el3_exit |