commit eb24dffcda632333820c982d93d8290d0f28072c
author Antonio Nino Diaz <antonio.ninodiaz@arm.com> Mon Feb 19 13:53:48 2018 +0000
committer Antonio Nino Diaz <antonio.ninodiaz@arm.com> Wed Feb 21 13:54:55 2018 +0000
tree 25ea1d115147da95470962d9098063ed770a750d
parent 2d855cd0deef674f9d199b4c8bff296d1f7ef403

Ensure the correct execution of TLBI instructions

After executing a TLBI a DSB is needed to ensure completion of the
TLBI.

rk3328: The MMU is allowed to load TLB entries for as long as it is
enabled. Because of this, the correct place to execute a TLBI is right
after disabling the MMU.

Change-Id: I8280f248d10b49a8c354a4ccbdc8f8345ac4c170
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>

bl1/aarch64/bl1_exceptions.S

diff --git a/bl1/aarch64/bl1_exceptions.S b/bl1/aarch64/bl1_exceptions.S
index eb98ffa..92313fa 100644
--- a/bl1/aarch64/bl1_exceptions.S
+++ b/bl1/aarch64/bl1_exceptions.S
@@ -187,6 +187,7 @@
 
 	bl	disable_mmu_icache_el3
 	tlbi	alle3
+	dsb	ish /* ERET implies ISB, so it is not needed here */
 
 #if SPIN_ON_BL1_EXIT
 	bl	print_debug_loop_message