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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Alexei Fedorov503bbf32019-08-13 15:17:53 +01002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
7#include <arch.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +01008#include <asm_macros.S>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009#include <bl1/bl1.h>
10#include <common/bl_common.h>
Yatharth Kochara65be2f2015-10-09 18:06:13 +010011#include <context.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010012
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010013/* -----------------------------------------------------------------------------
14 * Very simple stackless exception handlers used by BL1.
15 * -----------------------------------------------------------------------------
16 */
Sandrine Bailleux4d052752014-03-24 10:24:08 +000017 .globl bl1_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010018
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010019vector_base bl1_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010020
21 /* -----------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +010022 * Current EL with SP0 : 0x0 - 0x200
Achin Gupta4f6ad662013-10-25 09:08:21 +010023 * -----------------------------------------------------
24 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010025vector_entry SynchronousExceptionSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010026 mov x0, #SYNC_EXCEPTION_SP_EL0
27 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000028 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +010029end_vector_entry SynchronousExceptionSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010030
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010031vector_entry IrqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010032 mov x0, #IRQ_SP_EL0
33 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000034 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +010035end_vector_entry IrqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010037vector_entry FiqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010038 mov x0, #FIQ_SP_EL0
39 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000040 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +010041end_vector_entry FiqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010042
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010043vector_entry SErrorSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010044 mov x0, #SERROR_SP_EL0
45 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000046 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +010047end_vector_entry SErrorSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010048
49 /* -----------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +010050 * Current EL with SPx: 0x200 - 0x400
Achin Gupta4f6ad662013-10-25 09:08:21 +010051 * -----------------------------------------------------
52 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010053vector_entry SynchronousExceptionSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010054 mov x0, #SYNC_EXCEPTION_SP_ELX
55 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000056 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +010057end_vector_entry SynchronousExceptionSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010058
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010059vector_entry IrqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010060 mov x0, #IRQ_SP_ELX
61 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000062 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +010063end_vector_entry IrqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010064
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010065vector_entry FiqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010066 mov x0, #FIQ_SP_ELX
67 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000068 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +010069end_vector_entry FiqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010070
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010071vector_entry SErrorSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010072 mov x0, #SERROR_SP_ELX
73 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000074 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +010075end_vector_entry SErrorSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010076
77 /* -----------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +010078 * Lower EL using AArch64 : 0x400 - 0x600
Achin Gupta4f6ad662013-10-25 09:08:21 +010079 * -----------------------------------------------------
80 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010081vector_entry SynchronousExceptionA64
Achin Guptaed1744e2014-08-04 23:13:10 +010082 /* Enable the SError interrupt */
83 msr daifclr, #DAIF_ABT_BIT
84
Yatharth Kochara65be2f2015-10-09 18:06:13 +010085 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
86
Sandrine Bailleux16269462015-09-29 13:38:20 +010087 /* Expect only SMC exceptions */
Yatharth Kochara65be2f2015-10-09 18:06:13 +010088 mrs x30, esr_el3
89 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
90 cmp x30, #EC_AARCH64_SMC
Sandrine Bailleux16269462015-09-29 13:38:20 +010091 b.ne unexpected_sync_exception
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +010092
Sandrine Bailleux16269462015-09-29 13:38:20 +010093 b smc_handler64
Roberto Vargas95f30ab2018-04-17 11:31:43 +010094end_vector_entry SynchronousExceptionA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +000095
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010096vector_entry IrqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +000097 mov x0, #IRQ_AARCH64
98 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000099 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100100end_vector_entry IrqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000101
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100102vector_entry FiqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000103 mov x0, #FIQ_AARCH64
104 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000105 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100106end_vector_entry FiqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000107
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100108vector_entry SErrorA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000109 mov x0, #SERROR_AARCH64
110 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000111 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100112end_vector_entry SErrorA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000113
114 /* -----------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100115 * Lower EL using AArch32 : 0x600 - 0x800
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000116 * -----------------------------------------------------
117 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100118vector_entry SynchronousExceptionA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000119 mov x0, #SYNC_EXCEPTION_AARCH32
120 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000121 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100122end_vector_entry SynchronousExceptionA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000123
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100124vector_entry IrqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000125 mov x0, #IRQ_AARCH32
126 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000127 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100128end_vector_entry IrqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000129
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100130vector_entry FiqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000131 mov x0, #FIQ_AARCH32
132 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000133 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100134end_vector_entry FiqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000135
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100136vector_entry SErrorA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000137 mov x0, #SERROR_AARCH32
138 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000139 no_ret plat_panic_handler
Roberto Vargas95f30ab2018-04-17 11:31:43 +0100140end_vector_entry SErrorA32
Sandrine Bailleux16269462015-09-29 13:38:20 +0100141
142
143func smc_handler64
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100144
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100145 /* ----------------------------------------------
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100146 * Detect if this is a RUN_IMAGE or other SMC.
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100147 * ----------------------------------------------
148 */
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100149 mov x30, #BL1_SMC_RUN_IMAGE
150 cmp x30, x0
151 b.ne smc_handler
152
153 /* ------------------------------------------------
154 * Make sure only Secure world reaches here.
155 * ------------------------------------------------
156 */
157 mrs x30, scr_el3
158 tst x30, #SCR_NS_BIT
159 b.ne unexpected_sync_exception
160
161 /* ----------------------------------------------
162 * Handling RUN_IMAGE SMC. First switch back to
163 * SP_EL0 for the C runtime stack.
164 * ----------------------------------------------
165 */
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100166 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
167 msr spsel, #0
168 mov sp, x30
169
Sandrine Bailleux16269462015-09-29 13:38:20 +0100170 /* ---------------------------------------------------------------------
Yatharth Kochar5d361212016-06-28 17:07:09 +0100171 * Pass EL3 control to next BL image.
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100172 * Here it expects X1 with the address of a entry_point_info_t
Yatharth Kochar5d361212016-06-28 17:07:09 +0100173 * structure describing the next BL image entrypoint.
Sandrine Bailleux16269462015-09-29 13:38:20 +0100174 * ---------------------------------------------------------------------
175 */
Sandrine Bailleux16269462015-09-29 13:38:20 +0100176 mov x20, x1
177
Sandrine Bailleux16269462015-09-29 13:38:20 +0100178 mov x0, x20
Yatharth Kochar5d361212016-06-28 17:07:09 +0100179 bl bl1_print_next_bl_ep_info
Sandrine Bailleux16269462015-09-29 13:38:20 +0100180
181 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
182 msr elr_el3, x0
183 msr spsr_el3, x1
184 ubfx x0, x1, #MODE_EL_SHIFT, #2
185 cmp x0, #MODE_EL3
186 b.ne unexpected_sync_exception
187
188 bl disable_mmu_icache_el3
189 tlbi alle3
Antonio Nino Diazeb24dff2018-02-19 13:53:48 +0000190 dsb ish /* ERET implies ISB, so it is not needed here */
Sandrine Bailleux16269462015-09-29 13:38:20 +0100191
Sandrine Bailleuxb7e97c42015-11-10 10:01:19 +0000192#if SPIN_ON_BL1_EXIT
193 bl print_debug_loop_message
194debug_loop:
195 b debug_loop
196#endif
197
Sandrine Bailleux87322b32015-11-10 15:01:57 +0000198 mov x0, x20
Juan Castillod1413b22015-10-05 16:59:38 +0100199 bl bl1_plat_prepare_exit
200
Sandrine Bailleux16269462015-09-29 13:38:20 +0100201 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
202 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
203 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
204 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
205 eret
206endfunc smc_handler64
207
208unexpected_sync_exception:
209 mov x0, #SYNC_EXCEPTION_AARCH64
210 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000211 no_ret plat_panic_handler
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100212
213 /* -----------------------------------------------------
214 * Save Secure/Normal world context and jump to
215 * BL1 SMC handler.
216 * -----------------------------------------------------
217 */
218smc_handler:
219 /* -----------------------------------------------------
220 * Save the GP registers x0-x29.
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +0000221 * TODO: Revisit to store only SMCCC specified registers.
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100222 * -----------------------------------------------------
223 */
224 bl save_gp_registers
225
226 /* -----------------------------------------------------
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100227 * If Secure Cycle Counter is not disabled in MDCR_EL3
228 * when ARMv8.5-PMU is implemented, save PMCR_EL0 and
229 * disable all event counters and cycle counter.
230 * -----------------------------------------------------
231 */
232 bl save_pmcr_disable_pmu
233
234 /* -----------------------------------------------------
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100235 * Populate the parameters for the SMC handler. We
236 * already have x0-x4 in place. x5 will point to a
237 * cookie (not used now). x6 will point to the context
238 * structure (SP_EL3) and x7 will contain flags we need
239 * to pass to the handler.
240 * -----------------------------------------------------
241 */
242 mov x5, xzr
243 mov x6, sp
244
245 /* -----------------------------------------------------
246 * Restore the saved C runtime stack value which will
247 * become the new SP_EL0 i.e. EL3 runtime stack. It was
248 * saved in the 'cpu_context' structure prior to the last
249 * ERET from EL3.
250 * -----------------------------------------------------
251 */
252 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
253
254 /* ---------------------------------------------
255 * Switch back to SP_EL0 for the C runtime stack.
256 * ---------------------------------------------
257 */
258 msr spsel, #0
259 mov sp, x12
260
261 /* -----------------------------------------------------
262 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
263 * is a world switch during SMC handling.
264 * -----------------------------------------------------
265 */
266 mrs x16, spsr_el3
267 mrs x17, elr_el3
268 mrs x18, scr_el3
269 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
270 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
271
272 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
273 bfi x7, x18, #0, #1
274
275 /* -----------------------------------------------------
276 * Go to BL1 SMC handler.
277 * -----------------------------------------------------
278 */
279 bl bl1_smc_handler
280
281 /* -----------------------------------------------------
282 * Do the transition to next BL image.
283 * -----------------------------------------------------
284 */
285 b el3_exit