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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +01002 * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010032#include <asm_macros.S>
Achin Gupta4f6ad662013-10-25 09:08:21 +010033#include <bl_common.h>
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +010034#include <bl1.h>
Yatharth Kochara65be2f2015-10-09 18:06:13 +010035#include <context.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010036
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010037/* -----------------------------------------------------------------------------
38 * Very simple stackless exception handlers used by BL1.
39 * -----------------------------------------------------------------------------
40 */
Sandrine Bailleux4d052752014-03-24 10:24:08 +000041 .globl bl1_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010042
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010043vector_base bl1_exceptions
Achin Gupta4f6ad662013-10-25 09:08:21 +010044
45 /* -----------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +010046 * Current EL with SP0 : 0x0 - 0x200
Achin Gupta4f6ad662013-10-25 09:08:21 +010047 * -----------------------------------------------------
48 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010049vector_entry SynchronousExceptionSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010050 mov x0, #SYNC_EXCEPTION_SP_EL0
51 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000052 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000053 check_vector_size SynchronousExceptionSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010054
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010055vector_entry IrqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010056 mov x0, #IRQ_SP_EL0
57 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000058 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000059 check_vector_size IrqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010060
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010061vector_entry FiqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010062 mov x0, #FIQ_SP_EL0
63 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000064 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000065 check_vector_size FiqSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010066
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010067vector_entry SErrorSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010068 mov x0, #SERROR_SP_EL0
69 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000070 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000071 check_vector_size SErrorSP0
Achin Gupta4f6ad662013-10-25 09:08:21 +010072
73 /* -----------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +010074 * Current EL with SPx: 0x200 - 0x400
Achin Gupta4f6ad662013-10-25 09:08:21 +010075 * -----------------------------------------------------
76 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010077vector_entry SynchronousExceptionSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010078 mov x0, #SYNC_EXCEPTION_SP_ELX
79 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000080 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000081 check_vector_size SynchronousExceptionSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010082
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010083vector_entry IrqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010084 mov x0, #IRQ_SP_ELX
85 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000086 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000087 check_vector_size IrqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010088
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010089vector_entry FiqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010090 mov x0, #FIQ_SP_ELX
91 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000092 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000093 check_vector_size FiqSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010094
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +010095vector_entry SErrorSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +010096 mov x0, #SERROR_SP_ELX
97 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +000098 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +000099 check_vector_size SErrorSPx
Achin Gupta4f6ad662013-10-25 09:08:21 +0100100
101 /* -----------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100102 * Lower EL using AArch64 : 0x400 - 0x600
Achin Gupta4f6ad662013-10-25 09:08:21 +0100103 * -----------------------------------------------------
104 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100105vector_entry SynchronousExceptionA64
Achin Guptaed1744e2014-08-04 23:13:10 +0100106 /* Enable the SError interrupt */
107 msr daifclr, #DAIF_ABT_BIT
108
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100109 str x30, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_LR]
110
Sandrine Bailleux16269462015-09-29 13:38:20 +0100111 /* Expect only SMC exceptions */
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100112 mrs x30, esr_el3
113 ubfx x30, x30, #ESR_EC_SHIFT, #ESR_EC_LENGTH
114 cmp x30, #EC_AARCH64_SMC
Sandrine Bailleux16269462015-09-29 13:38:20 +0100115 b.ne unexpected_sync_exception
Vikram Kanigiria3a5e4a2014-05-15 18:27:15 +0100116
Sandrine Bailleux16269462015-09-29 13:38:20 +0100117 b smc_handler64
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000118 check_vector_size SynchronousExceptionA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000119
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100120vector_entry IrqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000121 mov x0, #IRQ_AARCH64
122 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000123 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000124 check_vector_size IrqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000125
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100126vector_entry FiqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000127 mov x0, #FIQ_AARCH64
128 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000129 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000130 check_vector_size FiqA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000131
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100132vector_entry SErrorA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000133 mov x0, #SERROR_AARCH64
134 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000135 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000136 check_vector_size SErrorA64
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000137
138 /* -----------------------------------------------------
Sandrine Bailleux046cd3f2014-08-06 11:27:23 +0100139 * Lower EL using AArch32 : 0x600 - 0x800
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000140 * -----------------------------------------------------
141 */
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100142vector_entry SynchronousExceptionA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000143 mov x0, #SYNC_EXCEPTION_AARCH32
144 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000145 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000146 check_vector_size SynchronousExceptionA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000147
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100148vector_entry IrqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000149 mov x0, #IRQ_AARCH32
150 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000151 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000152 check_vector_size IrqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000153
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100154vector_entry FiqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000155 mov x0, #FIQ_AARCH32
156 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000157 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000158 check_vector_size FiqA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000159
Sandrine Bailleux9e6ad6c2016-05-24 16:56:03 +0100160vector_entry SErrorA32
Jeenu Viswambharan65f07302014-02-07 15:50:57 +0000161 mov x0, #SERROR_AARCH32
162 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000163 no_ret plat_panic_handler
Jeenu Viswambharana7934d62014-02-07 15:53:18 +0000164 check_vector_size SErrorA32
Sandrine Bailleux16269462015-09-29 13:38:20 +0100165
166
167func smc_handler64
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100168
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100169 /* ----------------------------------------------
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100170 * Detect if this is a RUN_IMAGE or other SMC.
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100171 * ----------------------------------------------
172 */
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100173 mov x30, #BL1_SMC_RUN_IMAGE
174 cmp x30, x0
175 b.ne smc_handler
176
177 /* ------------------------------------------------
178 * Make sure only Secure world reaches here.
179 * ------------------------------------------------
180 */
181 mrs x30, scr_el3
182 tst x30, #SCR_NS_BIT
183 b.ne unexpected_sync_exception
184
185 /* ----------------------------------------------
186 * Handling RUN_IMAGE SMC. First switch back to
187 * SP_EL0 for the C runtime stack.
188 * ----------------------------------------------
189 */
Yatharth Kochara65be2f2015-10-09 18:06:13 +0100190 ldr x30, [sp, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
191 msr spsel, #0
192 mov sp, x30
193
Sandrine Bailleux16269462015-09-29 13:38:20 +0100194 /* ---------------------------------------------------------------------
Yatharth Kochar5d361212016-06-28 17:07:09 +0100195 * Pass EL3 control to next BL image.
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100196 * Here it expects X1 with the address of a entry_point_info_t
Yatharth Kochar5d361212016-06-28 17:07:09 +0100197 * structure describing the next BL image entrypoint.
Sandrine Bailleux16269462015-09-29 13:38:20 +0100198 * ---------------------------------------------------------------------
199 */
Sandrine Bailleux16269462015-09-29 13:38:20 +0100200 mov x20, x1
201
Sandrine Bailleux16269462015-09-29 13:38:20 +0100202 mov x0, x20
Yatharth Kochar5d361212016-06-28 17:07:09 +0100203 bl bl1_print_next_bl_ep_info
Sandrine Bailleux16269462015-09-29 13:38:20 +0100204
205 ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
206 msr elr_el3, x0
207 msr spsr_el3, x1
208 ubfx x0, x1, #MODE_EL_SHIFT, #2
209 cmp x0, #MODE_EL3
210 b.ne unexpected_sync_exception
211
212 bl disable_mmu_icache_el3
213 tlbi alle3
214
Sandrine Bailleuxb7e97c42015-11-10 10:01:19 +0000215#if SPIN_ON_BL1_EXIT
216 bl print_debug_loop_message
217debug_loop:
218 b debug_loop
219#endif
220
Sandrine Bailleux87322b32015-11-10 15:01:57 +0000221 mov x0, x20
Juan Castillod1413b22015-10-05 16:59:38 +0100222 bl bl1_plat_prepare_exit
223
Sandrine Bailleux16269462015-09-29 13:38:20 +0100224 ldp x6, x7, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x30)]
225 ldp x4, x5, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x20)]
226 ldp x2, x3, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x10)]
227 ldp x0, x1, [x20, #(ENTRY_POINT_INFO_ARGS_OFFSET + 0x0)]
228 eret
229endfunc smc_handler64
230
231unexpected_sync_exception:
232 mov x0, #SYNC_EXCEPTION_AARCH64
233 bl plat_report_exception
Jeenu Viswambharan68aef102016-11-30 15:21:11 +0000234 no_ret plat_panic_handler
Yatharth Kochar71c9a5e2015-10-10 19:06:53 +0100235
236 /* -----------------------------------------------------
237 * Save Secure/Normal world context and jump to
238 * BL1 SMC handler.
239 * -----------------------------------------------------
240 */
241smc_handler:
242 /* -----------------------------------------------------
243 * Save the GP registers x0-x29.
244 * TODO: Revisit to store only SMCC specified registers.
245 * -----------------------------------------------------
246 */
247 bl save_gp_registers
248
249 /* -----------------------------------------------------
250 * Populate the parameters for the SMC handler. We
251 * already have x0-x4 in place. x5 will point to a
252 * cookie (not used now). x6 will point to the context
253 * structure (SP_EL3) and x7 will contain flags we need
254 * to pass to the handler.
255 * -----------------------------------------------------
256 */
257 mov x5, xzr
258 mov x6, sp
259
260 /* -----------------------------------------------------
261 * Restore the saved C runtime stack value which will
262 * become the new SP_EL0 i.e. EL3 runtime stack. It was
263 * saved in the 'cpu_context' structure prior to the last
264 * ERET from EL3.
265 * -----------------------------------------------------
266 */
267 ldr x12, [x6, #CTX_EL3STATE_OFFSET + CTX_RUNTIME_SP]
268
269 /* ---------------------------------------------
270 * Switch back to SP_EL0 for the C runtime stack.
271 * ---------------------------------------------
272 */
273 msr spsel, #0
274 mov sp, x12
275
276 /* -----------------------------------------------------
277 * Save the SPSR_EL3, ELR_EL3, & SCR_EL3 in case there
278 * is a world switch during SMC handling.
279 * -----------------------------------------------------
280 */
281 mrs x16, spsr_el3
282 mrs x17, elr_el3
283 mrs x18, scr_el3
284 stp x16, x17, [x6, #CTX_EL3STATE_OFFSET + CTX_SPSR_EL3]
285 str x18, [x6, #CTX_EL3STATE_OFFSET + CTX_SCR_EL3]
286
287 /* Copy SCR_EL3.NS bit to the flag to indicate caller's security */
288 bfi x7, x18, #0, #1
289
290 /* -----------------------------------------------------
291 * Go to BL1 SMC handler.
292 * -----------------------------------------------------
293 */
294 bl bl1_smc_handler
295
296 /* -----------------------------------------------------
297 * Do the transition to next BL image.
298 * -----------------------------------------------------
299 */
300 b el3_exit