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Varun Wadekar921b9062015-08-25 17:03:14 +05301/*
Varun Wadekar84a775e2019-01-03 10:12:55 -08002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekar7cf57d72018-05-17 09:36:38 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar921b9062015-08-25 17:03:14 +05306 */
7
Varun Wadekarcad7b082015-12-28 18:12:59 -08008#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <arch_helpers.h>
11#include <bl31/bl31.h>
12#include <bl31/interrupt_mgmt.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
Varun Wadekar0ed62702018-06-20 14:30:59 -070015#include <common/ep_info.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <common/interrupt_props.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080017#include <context.h>
Varun Wadekar4debe052016-05-18 13:39:16 -070018#include <cortex_a57.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080019#include <denver.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <drivers/arm/gic_common.h>
21#include <drivers/arm/gicv2.h>
22#include <drivers/console.h>
23#include <lib/el3_runtime/context_mgmt.h>
Varun Wadekar0ed62702018-06-20 14:30:59 -070024#include <lib/utils.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000025#include <lib/xlat_tables/xlat_tables_v2.h>
26#include <plat/common/platform.h>
27
Varun Wadekar47ddd002016-03-28 16:00:02 -070028#include <mce.h>
Varun Wadekara1251802019-08-22 11:52:36 -070029#include <memctrl.h>
Kalyani Chidambaram Vaidyanathane7558562020-06-15 16:48:53 -070030#include <smmu.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053031#include <tegra_def.h>
Varun Wadekar5887c102016-07-19 11:29:40 -070032#include <tegra_platform.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080033#include <tegra_private.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053034
Varun Wadekar0ed62702018-06-20 14:30:59 -070035extern void memcpy16(void *dest, const void *src, unsigned int length);
36
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080037/*******************************************************************************
Varun Wadekar43dad672017-01-31 14:53:37 -080038 * Tegra186 CPU numbers in cluster #0
39 *******************************************************************************
40 */
Anthony Zhou25d127f2017-03-21 15:58:50 +080041#define TEGRA186_CLUSTER0_CORE2 2U
42#define TEGRA186_CLUSTER0_CORE3 3U
Varun Wadekar43dad672017-01-31 14:53:37 -080043
44/*******************************************************************************
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080045 * The Tegra power domain tree has a single system level power domain i.e. a
46 * single root node. The first entry in the power domain descriptor specifies
47 * the number of power domains at the highest power level.
48 *******************************************************************************
49 */
Anthony Zhou0895a8f2017-09-22 16:52:02 +080050static const uint8_t tegra_power_domain_tree_desc[] = {
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080051 /* No of root nodes */
52 1,
53 /* No of clusters */
54 PLATFORM_CLUSTER_COUNT,
55 /* No of CPU cores - cluster0 */
56 PLATFORM_MAX_CPUS_PER_CLUSTER,
57 /* No of CPU cores - cluster1 */
58 PLATFORM_MAX_CPUS_PER_CLUSTER
59};
60
Varun Wadekare34bc3d2017-04-28 08:43:33 -070061/*******************************************************************************
62 * This function returns the Tegra default topology tree information.
63 ******************************************************************************/
Anthony Zhou25d127f2017-03-21 15:58:50 +080064const uint8_t *plat_get_power_domain_tree_desc(void)
Varun Wadekare34bc3d2017-04-28 08:43:33 -070065{
66 return tegra_power_domain_tree_desc;
67}
68
Varun Wadekar921b9062015-08-25 17:03:14 +053069/*
70 * Table of regions to map using the MMU.
71 */
72static const mmap_region_t tegra_mmap[] = {
Anthony Zhou25d127f2017-03-21 15:58:50 +080073 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053074 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080075 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
Varun Wadekara0f26972016-03-11 17:18:51 -080076 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080077 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053078 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080079 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053080 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080081 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
Varun Wadekar9db0ad12016-07-12 10:04:28 -070082 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080083 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
Varun Wadekar9db0ad12016-07-12 10:04:28 -070084 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080085 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
Varun Wadekar921b9062015-08-25 17:03:14 +053086 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080087 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
Varun Wadekar4debe052016-05-18 13:39:16 -070088 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080089 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053090 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080091 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
Varun Wadekarb8776152016-03-03 13:52:52 -080092 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080093 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
Varun Wadekarb8776152016-03-03 13:52:52 -080094 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080095 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
Varun Wadekarb8776152016-03-03 13:52:52 -080096 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080097 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
Varun Wadekare60f1bf2016-02-17 10:10:50 -080098 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080099 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
Varun Wadekar921b9062015-08-25 17:03:14 +0530100 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar922550a2018-01-23 14:38:51 -0800101 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000U, /* 4KB */
102 MT_DEVICE | MT_RO | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +0800103 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
Varun Wadekarb8776152016-03-03 13:52:52 -0800104 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +0800105 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
Varun Wadekar921b9062015-08-25 17:03:14 +0530106 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +0800107 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000U, /* 128KB - ARM/Denver */
Varun Wadekard64db962016-09-23 14:28:16 -0700108 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +0800109 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +0530110 MT_DEVICE | MT_RW | MT_SECURE),
Jeetesh Burman29e03be2018-05-31 14:15:30 +0530111 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x10000U, /* 64KB */
112 MT_DEVICE | MT_RW | MT_SECURE),
113 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, TEGRA_BPMP_IPC_CH_MAP_SIZE, /* 4KB */
114 MT_DEVICE | MT_RW | MT_SECURE),
115 MAP_REGION_FLAT(TEGRA_BPMP_IPC_RX_PHYS_BASE, TEGRA_BPMP_IPC_CH_MAP_SIZE, /* 4KB */
116 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +0530117 {0}
118};
119
120/*******************************************************************************
121 * Set up the pagetables as per the platform memory map & initialize the MMU
122 ******************************************************************************/
123const mmap_region_t *plat_get_mmio_map(void)
124{
125 /* MMIO space */
126 return tegra_mmap;
127}
128
129/*******************************************************************************
130 * Handler to get the System Counter Frequency
131 ******************************************************************************/
Anthony Zhou25d127f2017-03-21 15:58:50 +0800132uint32_t plat_get_syscnt_freq2(void)
Varun Wadekar921b9062015-08-25 17:03:14 +0530133{
Varun Wadekar20c94292016-01-04 10:57:45 -0800134 return 31250000;
Varun Wadekar921b9062015-08-25 17:03:14 +0530135}
136
137/*******************************************************************************
138 * Maximum supported UART controllers
139 ******************************************************************************/
140#define TEGRA186_MAX_UART_PORTS 7
141
142/*******************************************************************************
143 * This variable holds the UART port base addresses
144 ******************************************************************************/
145static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
146 0, /* undefined - treated as an error case */
147 TEGRA_UARTA_BASE,
148 TEGRA_UARTB_BASE,
149 TEGRA_UARTC_BASE,
150 TEGRA_UARTD_BASE,
151 TEGRA_UARTE_BASE,
152 TEGRA_UARTF_BASE,
153 TEGRA_UARTG_BASE,
154};
155
156/*******************************************************************************
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700157 * Enable console corresponding to the console ID
Varun Wadekar921b9062015-08-25 17:03:14 +0530158 ******************************************************************************/
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700159void plat_enable_console(int32_t id)
Varun Wadekar921b9062015-08-25 17:03:14 +0530160{
Andre Przywara98b5a112020-01-25 00:58:35 +0000161 static console_t uart_console;
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700162 uint32_t console_clock;
Varun Wadekar921b9062015-08-25 17:03:14 +0530163
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700164 if ((id > 0) && (id < TEGRA186_MAX_UART_PORTS)) {
165 /*
166 * Reference clock used by the FPGAs is a lot slower.
167 */
168 if (tegra_platform_is_fpga()) {
169 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
170 } else {
171 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
172 }
Anthony Zhou25d127f2017-03-21 15:58:50 +0800173
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700174 (void)console_16550_register(tegra186_uart_addresses[id],
175 console_clock,
176 TEGRA_CONSOLE_BAUDRATE,
177 &uart_console);
Andre Przywara98b5a112020-01-25 00:58:35 +0000178 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700179 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
180 }
Varun Wadekar921b9062015-08-25 17:03:14 +0530181}
Varun Wadekarcad7b082015-12-28 18:12:59 -0800182
Varun Wadekar4debe052016-05-18 13:39:16 -0700183/*******************************************************************************
184 * Handler for early platform setup
185 ******************************************************************************/
186void plat_early_platform_setup(void)
187{
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800188 uint64_t impl, val;
189 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
Varun Wadekara1251802019-08-22 11:52:36 -0700190 const struct tegra_bl31_params *arg_from_bl2 = plat_get_bl31_params();
Varun Wadekar4debe052016-05-18 13:39:16 -0700191
kalyanic0a2cc612019-09-13 14:49:39 -0700192 /* Verify chip id is t186 */
193 assert(tegra_chipid_is_t186());
194
Varun Wadekar4debe052016-05-18 13:39:16 -0700195 /* sanity check MCE firmware compatibility */
196 mce_verify_firmware_version();
197
Varun Wadekara1251802019-08-22 11:52:36 -0700198 /*
199 * Do initial security configuration to allow DRAM/device access.
200 */
201 tegra_memctrl_tzdram_setup(plat_params->tzdram_base,
202 (uint32_t)plat_params->tzdram_size);
203
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800204 impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
205
Varun Wadekar4debe052016-05-18 13:39:16 -0700206 /*
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800207 * Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186
208 * A02p and beyond).
Varun Wadekar4debe052016-05-18 13:39:16 -0700209 */
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800210 if ((plat_params->l2_ecc_parity_prot_dis != 1) &&
211 (impl != (uint64_t)DENVER_IMPL)) {
Varun Wadekar4debe052016-05-18 13:39:16 -0700212
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800213 val = read_l2ctlr_el1();
Anthony Zhou25d127f2017-03-21 15:58:50 +0800214 val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800215 write_l2ctlr_el1(val);
Varun Wadekar4debe052016-05-18 13:39:16 -0700216 }
Varun Wadekara1251802019-08-22 11:52:36 -0700217
218 /*
219 * The previous bootloader might not have placed the BL32 image
220 * inside the TZDRAM. Platform handler to allow relocation of BL32
221 * image to TZDRAM memory. This behavior might change per platform.
222 */
223 plat_relocate_bl32_image(arg_from_bl2->bl32_image_info);
Varun Wadekar4debe052016-05-18 13:39:16 -0700224}
225
Varun Wadekar7cf57d72018-05-17 09:36:38 -0700226/*******************************************************************************
227 * Handler for late platform setup
228 ******************************************************************************/
229void plat_late_platform_setup(void)
230{
231 ; /* do nothing */
232}
233
Varun Wadekarcad7b082015-12-28 18:12:59 -0800234/* Secure IRQs for Tegra186 */
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700235static const interrupt_prop_t tegra186_interrupt_props[] = {
Varun Wadekarbef02f02020-04-17 19:09:21 -0700236 INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
237 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700238 INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700239 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700240 INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700241 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
Varun Wadekarcad7b082015-12-28 18:12:59 -0800242};
243
244/*******************************************************************************
245 * Initialize the GIC and SGIs
246 ******************************************************************************/
247void plat_gic_setup(void)
248{
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700249 tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props));
Varun Wadekar84a775e2019-01-03 10:12:55 -0800250 tegra_gic_init();
Varun Wadekarcad7b082015-12-28 18:12:59 -0800251
252 /*
253 * Initialize the FIQ handler only if the platform supports any
254 * FIQ interrupt sources.
255 */
Varun Wadekar84a775e2019-01-03 10:12:55 -0800256 tegra_fiq_handler_setup();
Varun Wadekarcad7b082015-12-28 18:12:59 -0800257}
Varun Wadekar94701ff2016-05-23 11:47:34 -0700258
259/*******************************************************************************
260 * Return pointer to the BL31 params from previous bootloader
261 ******************************************************************************/
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100262struct tegra_bl31_params *plat_get_bl31_params(void)
Varun Wadekar94701ff2016-05-23 11:47:34 -0700263{
264 uint32_t val;
265
Steven Kao186485e2017-10-23 18:22:09 +0800266 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
Varun Wadekar94701ff2016-05-23 11:47:34 -0700267
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100268 return (struct tegra_bl31_params *)(uintptr_t)val;
Varun Wadekar94701ff2016-05-23 11:47:34 -0700269}
270
271/*******************************************************************************
272 * Return pointer to the BL31 platform params from previous bootloader
273 ******************************************************************************/
274plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
275{
276 uint32_t val;
277
Steven Kao186485e2017-10-23 18:22:09 +0800278 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
Varun Wadekar94701ff2016-05-23 11:47:34 -0700279
280 return (plat_params_from_bl2_t *)(uintptr_t)val;
281}
Varun Wadekar43dad672017-01-31 14:53:37 -0800282
283/*******************************************************************************
284 * This function implements a part of the critical interface between the psci
285 * generic layer and the platform that allows the former to query the platform
286 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
287 * in case the MPIDR is invalid.
288 ******************************************************************************/
Anthony Zhou25d127f2017-03-21 15:58:50 +0800289int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
Varun Wadekar43dad672017-01-31 14:53:37 -0800290{
Anthony Zhou25d127f2017-03-21 15:58:50 +0800291 u_register_t cluster_id, cpu_id, pos;
292 int32_t ret;
Varun Wadekar43dad672017-01-31 14:53:37 -0800293
Anthony Zhou25d127f2017-03-21 15:58:50 +0800294 cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
295 cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
Varun Wadekar43dad672017-01-31 14:53:37 -0800296
297 /*
298 * Validate cluster_id by checking whether it represents
299 * one of the two clusters present on the platform.
Varun Wadekar43dad672017-01-31 14:53:37 -0800300 * Validate cpu_id by checking whether it represents a CPU in
301 * one of the two clusters present on the platform.
302 */
Anthony Zhou25d127f2017-03-21 15:58:50 +0800303 if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) ||
304 (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) {
Manish Pandey21315802023-10-27 16:18:50 +0100305 ret = -1;
Anthony Zhou25d127f2017-03-21 15:58:50 +0800306 } else {
307 /* calculate the core position */
308 pos = cpu_id + (cluster_id << 2U);
Varun Wadekar43dad672017-01-31 14:53:37 -0800309
Anthony Zhou25d127f2017-03-21 15:58:50 +0800310 /* check for non-existent CPUs */
311 if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) {
Manish Pandey21315802023-10-27 16:18:50 +0100312 ret = -1;
Anthony Zhou25d127f2017-03-21 15:58:50 +0800313 } else {
314 ret = (int32_t)pos;
315 }
316 }
Varun Wadekar43dad672017-01-31 14:53:37 -0800317
Anthony Zhou25d127f2017-03-21 15:58:50 +0800318 return ret;
Varun Wadekar43dad672017-01-31 14:53:37 -0800319}
Varun Wadekar0ed62702018-06-20 14:30:59 -0700320
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700321/*******************************************************************************
322 * Handler to relocate BL32 image to TZDRAM
323 ******************************************************************************/
Varun Wadekar0ed62702018-06-20 14:30:59 -0700324void plat_relocate_bl32_image(const image_info_t *bl32_img_info)
325{
326 const plat_params_from_bl2_t *plat_bl31_params = plat_get_bl31_plat_params();
327 const entry_point_info_t *bl32_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
328 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
329
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700330 if ((bl32_img_info != NULL) && (bl32_ep_info != NULL)) {
Varun Wadekar0ed62702018-06-20 14:30:59 -0700331
332 /* Relocate BL32 if it resides outside of the TZDRAM */
333 tzdram_start = plat_bl31_params->tzdram_base;
334 tzdram_end = plat_bl31_params->tzdram_base +
335 plat_bl31_params->tzdram_size;
336 bl32_start = bl32_img_info->image_base;
337 bl32_end = bl32_img_info->image_base + bl32_img_info->image_size;
338
339 assert(tzdram_end > tzdram_start);
340 assert(bl32_end > bl32_start);
341 assert(bl32_ep_info->pc > tzdram_start);
342 assert(bl32_ep_info->pc < tzdram_end);
343
344 /* relocate BL32 */
345 if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
346
347 INFO("Relocate BL32 to TZDRAM\n");
348
349 (void)memcpy16((void *)(uintptr_t)bl32_ep_info->pc,
350 (void *)(uintptr_t)bl32_start,
351 bl32_img_info->image_size);
352
353 /* clean up non-secure intermediate buffer */
354 zeromem((void *)(uintptr_t)bl32_start,
355 bl32_img_info->image_size);
356 }
357 }
358}
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700359
360/*******************************************************************************
361 * Handler to indicate support for System Suspend
362 ******************************************************************************/
363bool plat_supports_system_suspend(void)
364{
365 return true;
366}
Kalyani Chidambaram Vaidyanathane7558562020-06-15 16:48:53 -0700367/*******************************************************************************
368 * Platform specific runtime setup.
369 ******************************************************************************/
370void plat_runtime_setup(void)
371{
372 /*
373 * During cold boot, it is observed that the arbitration
374 * bit is set in the Memory controller leading to false
375 * error interrupts in the non-secure world. To avoid
376 * this, clean the interrupt status register before
377 * booting into the non-secure world
378 */
379 tegra_memctrl_clear_pending_interrupts();
380
381 /*
382 * During boot, USB3 and flash media (SDMMC/SATA) devices need
383 * access to IRAM. Because these clients connect to the MC and
384 * do not have a direct path to the IRAM, the MC implements AHB
385 * redirection during boot to allow path to IRAM. In this mode
386 * accesses to a programmed memory address aperture are directed
387 * to the AHB bus, allowing access to the IRAM. This mode must be
388 * disabled before we jump to the non-secure world.
389 */
390 tegra_memctrl_disable_ahb_redirection();
391
392 /*
393 * Verify the integrity of the previously configured SMMU(s)
394 * settings
395 */
396 tegra_smmu_verify();
397}