blob: 6260351190f88843445e6cc45bb5cab78cb3d79e [file] [log] [blame]
Varun Wadekar921b9062015-08-25 17:03:14 +05301/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <console.h>
32#include <tegra_def.h>
33#include <xlat_tables.h>
34
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080035/*******************************************************************************
36 * The Tegra power domain tree has a single system level power domain i.e. a
37 * single root node. The first entry in the power domain descriptor specifies
38 * the number of power domains at the highest power level.
39 *******************************************************************************
40 */
41const unsigned char tegra_power_domain_tree_desc[] = {
42 /* No of root nodes */
43 1,
44 /* No of clusters */
45 PLATFORM_CLUSTER_COUNT,
46 /* No of CPU cores - cluster0 */
47 PLATFORM_MAX_CPUS_PER_CLUSTER,
48 /* No of CPU cores - cluster1 */
49 PLATFORM_MAX_CPUS_PER_CLUSTER
50};
51
Varun Wadekar921b9062015-08-25 17:03:14 +053052/*
53 * Table of regions to map using the MMU.
54 */
55static const mmap_region_t tegra_mmap[] = {
56 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
57 MT_DEVICE | MT_RW | MT_SECURE),
58 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
59 MT_DEVICE | MT_RW | MT_SECURE),
60 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
61 MT_DEVICE | MT_RW | MT_SECURE),
62 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */
63 MT_DEVICE | MT_RW | MT_SECURE),
64 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
65 MT_DEVICE | MT_RW | MT_SECURE),
66 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
67 MT_DEVICE | MT_RW | MT_SECURE),
68 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
69 MT_DEVICE | MT_RW | MT_SECURE),
70 MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x10000, /* 64KB */
71 MT_DEVICE | MT_RW | MT_SECURE),
72 {0}
73};
74
75/*******************************************************************************
76 * Set up the pagetables as per the platform memory map & initialize the MMU
77 ******************************************************************************/
78const mmap_region_t *plat_get_mmio_map(void)
79{
80 /* MMIO space */
81 return tegra_mmap;
82}
83
84/*******************************************************************************
85 * Handler to get the System Counter Frequency
86 ******************************************************************************/
87unsigned int plat_get_syscnt_freq2(void)
88{
Varun Wadekar20c94292016-01-04 10:57:45 -080089 return 31250000;
Varun Wadekar921b9062015-08-25 17:03:14 +053090}
91
92/*******************************************************************************
93 * Maximum supported UART controllers
94 ******************************************************************************/
95#define TEGRA186_MAX_UART_PORTS 7
96
97/*******************************************************************************
98 * This variable holds the UART port base addresses
99 ******************************************************************************/
100static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
101 0, /* undefined - treated as an error case */
102 TEGRA_UARTA_BASE,
103 TEGRA_UARTB_BASE,
104 TEGRA_UARTC_BASE,
105 TEGRA_UARTD_BASE,
106 TEGRA_UARTE_BASE,
107 TEGRA_UARTF_BASE,
108 TEGRA_UARTG_BASE,
109};
110
111/*******************************************************************************
112 * Retrieve the UART controller base to be used as the console
113 ******************************************************************************/
114uint32_t plat_get_console_from_id(int id)
115{
116 if (id > TEGRA186_MAX_UART_PORTS)
117 return 0;
118
119 return tegra186_uart_addresses[id];
120}