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Varun Wadekar921b9062015-08-25 17:03:14 +05301/*
Varun Wadekar84a775e2019-01-03 10:12:55 -08002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Varun Wadekar7cf57d72018-05-17 09:36:38 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Varun Wadekar921b9062015-08-25 17:03:14 +05304 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar921b9062015-08-25 17:03:14 +05306 */
7
Varun Wadekarcad7b082015-12-28 18:12:59 -08008#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00009
10#include <arch_helpers.h>
11#include <bl31/bl31.h>
12#include <bl31/interrupt_mgmt.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
Varun Wadekar0ed62702018-06-20 14:30:59 -070015#include <common/ep_info.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <common/interrupt_props.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080017#include <context.h>
Varun Wadekar4debe052016-05-18 13:39:16 -070018#include <cortex_a57.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080019#include <denver.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000020#include <drivers/arm/gic_common.h>
21#include <drivers/arm/gicv2.h>
22#include <drivers/console.h>
23#include <lib/el3_runtime/context_mgmt.h>
Varun Wadekar0ed62702018-06-20 14:30:59 -070024#include <lib/utils.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000025#include <lib/xlat_tables/xlat_tables_v2.h>
26#include <plat/common/platform.h>
27
Varun Wadekar47ddd002016-03-28 16:00:02 -070028#include <mce.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053029#include <tegra_def.h>
Varun Wadekar5887c102016-07-19 11:29:40 -070030#include <tegra_platform.h>
Varun Wadekarcad7b082015-12-28 18:12:59 -080031#include <tegra_private.h>
Varun Wadekar921b9062015-08-25 17:03:14 +053032
Varun Wadekar0ed62702018-06-20 14:30:59 -070033extern void memcpy16(void *dest, const void *src, unsigned int length);
34
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080035/*******************************************************************************
Varun Wadekar43dad672017-01-31 14:53:37 -080036 * Tegra186 CPU numbers in cluster #0
37 *******************************************************************************
38 */
Anthony Zhou25d127f2017-03-21 15:58:50 +080039#define TEGRA186_CLUSTER0_CORE2 2U
40#define TEGRA186_CLUSTER0_CORE3 3U
Varun Wadekar43dad672017-01-31 14:53:37 -080041
42/*******************************************************************************
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080043 * The Tegra power domain tree has a single system level power domain i.e. a
44 * single root node. The first entry in the power domain descriptor specifies
45 * the number of power domains at the highest power level.
46 *******************************************************************************
47 */
Anthony Zhou0895a8f2017-09-22 16:52:02 +080048static const uint8_t tegra_power_domain_tree_desc[] = {
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -080049 /* No of root nodes */
50 1,
51 /* No of clusters */
52 PLATFORM_CLUSTER_COUNT,
53 /* No of CPU cores - cluster0 */
54 PLATFORM_MAX_CPUS_PER_CLUSTER,
55 /* No of CPU cores - cluster1 */
56 PLATFORM_MAX_CPUS_PER_CLUSTER
57};
58
Varun Wadekare34bc3d2017-04-28 08:43:33 -070059/*******************************************************************************
60 * This function returns the Tegra default topology tree information.
61 ******************************************************************************/
Anthony Zhou25d127f2017-03-21 15:58:50 +080062const uint8_t *plat_get_power_domain_tree_desc(void)
Varun Wadekare34bc3d2017-04-28 08:43:33 -070063{
64 return tegra_power_domain_tree_desc;
65}
66
Varun Wadekar921b9062015-08-25 17:03:14 +053067/*
68 * Table of regions to map using the MMU.
69 */
70static const mmap_region_t tegra_mmap[] = {
Anthony Zhou25d127f2017-03-21 15:58:50 +080071 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053072 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080073 MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
Varun Wadekara0f26972016-03-11 17:18:51 -080074 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080075 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053076 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080077 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053078 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080079 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
Varun Wadekar9db0ad12016-07-12 10:04:28 -070080 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080081 MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
Varun Wadekar9db0ad12016-07-12 10:04:28 -070082 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080083 MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
Varun Wadekar921b9062015-08-25 17:03:14 +053084 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080085 MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
Varun Wadekar4debe052016-05-18 13:39:16 -070086 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080087 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053088 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080089 MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
Varun Wadekarb8776152016-03-03 13:52:52 -080090 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080091 MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
Varun Wadekarb8776152016-03-03 13:52:52 -080092 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080093 MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
Varun Wadekarb8776152016-03-03 13:52:52 -080094 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080095 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
Varun Wadekare60f1bf2016-02-17 10:10:50 -080096 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +080097 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
Varun Wadekar921b9062015-08-25 17:03:14 +053098 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar922550a2018-01-23 14:38:51 -080099 MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000U, /* 4KB */
100 MT_DEVICE | MT_RO | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +0800101 MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
Varun Wadekarb8776152016-03-03 13:52:52 -0800102 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +0800103 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
Varun Wadekar921b9062015-08-25 17:03:14 +0530104 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +0800105 MAP_REGION_FLAT(TEGRA_ARM_ACTMON_CTR_BASE, 0x20000U, /* 128KB - ARM/Denver */
Varun Wadekard64db962016-09-23 14:28:16 -0700106 MT_DEVICE | MT_RW | MT_SECURE),
Anthony Zhou25d127f2017-03-21 15:58:50 +0800107 MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */
Varun Wadekar921b9062015-08-25 17:03:14 +0530108 MT_DEVICE | MT_RW | MT_SECURE),
Jeetesh Burman29e03be2018-05-31 14:15:30 +0530109 MAP_REGION_FLAT(TEGRA_HSP_DBELL_BASE, 0x10000U, /* 64KB */
110 MT_DEVICE | MT_RW | MT_SECURE),
111 MAP_REGION_FLAT(TEGRA_BPMP_IPC_TX_PHYS_BASE, TEGRA_BPMP_IPC_CH_MAP_SIZE, /* 4KB */
112 MT_DEVICE | MT_RW | MT_SECURE),
113 MAP_REGION_FLAT(TEGRA_BPMP_IPC_RX_PHYS_BASE, TEGRA_BPMP_IPC_CH_MAP_SIZE, /* 4KB */
114 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +0530115 {0}
116};
117
118/*******************************************************************************
119 * Set up the pagetables as per the platform memory map & initialize the MMU
120 ******************************************************************************/
121const mmap_region_t *plat_get_mmio_map(void)
122{
123 /* MMIO space */
124 return tegra_mmap;
125}
126
127/*******************************************************************************
128 * Handler to get the System Counter Frequency
129 ******************************************************************************/
Anthony Zhou25d127f2017-03-21 15:58:50 +0800130uint32_t plat_get_syscnt_freq2(void)
Varun Wadekar921b9062015-08-25 17:03:14 +0530131{
Varun Wadekar20c94292016-01-04 10:57:45 -0800132 return 31250000;
Varun Wadekar921b9062015-08-25 17:03:14 +0530133}
134
135/*******************************************************************************
136 * Maximum supported UART controllers
137 ******************************************************************************/
138#define TEGRA186_MAX_UART_PORTS 7
139
140/*******************************************************************************
141 * This variable holds the UART port base addresses
142 ******************************************************************************/
143static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
144 0, /* undefined - treated as an error case */
145 TEGRA_UARTA_BASE,
146 TEGRA_UARTB_BASE,
147 TEGRA_UARTC_BASE,
148 TEGRA_UARTD_BASE,
149 TEGRA_UARTE_BASE,
150 TEGRA_UARTF_BASE,
151 TEGRA_UARTG_BASE,
152};
153
154/*******************************************************************************
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700155 * Enable console corresponding to the console ID
Varun Wadekar921b9062015-08-25 17:03:14 +0530156 ******************************************************************************/
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700157void plat_enable_console(int32_t id)
Varun Wadekar921b9062015-08-25 17:03:14 +0530158{
Andre Przywara98b5a112020-01-25 00:58:35 +0000159 static console_t uart_console;
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700160 uint32_t console_clock;
Varun Wadekar921b9062015-08-25 17:03:14 +0530161
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700162 if ((id > 0) && (id < TEGRA186_MAX_UART_PORTS)) {
163 /*
164 * Reference clock used by the FPGAs is a lot slower.
165 */
166 if (tegra_platform_is_fpga()) {
167 console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
168 } else {
169 console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
170 }
Anthony Zhou25d127f2017-03-21 15:58:50 +0800171
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700172 (void)console_16550_register(tegra186_uart_addresses[id],
173 console_clock,
174 TEGRA_CONSOLE_BAUDRATE,
175 &uart_console);
Andre Przywara98b5a112020-01-25 00:58:35 +0000176 console_set_scope(&uart_console, CONSOLE_FLAG_BOOT |
Varun Wadekar9d15f7e2019-08-21 14:01:31 -0700177 CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
178 }
Varun Wadekar921b9062015-08-25 17:03:14 +0530179}
Varun Wadekarcad7b082015-12-28 18:12:59 -0800180
Varun Wadekar4debe052016-05-18 13:39:16 -0700181/*******************************************************************************
182 * Handler for early platform setup
183 ******************************************************************************/
184void plat_early_platform_setup(void)
185{
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800186 uint64_t impl, val;
187 const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
Varun Wadekar4debe052016-05-18 13:39:16 -0700188
189 /* sanity check MCE firmware compatibility */
190 mce_verify_firmware_version();
191
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800192 impl = (read_midr() >> MIDR_IMPL_SHIFT) & (uint64_t)MIDR_IMPL_MASK;
193
Varun Wadekar4debe052016-05-18 13:39:16 -0700194 /*
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800195 * Enable ECC and Parity Protection for Cortex-A57 CPUs (Tegra186
196 * A02p and beyond).
Varun Wadekar4debe052016-05-18 13:39:16 -0700197 */
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800198 if ((plat_params->l2_ecc_parity_prot_dis != 1) &&
199 (impl != (uint64_t)DENVER_IMPL)) {
Varun Wadekar4debe052016-05-18 13:39:16 -0700200
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800201 val = read_l2ctlr_el1();
Anthony Zhou25d127f2017-03-21 15:58:50 +0800202 val |= CORTEX_A57_L2_ECC_PARITY_PROTECTION_BIT;
Harvey Hsiehfbdfce12016-11-23 19:13:08 +0800203 write_l2ctlr_el1(val);
Varun Wadekar4debe052016-05-18 13:39:16 -0700204 }
205}
206
Varun Wadekar7cf57d72018-05-17 09:36:38 -0700207/*******************************************************************************
208 * Handler for late platform setup
209 ******************************************************************************/
210void plat_late_platform_setup(void)
211{
212 ; /* do nothing */
213}
214
Varun Wadekarcad7b082015-12-28 18:12:59 -0800215/* Secure IRQs for Tegra186 */
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700216static const interrupt_prop_t tegra186_interrupt_props[] = {
Varun Wadekarbef02f02020-04-17 19:09:21 -0700217 INTR_PROP_DESC(TEGRA_SDEI_SGI_PRIVATE, PLAT_SDEI_CRITICAL_PRI,
218 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700219 INTR_PROP_DESC(TEGRA186_TOP_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700220 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
Varun Wadekar10c32cb2020-03-31 18:42:59 -0700221 INTR_PROP_DESC(TEGRA186_AON_WDT_IRQ, PLAT_TEGRA_WDT_PRIO,
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700222 GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
Varun Wadekarcad7b082015-12-28 18:12:59 -0800223};
224
225/*******************************************************************************
226 * Initialize the GIC and SGIs
227 ******************************************************************************/
228void plat_gic_setup(void)
229{
Varun Wadekar9f4a7d32018-10-19 11:42:28 -0700230 tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props));
Varun Wadekar84a775e2019-01-03 10:12:55 -0800231 tegra_gic_init();
Varun Wadekarcad7b082015-12-28 18:12:59 -0800232
233 /*
234 * Initialize the FIQ handler only if the platform supports any
235 * FIQ interrupt sources.
236 */
Varun Wadekar84a775e2019-01-03 10:12:55 -0800237 tegra_fiq_handler_setup();
Varun Wadekarcad7b082015-12-28 18:12:59 -0800238}
Varun Wadekar94701ff2016-05-23 11:47:34 -0700239
240/*******************************************************************************
241 * Return pointer to the BL31 params from previous bootloader
242 ******************************************************************************/
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100243struct tegra_bl31_params *plat_get_bl31_params(void)
Varun Wadekar94701ff2016-05-23 11:47:34 -0700244{
245 uint32_t val;
246
Steven Kao186485e2017-10-23 18:22:09 +0800247 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
Varun Wadekar94701ff2016-05-23 11:47:34 -0700248
Antonio Nino Diaz6bf7c6b2018-09-24 17:16:05 +0100249 return (struct tegra_bl31_params *)(uintptr_t)val;
Varun Wadekar94701ff2016-05-23 11:47:34 -0700250}
251
252/*******************************************************************************
253 * Return pointer to the BL31 platform params from previous bootloader
254 ******************************************************************************/
255plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
256{
257 uint32_t val;
258
Steven Kao186485e2017-10-23 18:22:09 +0800259 val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
Varun Wadekar94701ff2016-05-23 11:47:34 -0700260
261 return (plat_params_from_bl2_t *)(uintptr_t)val;
262}
Varun Wadekar43dad672017-01-31 14:53:37 -0800263
264/*******************************************************************************
265 * This function implements a part of the critical interface between the psci
266 * generic layer and the platform that allows the former to query the platform
267 * to convert an MPIDR to a unique linear index. An error code (-1) is returned
268 * in case the MPIDR is invalid.
269 ******************************************************************************/
Anthony Zhou25d127f2017-03-21 15:58:50 +0800270int32_t plat_core_pos_by_mpidr(u_register_t mpidr)
Varun Wadekar43dad672017-01-31 14:53:37 -0800271{
Anthony Zhou25d127f2017-03-21 15:58:50 +0800272 u_register_t cluster_id, cpu_id, pos;
273 int32_t ret;
Varun Wadekar43dad672017-01-31 14:53:37 -0800274
Anthony Zhou25d127f2017-03-21 15:58:50 +0800275 cluster_id = (mpidr >> (u_register_t)MPIDR_AFF1_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
276 cpu_id = (mpidr >> (u_register_t)MPIDR_AFF0_SHIFT) & (u_register_t)MPIDR_AFFLVL_MASK;
Varun Wadekar43dad672017-01-31 14:53:37 -0800277
278 /*
279 * Validate cluster_id by checking whether it represents
280 * one of the two clusters present on the platform.
Varun Wadekar43dad672017-01-31 14:53:37 -0800281 * Validate cpu_id by checking whether it represents a CPU in
282 * one of the two clusters present on the platform.
283 */
Anthony Zhou25d127f2017-03-21 15:58:50 +0800284 if ((cluster_id >= (u_register_t)PLATFORM_CLUSTER_COUNT) ||
285 (cpu_id >= (u_register_t)PLATFORM_MAX_CPUS_PER_CLUSTER)) {
286 ret = PSCI_E_NOT_PRESENT;
287 } else {
288 /* calculate the core position */
289 pos = cpu_id + (cluster_id << 2U);
Varun Wadekar43dad672017-01-31 14:53:37 -0800290
Anthony Zhou25d127f2017-03-21 15:58:50 +0800291 /* check for non-existent CPUs */
292 if ((pos == TEGRA186_CLUSTER0_CORE2) || (pos == TEGRA186_CLUSTER0_CORE3)) {
293 ret = PSCI_E_NOT_PRESENT;
294 } else {
295 ret = (int32_t)pos;
296 }
297 }
Varun Wadekar43dad672017-01-31 14:53:37 -0800298
Anthony Zhou25d127f2017-03-21 15:58:50 +0800299 return ret;
Varun Wadekar43dad672017-01-31 14:53:37 -0800300}
Varun Wadekar0ed62702018-06-20 14:30:59 -0700301
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700302/*******************************************************************************
303 * Handler to relocate BL32 image to TZDRAM
304 ******************************************************************************/
Varun Wadekar0ed62702018-06-20 14:30:59 -0700305void plat_relocate_bl32_image(const image_info_t *bl32_img_info)
306{
307 const plat_params_from_bl2_t *plat_bl31_params = plat_get_bl31_plat_params();
308 const entry_point_info_t *bl32_ep_info = bl31_plat_get_next_image_ep_info(SECURE);
309 uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
310
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700311 if ((bl32_img_info != NULL) && (bl32_ep_info != NULL)) {
Varun Wadekar0ed62702018-06-20 14:30:59 -0700312
313 /* Relocate BL32 if it resides outside of the TZDRAM */
314 tzdram_start = plat_bl31_params->tzdram_base;
315 tzdram_end = plat_bl31_params->tzdram_base +
316 plat_bl31_params->tzdram_size;
317 bl32_start = bl32_img_info->image_base;
318 bl32_end = bl32_img_info->image_base + bl32_img_info->image_size;
319
320 assert(tzdram_end > tzdram_start);
321 assert(bl32_end > bl32_start);
322 assert(bl32_ep_info->pc > tzdram_start);
323 assert(bl32_ep_info->pc < tzdram_end);
324
325 /* relocate BL32 */
326 if ((bl32_start >= tzdram_end) || (bl32_end <= tzdram_start)) {
327
328 INFO("Relocate BL32 to TZDRAM\n");
329
330 (void)memcpy16((void *)(uintptr_t)bl32_ep_info->pc,
331 (void *)(uintptr_t)bl32_start,
332 bl32_img_info->image_size);
333
334 /* clean up non-secure intermediate buffer */
335 zeromem((void *)(uintptr_t)bl32_start,
336 bl32_img_info->image_size);
337 }
338 }
339}
Varun Wadekar8d7a02b2018-06-26 16:07:50 -0700340
341/*******************************************************************************
342 * Handler to indicate support for System Suspend
343 ******************************************************************************/
344bool plat_supports_system_suspend(void)
345{
346 return true;
347}