Gitiles
Code Review Sign In
git01.mediatek.com / filogic / atf / e60f1bfe77105f243af3d5afe73576c7e5addd0f / . / plat / nvidia / tegra / soc / t186 / plat_setup.c
blob: 0496f5a5e5ed7131ff0a0e45d6c6485e2dcf5deb [file] [log] [blame]
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]1/*
2 * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <console.h>
32#include <tegra_def.h>
33#include <xlat_tables.h>
34
Varun Wadekarc2c3a2a2016-01-08 17:38:51 -0800[diff] [blame]35/*******************************************************************************
36 * The Tegra power domain tree has a single system level power domain i.e. a
37 * single root node. The first entry in the power domain descriptor specifies
38 * the number of power domains at the highest power level.
39 *******************************************************************************
40 */
41const unsigned char tegra_power_domain_tree_desc[] = {
42 /* No of root nodes */
43 1,
44 /* No of clusters */
45 PLATFORM_CLUSTER_COUNT,
46 /* No of CPU cores - cluster0 */
47 PLATFORM_MAX_CPUS_PER_CLUSTER,
48 /* No of CPU cores - cluster1 */
49 PLATFORM_MAX_CPUS_PER_CLUSTER
50};
51
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]52/*
53 * Table of regions to map using the MMU.
54 */
55static const mmap_region_t tegra_mmap[] = {
56 MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
57 MT_DEVICE | MT_RW | MT_SECURE),
58 MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
59 MT_DEVICE | MT_RW | MT_SECURE),
60 MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
61 MT_DEVICE | MT_RW | MT_SECURE),
62 MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB */
63 MT_DEVICE | MT_RW | MT_SECURE),
64 MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
65 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekare60f1bf2016-02-17 10:10:50 -0800[diff] [blame^]66 MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */
67 MT_DEVICE | MT_RW | MT_SECURE),
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]68 MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
69 MT_DEVICE | MT_RW | MT_SECURE),
70 MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
71 MT_DEVICE | MT_RW | MT_SECURE),
72 MAP_REGION_FLAT(TEGRA_SMMU_BASE, 0x10000, /* 64KB */
73 MT_DEVICE | MT_RW | MT_SECURE),
74 {0}
75};
76
77/*******************************************************************************
78 * Set up the pagetables as per the platform memory map & initialize the MMU
79 ******************************************************************************/
80const mmap_region_t *plat_get_mmio_map(void)
81{
82 /* MMIO space */
83 return tegra_mmap;
84}
85
86/*******************************************************************************
87 * Handler to get the System Counter Frequency
88 ******************************************************************************/
89unsigned int plat_get_syscnt_freq2(void)
90{
Varun Wadekar20c94292016-01-04 10:57:45 -0800[diff] [blame]91 return 31250000;
Varun Wadekar921b9062015-08-25 17:03:14 +0530[diff] [blame]92}
93
94/*******************************************************************************
95 * Maximum supported UART controllers
96 ******************************************************************************/
97#define TEGRA186_MAX_UART_PORTS 7
98
99/*******************************************************************************
100 * This variable holds the UART port base addresses
101 ******************************************************************************/
102static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
103 0, /* undefined - treated as an error case */
104 TEGRA_UARTA_BASE,
105 TEGRA_UARTB_BASE,
106 TEGRA_UARTC_BASE,
107 TEGRA_UARTD_BASE,
108 TEGRA_UARTE_BASE,
109 TEGRA_UARTF_BASE,
110 TEGRA_UARTG_BASE,
111};
112
113/*******************************************************************************
114 * Retrieve the UART controller base to be used as the console
115 ******************************************************************************/
116uint32_t plat_get_console_from_id(int id)
117{
118 if (id > TEGRA186_MAX_UART_PORTS)
119 return 0;
120
121 return tegra186_uart_addresses[id];
122}