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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Alexei Fedorov813c9f92020-03-03 13:31:58 +00002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Varun Wadekar787a1292018-06-18 16:15:51 -07003 * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01006 */
7
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01008#ifndef ARCH_H
9#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +010010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010012
13/*******************************************************************************
14 * MIDR bit definitions
15 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070016#define MIDR_IMPL_MASK U(0xff)
17#define MIDR_IMPL_SHIFT U(0x18)
18#define MIDR_VAR_SHIFT U(20)
19#define MIDR_VAR_BITS U(4)
20#define MIDR_VAR_MASK U(0xf)
21#define MIDR_REV_SHIFT U(0)
22#define MIDR_REV_BITS U(4)
23#define MIDR_REV_MASK U(0xf)
24#define MIDR_PN_MASK U(0xfff)
25#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010026
27/*******************************************************************************
28 * MPIDR macros
29 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010030#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070032#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
33#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010034#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070035#define MPIDR_AFF0_SHIFT U(0)
36#define MPIDR_AFF1_SHIFT U(8)
37#define MPIDR_AFF2_SHIFT U(16)
38#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000039#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010040#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070041#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000042#define MPIDR_AFFLVL0 ULL(0x0)
43#define MPIDR_AFFLVL1 ULL(0x1)
44#define MPIDR_AFFLVL2 ULL(0x2)
45#define MPIDR_AFFLVL3 ULL(0x3)
46#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000047#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010048 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000049#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010050 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000051#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010052 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000053#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010054 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000055/*
56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
57 * add one while using this macro to define array sizes.
58 * TODO: Support only the first 3 affinity levels for now.
59 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070060#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000062#define MPID_MASK (MPIDR_MT_MASK | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
67
68#define MPIDR_AFF_ID(mpid, n) \
69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
70
71/*
72 * An invalid MPID. This value can be used by functions that return an MPID to
73 * indicate an error.
74 */
75#define INVALID_MPID U(0xFFFFFFFF)
Achin Gupta4f6ad662013-10-25 09:08:21 +010076
77/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010078 * Definitions for CPU system register interface to GICv3
79 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000080#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
81#define ICC_SGI1R S3_0_C12_C11_5
82#define ICC_SRE_EL1 S3_0_C12_C12_5
83#define ICC_SRE_EL2 S3_4_C12_C9_5
84#define ICC_SRE_EL3 S3_6_C12_C12_5
85#define ICC_CTLR_EL1 S3_0_C12_C12_4
86#define ICC_CTLR_EL3 S3_6_C12_C12_4
87#define ICC_PMR_EL1 S3_0_C4_C6_0
88#define ICC_RPR_EL1 S3_0_C12_C11_3
89#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
90#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
91#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
92#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
93#define ICC_IAR0_EL1 S3_0_c12_c8_0
94#define ICC_IAR1_EL1 S3_0_c12_c12_0
95#define ICC_EOIR0_EL1 S3_0_c12_c8_1
96#define ICC_EOIR1_EL1 S3_0_c12_c12_1
97#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010098
99/*******************************************************************************
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000100 * Definitions for EL2 system registers for save/restore routine
101 ******************************************************************************/
102
103#define CNTPOFF_EL2 S3_4_C14_C0_6
104#define HAFGRTR_EL2 S3_4_C3_C1_6
105#define HDFGRTR_EL2 S3_4_C3_C1_4
106#define HDFGWTR_EL2 S3_4_C3_C1_5
107#define HFGITR_EL2 S3_4_C1_C1_6
108#define HFGRTR_EL2 S3_4_C1_C1_4
109#define HFGWTR_EL2 S3_4_C1_C1_5
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000110#define ICH_HCR_EL2 S3_4_C12_C11_0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000111#define ICH_VMCR_EL2 S3_4_C12_C11_7
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000112#define MPAMVPM0_EL2 S3_4_C10_C5_0
113#define MPAMVPM1_EL2 S3_4_C10_C5_1
114#define MPAMVPM2_EL2 S3_4_C10_C5_2
115#define MPAMVPM3_EL2 S3_4_C10_C5_3
116#define MPAMVPM4_EL2 S3_4_C10_C5_4
117#define MPAMVPM5_EL2 S3_4_C10_C5_5
118#define MPAMVPM6_EL2 S3_4_C10_C5_6
119#define MPAMVPM7_EL2 S3_4_C10_C5_7
120#define MPAMVPMV_EL2 S3_4_C10_C4_1
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000121#define TRFCR_EL2 S3_4_C1_C2_1
122#define PMSCR_EL2 S3_4_C9_C9_0
123#define TFSR_EL2 S3_4_C5_C6_0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000124
125/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +0000126 * Generic timer memory mapped registers & offsets
127 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700128#define CNTCR_OFF U(0x000)
Yann Gautier007d7452019-04-17 13:47:07 +0200129#define CNTCV_OFF U(0x008)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700130#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +0000131
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700132#define CNTCR_EN (U(1) << 0)
133#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100134#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000135
136/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137 * System register bit definitions
138 ******************************************************************************/
139/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700140#define LOUIS_SHIFT U(21)
141#define LOC_SHIFT U(24)
Alexei Fedorova95a5892019-07-29 17:22:53 +0100142#define CTYPE_SHIFT(n) U(3 * (n - 1))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700143#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144
145/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700146#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100148/* Data cache set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700149#define DCISW U(0x0)
150#define DCCISW U(0x1)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000151#if ERRATA_A53_827319
152#define DCCSW DCCISW
153#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700154#define DCCSW U(0x2)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000155#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100156
157/* ID_AA64PFR0_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700158#define ID_AA64PFR0_EL0_SHIFT U(0)
159#define ID_AA64PFR0_EL1_SHIFT U(4)
160#define ID_AA64PFR0_EL2_SHIFT U(8)
161#define ID_AA64PFR0_EL3_SHIFT U(12)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100162#define ID_AA64PFR0_AMU_SHIFT U(44)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100163#define ID_AA64PFR0_AMU_MASK ULL(0xf)
164#define ID_AA64PFR0_ELX_MASK ULL(0xf)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100165#define ID_AA64PFR0_GIC_SHIFT U(24)
166#define ID_AA64PFR0_GIC_WIDTH U(4)
167#define ID_AA64PFR0_GIC_MASK ULL(0xf)
David Cunadoce88eee2017-10-20 11:30:57 +0100168#define ID_AA64PFR0_SVE_SHIFT U(32)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100169#define ID_AA64PFR0_SVE_MASK ULL(0xf)
Achin Gupta023c1552019-10-11 14:44:05 +0100170#define ID_AA64PFR0_SEL2_SHIFT U(36)
Artsem Artsemenkaa5334472019-11-26 16:40:31 +0000171#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100172#define ID_AA64PFR0_MPAM_SHIFT U(40)
173#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
Sathees Balya0911df12018-12-06 13:33:24 +0000174#define ID_AA64PFR0_DIT_SHIFT U(48)
175#define ID_AA64PFR0_DIT_MASK ULL(0xf)
176#define ID_AA64PFR0_DIT_LENGTH U(4)
177#define ID_AA64PFR0_DIT_SUPPORTED U(1)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000178#define ID_AA64PFR0_CSV2_SHIFT U(56)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100179#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
Dimitris Papastamos43e05ec2018-01-02 15:53:01 +0000180#define ID_AA64PFR0_CSV2_LENGTH U(4)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100182/* Exception level handling */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100183#define EL_IMPL_NONE ULL(0)
184#define EL_IMPL_A64ONLY ULL(1)
185#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000186
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100187/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
188#define ID_AA64DFR0_PMS_SHIFT U(32)
189#define ID_AA64DFR0_PMS_MASK ULL(0xf)
Achin Gupta92712a52015-09-03 14:18:02 +0100190
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000191/* ID_AA64ISAR1_EL1 definitions */
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000192#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000193#define ID_AA64ISAR1_GPI_SHIFT U(28)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000194#define ID_AA64ISAR1_GPI_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000195#define ID_AA64ISAR1_GPA_SHIFT U(24)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000196#define ID_AA64ISAR1_GPA_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000197#define ID_AA64ISAR1_API_SHIFT U(8)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000198#define ID_AA64ISAR1_API_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000199#define ID_AA64ISAR1_APA_SHIFT U(4)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000200#define ID_AA64ISAR1_APA_MASK ULL(0xf)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000201
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000202/* ID_AA64MMFR0_EL1 definitions */
203#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
204#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
205
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700206#define PARANGE_0000 U(32)
207#define PARANGE_0001 U(36)
208#define PARANGE_0010 U(40)
209#define PARANGE_0011 U(42)
210#define PARANGE_0100 U(44)
211#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000212#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000213
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100214#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100215#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
216#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
217#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100218
219#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100220#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
221#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
222#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100223
224#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100225#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
226#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
227#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100228
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000229/* ID_AA64MMFR2_EL1 definitions */
230#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
Sathees Balya74155972019-01-25 11:36:01 +0000231
232#define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
233#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
234
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000235#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
236#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
237
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000238/* ID_AA64PFR1_EL1 definitions */
239#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
240#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
241
242#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
243
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100244#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
245#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
246
247#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
248
Soby Mathew830f0ad2019-07-12 09:23:38 +0100249#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
250#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
251
252#define MTE_UNIMPLEMENTED ULL(0)
253#define MTE_IMPLEMENTED_EL0 ULL(1) /* MTE is only implemented at EL0 */
254#define MTE_IMPLEMENTED_ELX ULL(2) /* MTE is implemented at all ELs */
255
Achin Gupta4f6ad662013-10-25 09:08:21 +0100256/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700257#define ID_PFR1_VIRTEXT_SHIFT U(12)
258#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz34235a32018-07-11 16:45:49 +0100259#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100260 & ID_PFR1_VIRTEXT_MASK)
261
262/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100263#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700264 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
265 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100266
John Powella5c66362020-03-20 14:21:05 -0500267#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
268 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200269#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700270 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
271 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200272
David Cunadofee86532017-04-13 22:38:29 +0100273#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
274 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
275 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
276
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000277#define SCTLR_M_BIT (ULL(1) << 0)
278#define SCTLR_A_BIT (ULL(1) << 1)
279#define SCTLR_C_BIT (ULL(1) << 2)
280#define SCTLR_SA_BIT (ULL(1) << 3)
281#define SCTLR_SA0_BIT (ULL(1) << 4)
282#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
283#define SCTLR_ITD_BIT (ULL(1) << 7)
284#define SCTLR_SED_BIT (ULL(1) << 8)
285#define SCTLR_UMA_BIT (ULL(1) << 9)
286#define SCTLR_I_BIT (ULL(1) << 12)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100287#define SCTLR_EnDB_BIT (ULL(1) << 13)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000288#define SCTLR_DZE_BIT (ULL(1) << 14)
289#define SCTLR_UCT_BIT (ULL(1) << 15)
290#define SCTLR_NTWI_BIT (ULL(1) << 16)
291#define SCTLR_NTWE_BIT (ULL(1) << 18)
292#define SCTLR_WXN_BIT (ULL(1) << 19)
293#define SCTLR_UWXN_BIT (ULL(1) << 20)
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000294#define SCTLR_IESB_BIT (ULL(1) << 21)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000295#define SCTLR_E0E_BIT (ULL(1) << 24)
296#define SCTLR_EE_BIT (ULL(1) << 25)
297#define SCTLR_UCI_BIT (ULL(1) << 26)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100298#define SCTLR_EnDA_BIT (ULL(1) << 27)
299#define SCTLR_EnIB_BIT (ULL(1) << 30)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000300#define SCTLR_EnIA_BIT (ULL(1) << 31)
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100301#define SCTLR_BT0_BIT (ULL(1) << 35)
302#define SCTLR_BT1_BIT (ULL(1) << 36)
303#define SCTLR_BT_BIT (ULL(1) << 36)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000304#define SCTLR_DSSBS_BIT (ULL(1) << 44)
David Cunadofee86532017-04-13 22:38:29 +0100305#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100306
Achin Gupta4f6ad662013-10-25 09:08:21 +0100307/* CPACR_El1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700308#define CPACR_EL1_FPEN(x) ((x) << 20)
309#define CPACR_EL1_FP_TRAP_EL0 U(0x1)
310#define CPACR_EL1_FP_TRAP_ALL U(0x2)
311#define CPACR_EL1_FP_TRAP_NONE U(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100312
313/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700314#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
Soby Mathew830f0ad2019-07-12 09:23:38 +0100315#define SCR_ATA_BIT (U(1) << 26)
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000316#define SCR_FIEN_BIT (U(1) << 21)
Achin Gupta023c1552019-10-11 14:44:05 +0100317#define SCR_EEL2_BIT (U(1) << 18)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100318#define SCR_API_BIT (U(1) << 17)
319#define SCR_APK_BIT (U(1) << 16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700320#define SCR_TWE_BIT (U(1) << 13)
321#define SCR_TWI_BIT (U(1) << 12)
322#define SCR_ST_BIT (U(1) << 11)
323#define SCR_RW_BIT (U(1) << 10)
324#define SCR_SIF_BIT (U(1) << 9)
325#define SCR_HCE_BIT (U(1) << 8)
326#define SCR_SMD_BIT (U(1) << 7)
327#define SCR_EA_BIT (U(1) << 3)
328#define SCR_FIQ_BIT (U(1) << 2)
329#define SCR_IRQ_BIT (U(1) << 1)
330#define SCR_NS_BIT (U(1) << 0)
331#define SCR_VALID_BIT_MASK U(0x2f8f)
David Cunadofee86532017-04-13 22:38:29 +0100332#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100333
David Cunadofee86532017-04-13 22:38:29 +0100334/* MDCR_EL3 definitions */
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100335#define MDCR_SCCD_BIT (ULL(1) << 23)
336#define MDCR_SPME_BIT (ULL(1) << 17)
337#define MDCR_SDD_BIT (ULL(1) << 16)
dp-arm595d0d52017-02-08 11:51:50 +0000338#define MDCR_SPD32(x) ((x) << 14)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000339#define MDCR_SPD32_LEGACY ULL(0x0)
340#define MDCR_SPD32_DISABLE ULL(0x2)
341#define MDCR_SPD32_ENABLE ULL(0x3)
dp-armee3457b2017-05-23 09:32:49 +0100342#define MDCR_NSPB(x) ((x) << 12)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000343#define MDCR_NSPB_EL1 ULL(0x3)
344#define MDCR_TDOSA_BIT (ULL(1) << 10)
345#define MDCR_TDA_BIT (ULL(1) << 9)
346#define MDCR_TPM_BIT (ULL(1) << 6)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000347#define MDCR_EL3_RESET_VAL ULL(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000348
David Cunadofee86532017-04-13 22:38:29 +0100349/* MDCR_EL2 definitions */
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100350#define MDCR_EL2_HLP (U(1) << 26)
351#define MDCR_EL2_HCCD (U(1) << 23)
352#define MDCR_EL2_TTRF (U(1) << 19)
353#define MDCR_EL2_HPMD (U(1) << 17)
dp-armee3457b2017-05-23 09:32:49 +0100354#define MDCR_EL2_TPMS (U(1) << 14)
355#define MDCR_EL2_E2PB(x) ((x) << 12)
356#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100357#define MDCR_EL2_TDRA_BIT (U(1) << 11)
358#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
359#define MDCR_EL2_TDA_BIT (U(1) << 9)
360#define MDCR_EL2_TDE_BIT (U(1) << 8)
361#define MDCR_EL2_HPME_BIT (U(1) << 7)
362#define MDCR_EL2_TPM_BIT (U(1) << 6)
363#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
364#define MDCR_EL2_RESET_VAL U(0x0)
365
366/* HSTR_EL2 definitions */
367#define HSTR_EL2_RESET_VAL U(0x0)
368#define HSTR_EL2_T_MASK U(0xff)
369
370/* CNTHP_CTL_EL2 definitions */
371#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
372#define CNTHP_CTL_RESET_VAL U(0x0)
373
374/* VTTBR_EL2 definitions */
375#define VTTBR_RESET_VAL ULL(0x0)
376#define VTTBR_VMID_MASK ULL(0xff)
377#define VTTBR_VMID_SHIFT U(48)
378#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
379#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000380
Achin Gupta4f6ad662013-10-25 09:08:21 +0100381/* HCR definitions */
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100382#define HCR_API_BIT (ULL(1) << 41)
383#define HCR_APK_BIT (ULL(1) << 40)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000384#define HCR_TGE_BIT (ULL(1) << 27)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700385#define HCR_RW_SHIFT U(31)
386#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100387#define HCR_AMO_BIT (ULL(1) << 5)
388#define HCR_IMO_BIT (ULL(1) << 4)
389#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100390
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100391/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700392#define ISR_A_SHIFT U(8)
393#define ISR_I_SHIFT U(7)
394#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100395
Achin Gupta4f6ad662013-10-25 09:08:21 +0100396/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100397#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700398#define EVNTEN_BIT (U(1) << 2)
399#define EL1PCEN_BIT (U(1) << 1)
400#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100401
402/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700403#define EL0PTEN_BIT (U(1) << 9)
404#define EL0VTEN_BIT (U(1) << 8)
405#define EL0PCTEN_BIT (U(1) << 0)
406#define EL0VCTEN_BIT (U(1) << 1)
407#define EVNTEN_BIT (U(1) << 2)
408#define EVNTDIR_BIT (U(1) << 3)
409#define EVNTI_SHIFT U(4)
410#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100411
412/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700413#define TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100414#define TAM_BIT (U(1) << 30)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700415#define TTA_BIT (U(1) << 20)
416#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100417#define CPTR_EZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100418#define CPTR_EL3_RESET_VAL U(0x0)
419
420/* CPTR_EL2 definitions */
421#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
422#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100423#define CPTR_EL2_TAM_BIT (U(1) << 30)
David Cunadofee86532017-04-13 22:38:29 +0100424#define CPTR_EL2_TTA_BIT (U(1) << 20)
425#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100426#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100427#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100428
429/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700430#define DAIF_FIQ_BIT (U(1) << 0)
431#define DAIF_IRQ_BIT (U(1) << 1)
432#define DAIF_ABT_BIT (U(1) << 2)
433#define DAIF_DBG_BIT (U(1) << 3)
434#define SPSR_DAIF_SHIFT U(6)
435#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100436
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700437#define SPSR_AIF_SHIFT U(6)
438#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100439
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700440#define SPSR_E_SHIFT U(9)
441#define SPSR_E_MASK U(0x1)
442#define SPSR_E_LITTLE U(0x0)
443#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100444
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700445#define SPSR_T_SHIFT U(5)
446#define SPSR_T_MASK U(0x1)
447#define SPSR_T_ARM U(0x0)
448#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100449
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000450#define SPSR_M_SHIFT U(4)
451#define SPSR_M_MASK U(0x1)
452#define SPSR_M_AARCH64 U(0x0)
453#define SPSR_M_AARCH32 U(0x1)
454
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000455#define SPSR_EL_SHIFT U(2)
456#define SPSR_EL_WIDTH U(2)
457
John Tsichritzis55534172019-07-23 11:12:41 +0100458#define SPSR_SSBS_BIT_AARCH64 BIT_64(12)
459#define SPSR_SSBS_BIT_AARCH32 BIT_64(23)
460
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100461#define DISABLE_ALL_EXCEPTIONS \
462 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
463
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000464#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
465
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000466/*
467 * RMR_EL3 definitions
468 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700469#define RMR_EL3_RR_BIT (U(1) << 1)
470#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000471
472/*
473 * HI-VECTOR address for AArch32 state
474 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000475#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100476
477/*
478 * TCR defintions
479 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000480#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100481#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700482#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100483#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700484#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700485
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100486#define TCR_TxSZ_MIN ULL(16)
487#define TCR_TxSZ_MAX ULL(39)
Sathees Balya74155972019-01-25 11:36:01 +0000488#define TCR_TxSZ_MAX_TTST ULL(48)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100489
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000490#define TCR_T0SZ_SHIFT U(0)
491#define TCR_T1SZ_SHIFT U(16)
492
Lin Ma741a3822014-06-27 16:56:30 -0700493/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100494#define TCR_PS_BITS_4GB ULL(0x0)
495#define TCR_PS_BITS_64GB ULL(0x1)
496#define TCR_PS_BITS_1TB ULL(0x2)
497#define TCR_PS_BITS_4TB ULL(0x3)
498#define TCR_PS_BITS_16TB ULL(0x4)
499#define TCR_PS_BITS_256TB ULL(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100500
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700501#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
502#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
503#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
504#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
505#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
506#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100507
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100508#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
509#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
510#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
511#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100512
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100513#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
514#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
515#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
516#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100517
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100518#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
519#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
520#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100521
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000522#define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
523#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
524#define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
525#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
526
527#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
528#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
529#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
530#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
531
532#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
533#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
534#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
535
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100536#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100537#define TCR_TG0_MASK ULL(3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100538#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
539#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
540#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
541
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000542#define TCR_TG1_SHIFT U(30)
543#define TCR_TG1_MASK ULL(3)
544#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
545#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
546#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
547
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100548#define TCR_EPD0_BIT (ULL(1) << 7)
549#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100550
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700551#define MODE_SP_SHIFT U(0x0)
552#define MODE_SP_MASK U(0x1)
553#define MODE_SP_EL0 U(0x0)
554#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100555
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700556#define MODE_RW_SHIFT U(0x4)
557#define MODE_RW_MASK U(0x1)
558#define MODE_RW_64 U(0x0)
559#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100560
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700561#define MODE_EL_SHIFT U(0x2)
562#define MODE_EL_MASK U(0x3)
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000563#define MODE_EL_WIDTH U(0x2)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700564#define MODE_EL3 U(0x3)
565#define MODE_EL2 U(0x2)
566#define MODE_EL1 U(0x1)
567#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100568
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700569#define MODE32_SHIFT U(0)
570#define MODE32_MASK U(0xf)
571#define MODE32_usr U(0x0)
572#define MODE32_fiq U(0x1)
573#define MODE32_irq U(0x2)
574#define MODE32_svc U(0x3)
575#define MODE32_mon U(0x6)
576#define MODE32_abt U(0x7)
577#define MODE32_hyp U(0xa)
578#define MODE32_und U(0xb)
579#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100580
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100581#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
582#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
583#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
584#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100585
John Tsichritzis55534172019-07-23 11:12:41 +0100586#define SPSR_64(el, sp, daif) \
587 (((MODE_RW_64 << MODE_RW_SHIFT) | \
588 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
589 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
590 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
591 (~(SPSR_SSBS_BIT_AARCH64)))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100592
593#define SPSR_MODE32(mode, isa, endian, aif) \
John Tsichritzis55534172019-07-23 11:12:41 +0100594 (((MODE_RW_32 << MODE_RW_SHIFT) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700595 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
596 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
597 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
John Tsichritzis55534172019-07-23 11:12:41 +0100598 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \
599 (~(SPSR_SSBS_BIT_AARCH32)))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100600
Dan Handley0cdebbd2015-03-30 17:15:16 +0100601/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100602 * TTBR Definitions
603 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100604#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100605
606/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100607 * CTR_EL0 definitions
608 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700609#define CTR_CWG_SHIFT U(24)
610#define CTR_CWG_MASK U(0xf)
611#define CTR_ERG_SHIFT U(20)
612#define CTR_ERG_MASK U(0xf)
613#define CTR_DMINLINE_SHIFT U(16)
614#define CTR_DMINLINE_MASK U(0xf)
615#define CTR_L1IP_SHIFT U(14)
616#define CTR_L1IP_MASK U(0x3)
617#define CTR_IMINLINE_SHIFT U(0)
618#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100619
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700620#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100621
Achin Gupta405406d2014-05-09 12:00:17 +0100622/* Physical timer control register bit fields shifts and masks */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700623#define CNTP_CTL_ENABLE_SHIFT U(0)
624#define CNTP_CTL_IMASK_SHIFT U(1)
625#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100626
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700627#define CNTP_CTL_ENABLE_MASK U(1)
628#define CNTP_CTL_IMASK_MASK U(1)
629#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100630
Varun Wadekar787a1292018-06-18 16:15:51 -0700631/* Physical timer control macros */
632#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
633#define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT)
634
Achin Gupta4f6ad662013-10-25 09:08:21 +0100635/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700636#define ESR_EC_SHIFT U(26)
637#define ESR_EC_MASK U(0x3f)
638#define ESR_EC_LENGTH U(6)
Justin Chadwell83e04882019-08-20 11:01:52 +0100639#define ESR_ISS_SHIFT U(0)
640#define ESR_ISS_LENGTH U(25)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700641#define EC_UNKNOWN U(0x0)
642#define EC_WFE_WFI U(0x1)
643#define EC_AARCH32_CP15_MRC_MCR U(0x3)
644#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
645#define EC_AARCH32_CP14_MRC_MCR U(0x5)
646#define EC_AARCH32_CP14_LDC_STC U(0x6)
647#define EC_FP_SIMD U(0x7)
648#define EC_AARCH32_CP10_MRC U(0x8)
649#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
650#define EC_ILLEGAL U(0xe)
651#define EC_AARCH32_SVC U(0x11)
652#define EC_AARCH32_HVC U(0x12)
653#define EC_AARCH32_SMC U(0x13)
654#define EC_AARCH64_SVC U(0x15)
655#define EC_AARCH64_HVC U(0x16)
656#define EC_AARCH64_SMC U(0x17)
657#define EC_AARCH64_SYS U(0x18)
658#define EC_IABORT_LOWER_EL U(0x20)
659#define EC_IABORT_CUR_EL U(0x21)
660#define EC_PC_ALIGN U(0x22)
661#define EC_DABORT_LOWER_EL U(0x24)
662#define EC_DABORT_CUR_EL U(0x25)
663#define EC_SP_ALIGN U(0x26)
664#define EC_AARCH32_FP U(0x28)
665#define EC_AARCH64_FP U(0x2c)
666#define EC_SERROR U(0x2f)
Justin Chadwell83e04882019-08-20 11:01:52 +0100667#define EC_BRK U(0x3c)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100668
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000669/*
670 * External Abort bit in Instruction and Data Aborts synchronous exception
671 * syndromes.
672 */
673#define ESR_ISS_EABORT_EA_BIT U(9)
674
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700675#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100676
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800677/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700678#define RMR_RESET_REQUEST_SHIFT U(0x1)
679#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800680
Dan Handleyed6ff952014-05-14 17:44:19 +0100681/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000682 * Definitions of register offsets, fields and macros for CPU system
683 * instructions.
684 ******************************************************************************/
685
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700686#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000687#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
688#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
689
690/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100691 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
692 * system level implementation of the Generic Timer.
693 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100694#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700695#define CNTNSAR U(0x4)
696#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +0100697
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700698#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
699#define CNTACR_RPCT_SHIFT U(0x0)
700#define CNTACR_RVCT_SHIFT U(0x1)
701#define CNTACR_RFRQ_SHIFT U(0x2)
702#define CNTACR_RVOFF_SHIFT U(0x3)
703#define CNTACR_RWVT_SHIFT U(0x4)
704#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +0100705
Soby Mathew2d9f7952018-06-11 16:21:30 +0100706/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000707 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +0100708 * system level implementation of the Generic Timer.
709 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000710/* Physical Count register. */
711#define CNTPCT_LO U(0x0)
712/* Counter Frequency register. */
713#define CNTBASEN_CNTFRQ U(0x10)
714/* Physical Timer CompareValue register. */
715#define CNTP_CVAL_LO U(0x20)
716/* Physical Timer Control register. */
717#define CNTP_CTL U(0x2c)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100718
David Cunado5f55e282016-10-31 17:37:34 +0000719/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +0100720#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700721#define PMCR_EL0_N_SHIFT U(11)
722#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000723#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100724#define PMCR_EL0_LP_BIT (U(1) << 7)
David Cunado4168f2f2017-10-02 17:41:39 +0100725#define PMCR_EL0_LC_BIT (U(1) << 6)
726#define PMCR_EL0_DP_BIT (U(1) << 5)
727#define PMCR_EL0_X_BIT (U(1) << 4)
728#define PMCR_EL0_D_BIT (U(1) << 3)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100729#define PMCR_EL0_C_BIT (U(1) << 2)
730#define PMCR_EL0_P_BIT (U(1) << 1)
731#define PMCR_EL0_E_BIT (U(1) << 0)
David Cunado5f55e282016-10-31 17:37:34 +0000732
Isla Mitchell02c63072017-07-21 14:44:36 +0100733/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +0100734 * Definitions for system register interface to SVE
735 ******************************************************************************/
736#define ZCR_EL3 S3_6_C1_C2_0
737#define ZCR_EL2 S3_4_C1_C2_0
738
739/* ZCR_EL3 definitions */
740#define ZCR_EL3_LEN_MASK U(0xf)
741
742/* ZCR_EL2 definitions */
743#define ZCR_EL2_LEN_MASK U(0xf)
744
745/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +0100746 * Definitions of MAIR encodings for device and normal memory
747 ******************************************************************************/
748/*
749 * MAIR encodings for device memory attributes.
750 */
751#define MAIR_DEV_nGnRnE ULL(0x0)
752#define MAIR_DEV_nGnRE ULL(0x4)
753#define MAIR_DEV_nGRE ULL(0x8)
754#define MAIR_DEV_GRE ULL(0xc)
755
756/*
757 * MAIR encodings for normal memory attributes.
758 *
759 * Cache Policy
760 * WT: Write Through
761 * WB: Write Back
762 * NC: Non-Cacheable
763 *
764 * Transient Hint
765 * NTR: Non-Transient
766 * TR: Transient
767 *
768 * Allocation Policy
769 * RA: Read Allocate
770 * WA: Write Allocate
771 * RWA: Read and Write Allocate
772 * NA: No Allocation
773 */
774#define MAIR_NORM_WT_TR_WA ULL(0x1)
775#define MAIR_NORM_WT_TR_RA ULL(0x2)
776#define MAIR_NORM_WT_TR_RWA ULL(0x3)
777#define MAIR_NORM_NC ULL(0x4)
778#define MAIR_NORM_WB_TR_WA ULL(0x5)
779#define MAIR_NORM_WB_TR_RA ULL(0x6)
780#define MAIR_NORM_WB_TR_RWA ULL(0x7)
781#define MAIR_NORM_WT_NTR_NA ULL(0x8)
782#define MAIR_NORM_WT_NTR_WA ULL(0x9)
783#define MAIR_NORM_WT_NTR_RA ULL(0xa)
784#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
785#define MAIR_NORM_WB_NTR_NA ULL(0xc)
786#define MAIR_NORM_WB_NTR_WA ULL(0xd)
787#define MAIR_NORM_WB_NTR_RA ULL(0xe)
788#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
789
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100790#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +0100791
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100792#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
793 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +0100794
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100795/* PAR_EL1 fields */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100796#define PAR_F_SHIFT U(0)
797#define PAR_F_MASK ULL(0x1)
798#define PAR_ADDR_SHIFT U(12)
799#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +0100800
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100801/*******************************************************************************
802 * Definitions for system register interface to SPE
803 ******************************************************************************/
804#define PMBLIMITR_EL1 S3_0_C9_C10_0
805
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100806/*******************************************************************************
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100807 * Definitions for system register interface to MPAM
808 ******************************************************************************/
809#define MPAMIDR_EL1 S3_0_C10_C4_4
810#define MPAM2_EL2 S3_4_C10_C5_0
811#define MPAMHCR_EL2 S3_4_C10_C4_0
812#define MPAM3_EL3 S3_6_C10_C5_0
813
814/*******************************************************************************
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100815 * Definitions for system register interface to AMU for ARMv8.4 onwards
816 ******************************************************************************/
817#define AMCR_EL0 S3_3_C13_C2_0
818#define AMCFGR_EL0 S3_3_C13_C2_1
819#define AMCGCR_EL0 S3_3_C13_C2_2
820#define AMUSERENR_EL0 S3_3_C13_C2_3
821#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
822#define AMCNTENSET0_EL0 S3_3_C13_C2_5
823#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
824#define AMCNTENSET1_EL0 S3_3_C13_C3_1
825
826/* Activity Monitor Group 0 Event Counter Registers */
827#define AMEVCNTR00_EL0 S3_3_C13_C4_0
828#define AMEVCNTR01_EL0 S3_3_C13_C4_1
829#define AMEVCNTR02_EL0 S3_3_C13_C4_2
830#define AMEVCNTR03_EL0 S3_3_C13_C4_3
831
832/* Activity Monitor Group 0 Event Type Registers */
833#define AMEVTYPER00_EL0 S3_3_C13_C6_0
834#define AMEVTYPER01_EL0 S3_3_C13_C6_1
835#define AMEVTYPER02_EL0 S3_3_C13_C6_2
836#define AMEVTYPER03_EL0 S3_3_C13_C6_3
837
Dimitris Papastamos525c37a2017-11-13 09:49:45 +0000838/* Activity Monitor Group 1 Event Counter Registers */
839#define AMEVCNTR10_EL0 S3_3_C13_C12_0
840#define AMEVCNTR11_EL0 S3_3_C13_C12_1
841#define AMEVCNTR12_EL0 S3_3_C13_C12_2
842#define AMEVCNTR13_EL0 S3_3_C13_C12_3
843#define AMEVCNTR14_EL0 S3_3_C13_C12_4
844#define AMEVCNTR15_EL0 S3_3_C13_C12_5
845#define AMEVCNTR16_EL0 S3_3_C13_C12_6
846#define AMEVCNTR17_EL0 S3_3_C13_C12_7
847#define AMEVCNTR18_EL0 S3_3_C13_C13_0
848#define AMEVCNTR19_EL0 S3_3_C13_C13_1
849#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
850#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
851#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
852#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
853#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
854#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
855
856/* Activity Monitor Group 1 Event Type Registers */
857#define AMEVTYPER10_EL0 S3_3_C13_C14_0
858#define AMEVTYPER11_EL0 S3_3_C13_C14_1
859#define AMEVTYPER12_EL0 S3_3_C13_C14_2
860#define AMEVTYPER13_EL0 S3_3_C13_C14_3
861#define AMEVTYPER14_EL0 S3_3_C13_C14_4
862#define AMEVTYPER15_EL0 S3_3_C13_C14_5
863#define AMEVTYPER16_EL0 S3_3_C13_C14_6
864#define AMEVTYPER17_EL0 S3_3_C13_C14_7
865#define AMEVTYPER18_EL0 S3_3_C13_C15_0
866#define AMEVTYPER19_EL0 S3_3_C13_C15_1
867#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
868#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
869#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
870#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
871#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
872#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
873
874/* AMCGCR_EL0 definitions */
875#define AMCGCR_EL0_CG1NC_SHIFT U(8)
876#define AMCGCR_EL0_CG1NC_LENGTH U(8)
877#define AMCGCR_EL0_CG1NC_MASK U(0xff)
878
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100879/* MPAM register definitions */
880#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
Louis Mayencourtbdfa1032019-02-11 11:25:50 +0000881#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
882
883#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
884#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100885
886#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
887
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100888/*******************************************************************************
889 * RAS system registers
Sathees Balya0911df12018-12-06 13:33:24 +0000890 ******************************************************************************/
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100891#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100892#define DISR_A_BIT U(31)
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +0100893
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000894#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100895#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000896
897#define ERRSELR_EL1 S3_0_C5_C3_1
898
899/* System register access to Standard Error Record registers */
900#define ERXFR_EL1 S3_0_C5_C4_0
901#define ERXCTLR_EL1 S3_0_C5_C4_1
902#define ERXSTATUS_EL1 S3_0_C5_C4_2
903#define ERXADDR_EL1 S3_0_C5_C4_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000904#define ERXPFGF_EL1 S3_0_C5_C4_4
905#define ERXPFGCTL_EL1 S3_0_C5_C4_5
906#define ERXPFGCDN_EL1 S3_0_C5_C4_6
Jan Dabros82ef8bf2018-08-30 13:52:23 +0200907#define ERXMISC0_EL1 S3_0_C5_C5_0
908#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +0000909
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000910#define ERXCTLR_ED_BIT (U(1) << 0)
911#define ERXCTLR_UE_BIT (U(1) << 4)
912
913#define ERXPFGCTL_UC_BIT (U(1) << 1)
914#define ERXPFGCTL_UEU_BIT (U(1) << 2)
915#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
916
917/*******************************************************************************
918 * Armv8.3 Pointer Authentication Registers
Sathees Balya0911df12018-12-06 13:33:24 +0000919 ******************************************************************************/
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000920#define APIAKeyLo_EL1 S3_0_C2_C1_0
921#define APIAKeyHi_EL1 S3_0_C2_C1_1
922#define APIBKeyLo_EL1 S3_0_C2_C1_2
923#define APIBKeyHi_EL1 S3_0_C2_C1_3
924#define APDAKeyLo_EL1 S3_0_C2_C2_0
925#define APDAKeyHi_EL1 S3_0_C2_C2_1
926#define APDBKeyLo_EL1 S3_0_C2_C2_2
927#define APDBKeyHi_EL1 S3_0_C2_C2_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000928#define APGAKeyLo_EL1 S3_0_C2_C3_0
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000929#define APGAKeyHi_EL1 S3_0_C2_C3_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000930
Sathees Balya0911df12018-12-06 13:33:24 +0000931/*******************************************************************************
932 * Armv8.4 Data Independent Timing Registers
933 ******************************************************************************/
934#define DIT S3_3_C4_C2_5
935#define DIT_BIT BIT(24)
936
John Tsichritzis1f9ff492019-03-04 16:41:26 +0000937/*******************************************************************************
938 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
939 ******************************************************************************/
940#define SSBS S3_3_C4_C2_6
941
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100942/*******************************************************************************
943 * Armv8.5 - Memory Tagging Extension Registers
944 ******************************************************************************/
945#define TFSRE0_EL1 S3_0_C5_C6_1
946#define TFSR_EL1 S3_0_C5_C6_0
947#define RGSR_EL1 S3_0_C1_C0_5
948#define GCR_EL1 S3_0_C1_C0_6
949
Madhukar Pappireddy90d65322019-10-30 14:24:39 -0500950/*******************************************************************************
951 * Definitions for DynamicIQ Shared Unit registers
952 ******************************************************************************/
953#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
954
955/* CLUSTERPWRDN_EL1 register definitions */
956#define DSU_CLUSTER_PWR_OFF 0
957#define DSU_CLUSTER_PWR_ON 1
958#define DSU_CLUSTER_PWR_MASK U(1)
959
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +0100960#endif /* ARCH_H */