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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +00002 * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
Varun Wadekar423045d2022-05-25 12:45:22 +01003 * Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01004 *
dp-armfa3cf0b2017-05-03 09:38:09 +01005 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01006 */
7
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01008#ifndef ARCH_H
9#define ARCH_H
Achin Gupta4f6ad662013-10-25 09:08:21 +010010
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000011#include <lib/utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010012
13/*******************************************************************************
14 * MIDR bit definitions
15 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -070016#define MIDR_IMPL_MASK U(0xff)
17#define MIDR_IMPL_SHIFT U(0x18)
18#define MIDR_VAR_SHIFT U(20)
19#define MIDR_VAR_BITS U(4)
20#define MIDR_VAR_MASK U(0xf)
21#define MIDR_REV_SHIFT U(0)
22#define MIDR_REV_BITS U(4)
23#define MIDR_REV_MASK U(0xf)
24#define MIDR_PN_MASK U(0xfff)
25#define MIDR_PN_SHIFT U(0x4)
Achin Gupta4f6ad662013-10-25 09:08:21 +010026
27/*******************************************************************************
28 * MPIDR macros
29 ******************************************************************************/
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010030#define MPIDR_MT_MASK (ULL(1) << 24)
Achin Gupta4f6ad662013-10-25 09:08:21 +010031#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
Varun Wadekarc6a11f62017-05-25 18:04:48 -070032#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
33#define MPIDR_AFFINITY_BITS U(8)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010034#define MPIDR_AFFLVL_MASK ULL(0xff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070035#define MPIDR_AFF0_SHIFT U(0)
36#define MPIDR_AFF1_SHIFT U(8)
37#define MPIDR_AFF2_SHIFT U(16)
38#define MPIDR_AFF3_SHIFT U(32)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000039#define MPIDR_AFF_SHIFT(_n) MPIDR_AFF##_n##_SHIFT
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +010040#define MPIDR_AFFINITY_MASK ULL(0xff00ffffff)
Varun Wadekarc6a11f62017-05-25 18:04:48 -070041#define MPIDR_AFFLVL_SHIFT U(3)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000042#define MPIDR_AFFLVL0 ULL(0x0)
43#define MPIDR_AFFLVL1 ULL(0x1)
44#define MPIDR_AFFLVL2 ULL(0x2)
45#define MPIDR_AFFLVL3 ULL(0x3)
46#define MPIDR_AFFLVL(_n) MPIDR_AFFLVL##_n
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000047#define MPIDR_AFFLVL0_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010048 (((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000049#define MPIDR_AFFLVL1_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010050 (((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000051#define MPIDR_AFFLVL2_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010052 (((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
Vikram Kanigiri4e97e542015-02-26 15:25:58 +000053#define MPIDR_AFFLVL3_VAL(mpidr) \
Antonio Nino Diaz34235a32018-07-11 16:45:49 +010054 (((mpidr) >> MPIDR_AFF3_SHIFT) & MPIDR_AFFLVL_MASK)
Soby Mathewe2b2d8f2014-12-04 14:14:12 +000055/*
56 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to
57 * add one while using this macro to define array sizes.
58 * TODO: Support only the first 3 affinity levels for now.
59 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -070060#define MPIDR_MAX_AFFLVL U(2)
Achin Gupta4f6ad662013-10-25 09:08:21 +010061
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000062#define MPID_MASK (MPIDR_MT_MASK | \
63 (MPIDR_AFFLVL_MASK << MPIDR_AFF3_SHIFT) | \
64 (MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT) | \
65 (MPIDR_AFFLVL_MASK << MPIDR_AFF1_SHIFT) | \
66 (MPIDR_AFFLVL_MASK << MPIDR_AFF0_SHIFT))
67
68#define MPIDR_AFF_ID(mpid, n) \
69 (((mpid) >> MPIDR_AFF_SHIFT(n)) & MPIDR_AFFLVL_MASK)
70
71/*
72 * An invalid MPID. This value can be used by functions that return an MPID to
73 * indicate an error.
74 */
75#define INVALID_MPID U(0xFFFFFFFF)
Achin Gupta4f6ad662013-10-25 09:08:21 +010076
77/*******************************************************************************
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010078 * Definitions for CPU system register interface to GICv3
79 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000080#define ICC_IGRPEN1_EL1 S3_0_C12_C12_7
81#define ICC_SGI1R S3_0_C12_C11_5
Florian Lugoud4e25032021-09-08 12:40:24 +020082#define ICC_ASGI1R S3_0_C12_C11_6
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +000083#define ICC_SRE_EL1 S3_0_C12_C12_5
84#define ICC_SRE_EL2 S3_4_C12_C9_5
85#define ICC_SRE_EL3 S3_6_C12_C12_5
86#define ICC_CTLR_EL1 S3_0_C12_C12_4
87#define ICC_CTLR_EL3 S3_6_C12_C12_4
88#define ICC_PMR_EL1 S3_0_C4_C6_0
89#define ICC_RPR_EL1 S3_0_C12_C11_3
90#define ICC_IGRPEN1_EL3 S3_6_c12_c12_7
91#define ICC_IGRPEN0_EL1 S3_0_c12_c12_6
92#define ICC_HPPIR0_EL1 S3_0_c12_c8_2
93#define ICC_HPPIR1_EL1 S3_0_c12_c12_2
94#define ICC_IAR0_EL1 S3_0_c12_c8_0
95#define ICC_IAR1_EL1 S3_0_c12_c12_0
96#define ICC_EOIR0_EL1 S3_0_c12_c8_1
97#define ICC_EOIR1_EL1 S3_0_c12_c12_1
98#define ICC_SGI0R_EL1 S3_0_c12_c11_7
Andrew Thoelke3f78dc32014-06-02 15:44:43 +010099
100/*******************************************************************************
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000101 * Definitions for EL2 system registers for save/restore routine
102 ******************************************************************************/
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000103#define CNTPOFF_EL2 S3_4_C14_C0_6
104#define HAFGRTR_EL2 S3_4_C3_C1_6
105#define HDFGRTR_EL2 S3_4_C3_C1_4
106#define HDFGWTR_EL2 S3_4_C3_C1_5
107#define HFGITR_EL2 S3_4_C1_C1_6
108#define HFGRTR_EL2 S3_4_C1_C1_4
109#define HFGWTR_EL2 S3_4_C1_C1_5
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000110#define ICH_HCR_EL2 S3_4_C12_C11_0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000111#define ICH_VMCR_EL2 S3_4_C12_C11_7
Varun Wadekar423045d2022-05-25 12:45:22 +0100112#define MPAMVPM0_EL2 S3_4_C10_C6_0
113#define MPAMVPM1_EL2 S3_4_C10_C6_1
114#define MPAMVPM2_EL2 S3_4_C10_C6_2
115#define MPAMVPM3_EL2 S3_4_C10_C6_3
116#define MPAMVPM4_EL2 S3_4_C10_C6_4
117#define MPAMVPM5_EL2 S3_4_C10_C6_5
118#define MPAMVPM6_EL2 S3_4_C10_C6_6
119#define MPAMVPM7_EL2 S3_4_C10_C6_7
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000120#define MPAMVPMV_EL2 S3_4_C10_C4_1
Max Shvetsovc9e2c922020-02-17 16:15:47 +0000121#define TRFCR_EL2 S3_4_C1_C2_1
122#define PMSCR_EL2 S3_4_C9_C9_0
123#define TFSR_EL2 S3_4_C5_C6_0
Max Shvetsovbdf502d2020-02-25 13:56:19 +0000124
125/*******************************************************************************
Achin Guptac2b43af2013-10-31 11:27:43 +0000126 * Generic timer memory mapped registers & offsets
127 ******************************************************************************/
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700128#define CNTCR_OFF U(0x000)
Yann Gautier007d7452019-04-17 13:47:07 +0200129#define CNTCV_OFF U(0x008)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700130#define CNTFID_OFF U(0x020)
Achin Guptac2b43af2013-10-31 11:27:43 +0000131
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700132#define CNTCR_EN (U(1) << 0)
133#define CNTCR_HDBG (U(1) << 1)
Sandrine Bailleux3fa98472014-03-31 11:25:18 +0100134#define CNTCR_FCREQ(x) ((x) << 8)
Achin Guptac2b43af2013-10-31 11:27:43 +0000135
136/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100137 * System register bit definitions
138 ******************************************************************************/
139/* CLIDR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700140#define LOUIS_SHIFT U(21)
141#define LOC_SHIFT U(24)
Alexei Fedorova95a5892019-07-29 17:22:53 +0100142#define CTYPE_SHIFT(n) U(3 * (n - 1))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700143#define CLIDR_FIELD_WIDTH U(3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144
145/* CSSELR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700146#define LEVEL_SHIFT U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100147
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100148/* Data cache set/way op type defines */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700149#define DCISW U(0x0)
150#define DCCISW U(0x1)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000151#if ERRATA_A53_827319
152#define DCCSW DCCISW
153#else
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700154#define DCCSW U(0x2)
Ambroise Vincentf5fdfbc2019-02-21 14:16:24 +0000155#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100156
157/* ID_AA64PFR0_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000158#define ID_AA64PFR0_EL0_SHIFT U(0)
159#define ID_AA64PFR0_EL1_SHIFT U(4)
160#define ID_AA64PFR0_EL2_SHIFT U(8)
161#define ID_AA64PFR0_EL3_SHIFT U(12)
162
163#define ID_AA64PFR0_AMU_SHIFT U(44)
164#define ID_AA64PFR0_AMU_MASK ULL(0xf)
165#define ID_AA64PFR0_AMU_NOT_SUPPORTED U(0x0)
166#define ID_AA64PFR0_AMU_V1 ULL(0x1)
167#define ID_AA64PFR0_AMU_V1P1 U(0x2)
168
169#define ID_AA64PFR0_ELX_MASK ULL(0xf)
170
171#define ID_AA64PFR0_GIC_SHIFT U(24)
172#define ID_AA64PFR0_GIC_WIDTH U(4)
173#define ID_AA64PFR0_GIC_MASK ULL(0xf)
174
175#define ID_AA64PFR0_SVE_SHIFT U(32)
176#define ID_AA64PFR0_SVE_MASK ULL(0xf)
177#define ID_AA64PFR0_SVE_SUPPORTED ULL(0x1)
178#define ID_AA64PFR0_SVE_LENGTH U(4)
179
180#define ID_AA64PFR0_SEL2_SHIFT U(36)
181#define ID_AA64PFR0_SEL2_MASK ULL(0xf)
182
183#define ID_AA64PFR0_MPAM_SHIFT U(40)
184#define ID_AA64PFR0_MPAM_MASK ULL(0xf)
185
186#define ID_AA64PFR0_DIT_SHIFT U(48)
187#define ID_AA64PFR0_DIT_MASK ULL(0xf)
188#define ID_AA64PFR0_DIT_LENGTH U(4)
189#define ID_AA64PFR0_DIT_SUPPORTED U(1)
190
191#define ID_AA64PFR0_CSV2_SHIFT U(56)
192#define ID_AA64PFR0_CSV2_MASK ULL(0xf)
193#define ID_AA64PFR0_CSV2_LENGTH U(4)
194#define ID_AA64PFR0_CSV2_2_SUPPORTED ULL(0x2)
195
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500196#define ID_AA64PFR0_FEAT_RME_SHIFT U(52)
197#define ID_AA64PFR0_FEAT_RME_MASK ULL(0xf)
198#define ID_AA64PFR0_FEAT_RME_LENGTH U(4)
199#define ID_AA64PFR0_FEAT_RME_NOT_SUPPORTED U(0)
200#define ID_AA64PFR0_FEAT_RME_V1 U(1)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100201
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000202#define ID_AA64PFR0_RAS_SHIFT U(28)
203#define ID_AA64PFR0_RAS_MASK ULL(0xf)
204#define ID_AA64PFR0_RAS_NOT_SUPPORTED ULL(0x0)
205#define ID_AA64PFR0_RAS_LENGTH U(4)
206
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100207/* Exception level handling */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100208#define EL_IMPL_NONE ULL(0)
209#define EL_IMPL_A64ONLY ULL(1)
210#define EL_IMPL_A64_A32 ULL(2)
Jeenu Viswambharan2a9b8822017-02-21 14:40:44 +0000211
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100212/* ID_AA64DFR0_EL1.TraceVer definitions */
213#define ID_AA64DFR0_TRACEVER_SHIFT U(4)
214#define ID_AA64DFR0_TRACEVER_MASK ULL(0xf)
215#define ID_AA64DFR0_TRACEVER_SUPPORTED ULL(1)
216#define ID_AA64DFR0_TRACEVER_LENGTH U(4)
Manish V Badarkhe8ce33942021-07-18 02:26:27 +0100217#define ID_AA64DFR0_TRACEFILT_SHIFT U(40)
218#define ID_AA64DFR0_TRACEFILT_MASK U(0xf)
219#define ID_AA64DFR0_TRACEFILT_SUPPORTED U(1)
220#define ID_AA64DFR0_TRACEFILT_LENGTH U(4)
Manish V Badarkhef7ee0642021-07-07 16:27:10 +0100221
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100222/* ID_AA64DFR0_EL1.PMS definitions (for ARMv8.2+) */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000223#define ID_AA64DFR0_PMS_SHIFT U(32)
224#define ID_AA64DFR0_PMS_MASK ULL(0xf)
225#define ID_AA64DFR0_SPE_SUPPORTED ULL(0x1)
226#define ID_AA64DFR0_SPE_NOT_SUPPORTED ULL(0x0)
Achin Gupta92712a52015-09-03 14:18:02 +0100227
Manish V Badarkhe20df29c2021-07-02 09:10:56 +0100228/* ID_AA64DFR0_EL1.TraceBuffer definitions */
229#define ID_AA64DFR0_TRACEBUFFER_SHIFT U(44)
230#define ID_AA64DFR0_TRACEBUFFER_MASK ULL(0xf)
231#define ID_AA64DFR0_TRACEBUFFER_SUPPORTED ULL(1)
232
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000233/* ID_AA64DFR0_EL1.MTPMU definitions (for ARMv8.6+) */
234#define ID_AA64DFR0_MTPMU_SHIFT U(48)
235#define ID_AA64DFR0_MTPMU_MASK ULL(0xf)
236#define ID_AA64DFR0_MTPMU_SUPPORTED ULL(1)
237
johpow0181865962022-01-28 17:06:20 -0600238/* ID_AA64DFR0_EL1.BRBE definitions */
239#define ID_AA64DFR0_BRBE_SHIFT U(52)
240#define ID_AA64DFR0_BRBE_MASK ULL(0xf)
241#define ID_AA64DFR0_BRBE_SUPPORTED ULL(1)
242
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000243/* ID_AA64ISAR0_EL1 definitions */
johpow019baade32021-07-08 14:14:00 -0500244#define ID_AA64ISAR0_RNDR_SHIFT U(60)
245#define ID_AA64ISAR0_RNDR_MASK ULL(0xf)
Tomas Pilar6fd816e2020-10-28 15:34:12 +0000246
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000247/* ID_AA64ISAR1_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000248#define ID_AA64ISAR1_EL1 S3_0_C0_C6_1
249
250#define ID_AA64ISAR1_GPI_SHIFT U(28)
251#define ID_AA64ISAR1_GPI_MASK ULL(0xf)
252#define ID_AA64ISAR1_GPA_SHIFT U(24)
253#define ID_AA64ISAR1_GPA_MASK ULL(0xf)
254
255#define ID_AA64ISAR1_API_SHIFT U(8)
256#define ID_AA64ISAR1_API_MASK ULL(0xf)
257#define ID_AA64ISAR1_APA_SHIFT U(4)
258#define ID_AA64ISAR1_APA_MASK ULL(0xf)
259
260#define ID_AA64ISAR1_SB_SHIFT U(36)
261#define ID_AA64ISAR1_SB_MASK ULL(0xf)
262#define ID_AA64ISAR1_SB_SUPPORTED ULL(0x1)
263#define ID_AA64ISAR1_SB_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000264
Juan Pablo Condee089a172022-06-29 17:44:43 -0400265/* ID_AA64ISAR2_EL1 definitions */
266#define ID_AA64ISAR2_EL1 S3_0_C0_C6_2
267
268#define ID_AA64ISAR2_GPA3_SHIFT U(8)
269#define ID_AA64ISAR2_GPA3_MASK ULL(0xf)
270
271#define ID_AA64ISAR2_APA3_SHIFT U(12)
272#define ID_AA64ISAR2_APA3_MASK ULL(0xf)
273
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000274/* ID_AA64MMFR0_EL1 definitions */
275#define ID_AA64MMFR0_EL1_PARANGE_SHIFT U(0)
276#define ID_AA64MMFR0_EL1_PARANGE_MASK ULL(0xf)
277
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700278#define PARANGE_0000 U(32)
279#define PARANGE_0001 U(36)
280#define PARANGE_0010 U(40)
281#define PARANGE_0011 U(42)
282#define PARANGE_0100 U(44)
283#define PARANGE_0101 U(48)
Antonio Nino Diazb9ef6642017-11-17 09:52:53 +0000284#define PARANGE_0110 U(52)
Antonio Nino Diazd1beee22016-12-13 15:28:54 +0000285
Jimmy Brisson83573892020-04-16 10:48:02 -0500286#define ID_AA64MMFR0_EL1_ECV_SHIFT U(60)
287#define ID_AA64MMFR0_EL1_ECV_MASK ULL(0xf)
288#define ID_AA64MMFR0_EL1_ECV_NOT_SUPPORTED ULL(0x0)
289#define ID_AA64MMFR0_EL1_ECV_SUPPORTED ULL(0x1)
290#define ID_AA64MMFR0_EL1_ECV_SELF_SYNCH ULL(0x2)
291
Jimmy Brissonecc3c672020-04-16 10:47:56 -0500292#define ID_AA64MMFR0_EL1_FGT_SHIFT U(56)
293#define ID_AA64MMFR0_EL1_FGT_MASK ULL(0xf)
294#define ID_AA64MMFR0_EL1_FGT_SUPPORTED ULL(0x1)
295#define ID_AA64MMFR0_EL1_FGT_NOT_SUPPORTED ULL(0x0)
296
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100297#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT U(28)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100298#define ID_AA64MMFR0_EL1_TGRAN4_MASK ULL(0xf)
299#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED ULL(0x0)
300#define ID_AA64MMFR0_EL1_TGRAN4_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100301
302#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT U(24)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100303#define ID_AA64MMFR0_EL1_TGRAN64_MASK ULL(0xf)
304#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED ULL(0x0)
305#define ID_AA64MMFR0_EL1_TGRAN64_NOT_SUPPORTED ULL(0xf)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100306
307#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT U(20)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100308#define ID_AA64MMFR0_EL1_TGRAN16_MASK ULL(0xf)
309#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED ULL(0x1)
310#define ID_AA64MMFR0_EL1_TGRAN16_NOT_SUPPORTED ULL(0x0)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100311
johpow013e24c162020-04-22 14:05:13 -0500312/* ID_AA64MMFR1_EL1 definitions */
313#define ID_AA64MMFR1_EL1_TWED_SHIFT U(32)
314#define ID_AA64MMFR1_EL1_TWED_MASK ULL(0xf)
315#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
316#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
317
Alexei Fedorovc082f032020-11-25 14:07:05 +0000318#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
319#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
320#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
321#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
322#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
323#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
324
Daniel Boulby44b43332020-11-25 16:36:46 +0000325#define ID_AA64MMFR1_EL1_VHE_SHIFT U(8)
326#define ID_AA64MMFR1_EL1_VHE_MASK ULL(0xf)
327
johpow019baade32021-07-08 14:14:00 -0500328#define ID_AA64MMFR1_EL1_HCX_SHIFT U(40)
329#define ID_AA64MMFR1_EL1_HCX_MASK ULL(0xf)
330#define ID_AA64MMFR1_EL1_HCX_SUPPORTED ULL(0x1)
331#define ID_AA64MMFR1_EL1_HCX_NOT_SUPPORTED ULL(0x0)
johpow01f91e59f2021-08-04 19:38:18 -0500332
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000333/* ID_AA64MMFR2_EL1 definitions */
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000334#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
Sathees Balya74155972019-01-25 11:36:01 +0000335
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000336#define ID_AA64MMFR2_EL1_ST_SHIFT U(28)
337#define ID_AA64MMFR2_EL1_ST_MASK ULL(0xf)
Sathees Balya74155972019-01-25 11:36:01 +0000338
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000339#define ID_AA64MMFR2_EL1_CCIDX_SHIFT U(20)
340#define ID_AA64MMFR2_EL1_CCIDX_MASK ULL(0xf)
341#define ID_AA64MMFR2_EL1_CCIDX_LENGTH U(4)
342
343#define ID_AA64MMFR2_EL1_CNP_SHIFT U(0)
344#define ID_AA64MMFR2_EL1_CNP_MASK ULL(0xf)
johpow0174b7e442021-12-01 13:18:30 -0600345
Jayanth Dodderi Chidanand9461a892022-01-17 18:57:17 +0000346#define ID_AA64MMFR2_EL1_NV_SHIFT U(24)
347#define ID_AA64MMFR2_EL1_NV_MASK ULL(0xf)
348#define ID_AA64MMFR2_EL1_NV_NOT_SUPPORTED ULL(0x0)
349#define ID_AA64MMFR2_EL1_NV_SUPPORTED ULL(0x1)
350#define ID_AA64MMFR2_EL1_NV2_SUPPORTED ULL(0x2)
Antonio Nino Diazc326c342019-01-11 11:20:10 +0000351
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000352/* ID_AA64PFR1_EL1 definitions */
353#define ID_AA64PFR1_EL1_SSBS_SHIFT U(4)
354#define ID_AA64PFR1_EL1_SSBS_MASK ULL(0xf)
355
356#define SSBS_UNAVAILABLE ULL(0) /* No architectural SSBS support */
357
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100358#define ID_AA64PFR1_EL1_BT_SHIFT U(0)
359#define ID_AA64PFR1_EL1_BT_MASK ULL(0xf)
360
361#define BTI_IMPLEMENTED ULL(1) /* The BTI mechanism is implemented */
362
Soby Mathew830f0ad2019-07-12 09:23:38 +0100363#define ID_AA64PFR1_EL1_MTE_SHIFT U(8)
364#define ID_AA64PFR1_EL1_MTE_MASK ULL(0xf)
365
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400366#define ID_AA64PFR1_EL1_RNDR_TRAP_SHIFT U(28)
367#define ID_AA64PFR1_EL1_RNDR_TRAP_MASK U(0xf)
368
369#define ID_AA64PFR1_EL1_RNG_TRAP_SUPPORTED ULL(0x1)
370#define ID_AA64PFR1_EL1_RNG_TRAP_NOT_SUPPORTED ULL(0x0)
371
Alexei Fedorovaf54f6e2020-12-01 13:22:25 +0000372/* Memory Tagging Extension is not implemented */
373#define MTE_UNIMPLEMENTED U(0)
374/* FEAT_MTE: MTE instructions accessible at EL0 are implemented */
375#define MTE_IMPLEMENTED_EL0 U(1)
376/* FEAT_MTE2: Full MTE is implemented */
377#define MTE_IMPLEMENTED_ELX U(2)
378/*
379 * FEAT_MTE3: MTE is implemented with support for
380 * asymmetric Tag Check Fault handling
381 */
382#define MTE_IMPLEMENTED_ASY U(3)
Soby Mathew830f0ad2019-07-12 09:23:38 +0100383
Alexei Fedorov19933552020-05-26 13:16:41 +0100384#define ID_AA64PFR1_MPAM_FRAC_SHIFT ULL(16)
385#define ID_AA64PFR1_MPAM_FRAC_MASK ULL(0xf)
386
johpow019baade32021-07-08 14:14:00 -0500387#define ID_AA64PFR1_EL1_SME_SHIFT U(24)
388#define ID_AA64PFR1_EL1_SME_MASK ULL(0xf)
389
Achin Gupta4f6ad662013-10-25 09:08:21 +0100390/* ID_PFR1_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700391#define ID_PFR1_VIRTEXT_SHIFT U(12)
392#define ID_PFR1_VIRTEXT_MASK U(0xf)
Antonio Nino Diaz34235a32018-07-11 16:45:49 +0100393#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
Achin Gupta4f6ad662013-10-25 09:08:21 +0100394 & ID_PFR1_VIRTEXT_MASK)
395
396/* SCTLR definitions */
David Cunadofee86532017-04-13 22:38:29 +0100397#define SCTLR_EL2_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700398 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
399 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100400
John Powella5c66362020-03-20 14:21:05 -0500401#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
402 (UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
Alexei Fedorovc082f032020-11-25 14:07:05 +0000403
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200404#define SCTLR_AARCH32_EL1_RES1 \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700405 ((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
406 (U(1) << 4) | (U(1) << 3))
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200407
David Cunadofee86532017-04-13 22:38:29 +0100408#define SCTLR_EL3_RES1 ((U(1) << 29) | (U(1) << 28) | (U(1) << 23) | \
409 (U(1) << 22) | (U(1) << 18) | (U(1) << 16) | \
410 (U(1) << 11) | (U(1) << 5) | (U(1) << 4))
411
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000412#define SCTLR_M_BIT (ULL(1) << 0)
413#define SCTLR_A_BIT (ULL(1) << 1)
414#define SCTLR_C_BIT (ULL(1) << 2)
415#define SCTLR_SA_BIT (ULL(1) << 3)
416#define SCTLR_SA0_BIT (ULL(1) << 4)
417#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000418#define SCTLR_nAA_BIT (ULL(1) << 6)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000419#define SCTLR_ITD_BIT (ULL(1) << 7)
420#define SCTLR_SED_BIT (ULL(1) << 8)
421#define SCTLR_UMA_BIT (ULL(1) << 9)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000422#define SCTLR_EnRCTX_BIT (ULL(1) << 10)
423#define SCTLR_EOS_BIT (ULL(1) << 11)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000424#define SCTLR_I_BIT (ULL(1) << 12)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100425#define SCTLR_EnDB_BIT (ULL(1) << 13)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000426#define SCTLR_DZE_BIT (ULL(1) << 14)
427#define SCTLR_UCT_BIT (ULL(1) << 15)
428#define SCTLR_NTWI_BIT (ULL(1) << 16)
429#define SCTLR_NTWE_BIT (ULL(1) << 18)
430#define SCTLR_WXN_BIT (ULL(1) << 19)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000431#define SCTLR_TSCXT_BIT (ULL(1) << 20)
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000432#define SCTLR_IESB_BIT (ULL(1) << 21)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000433#define SCTLR_EIS_BIT (ULL(1) << 22)
434#define SCTLR_SPAN_BIT (ULL(1) << 23)
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +0000435#define SCTLR_E0E_BIT (ULL(1) << 24)
436#define SCTLR_EE_BIT (ULL(1) << 25)
437#define SCTLR_UCI_BIT (ULL(1) << 26)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100438#define SCTLR_EnDA_BIT (ULL(1) << 27)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000439#define SCTLR_nTLSMD_BIT (ULL(1) << 28)
440#define SCTLR_LSMAOE_BIT (ULL(1) << 29)
Alexei Fedorovc31ab382019-07-10 10:49:12 +0100441#define SCTLR_EnIB_BIT (ULL(1) << 30)
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000442#define SCTLR_EnIA_BIT (ULL(1) << 31)
Alexei Fedorov90f2e882019-05-24 12:17:09 +0100443#define SCTLR_BT0_BIT (ULL(1) << 35)
444#define SCTLR_BT1_BIT (ULL(1) << 36)
445#define SCTLR_BT_BIT (ULL(1) << 36)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000446#define SCTLR_ITFSB_BIT (ULL(1) << 37)
447#define SCTLR_TCF0_SHIFT U(38)
448#define SCTLR_TCF0_MASK ULL(3)
johpow019baade32021-07-08 14:14:00 -0500449#define SCTLR_ENTP2_BIT (ULL(1) << 60)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000450
451/* Tag Check Faults in EL0 have no effect on the PE */
452#define SCTLR_TCF0_NO_EFFECT U(0)
453/* Tag Check Faults in EL0 cause a synchronous exception */
454#define SCTLR_TCF0_SYNC U(1)
455/* Tag Check Faults in EL0 are asynchronously accumulated */
456#define SCTLR_TCF0_ASYNC U(2)
457/*
458 * Tag Check Faults in EL0 cause a synchronous exception on reads,
459 * and are asynchronously accumulated on writes
460 */
461#define SCTLR_TCF0_SYNCR_ASYNCW U(3)
462
463#define SCTLR_TCF_SHIFT U(40)
464#define SCTLR_TCF_MASK ULL(3)
465
466/* Tag Check Faults in EL1 have no effect on the PE */
467#define SCTLR_TCF_NO_EFFECT U(0)
468/* Tag Check Faults in EL1 cause a synchronous exception */
469#define SCTLR_TCF_SYNC U(1)
470/* Tag Check Faults in EL1 are asynchronously accumulated */
471#define SCTLR_TCF_ASYNC U(2)
472/*
473 * Tag Check Faults in EL1 cause a synchronous exception on reads,
474 * and are asynchronously accumulated on writes
475 */
476#define SCTLR_TCF_SYNCR_ASYNCW U(3)
477
478#define SCTLR_ATA0_BIT (ULL(1) << 42)
479#define SCTLR_ATA_BIT (ULL(1) << 43)
Daniel Boulby44b43332020-11-25 16:36:46 +0000480#define SCTLR_DSSBS_SHIFT U(44)
481#define SCTLR_DSSBS_BIT (ULL(1) << SCTLR_DSSBS_SHIFT)
Alexei Fedorovc082f032020-11-25 14:07:05 +0000482#define SCTLR_TWEDEn_BIT (ULL(1) << 45)
483#define SCTLR_TWEDEL_SHIFT U(46)
484#define SCTLR_TWEDEL_MASK ULL(0xf)
485#define SCTLR_EnASR_BIT (ULL(1) << 54)
486#define SCTLR_EnAS0_BIT (ULL(1) << 55)
487#define SCTLR_EnALS_BIT (ULL(1) << 56)
488#define SCTLR_EPAN_BIT (ULL(1) << 57)
David Cunadofee86532017-04-13 22:38:29 +0100489#define SCTLR_RESET_VAL SCTLR_EL3_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100490
Alexei Fedorovc082f032020-11-25 14:07:05 +0000491/* CPACR_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700492#define CPACR_EL1_FPEN(x) ((x) << 20)
Jimmy Brissoned202072020-08-04 16:18:52 -0500493#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
494#define CPACR_EL1_FP_TRAP_ALL UL(0x2)
495#define CPACR_EL1_FP_TRAP_NONE UL(0x3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100496
497/* SCR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700498#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
Zelalem Aweke79e3d292021-07-08 16:51:14 -0500499#define SCR_NSE_SHIFT U(62)
500#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
501#define SCR_GPF_BIT (UL(1) << 48)
johpow013e24c162020-04-22 14:05:13 -0500502#define SCR_TWEDEL_SHIFT U(30)
503#define SCR_TWEDEL_MASK ULL(0xf)
Juan Pablo Conde42305f22022-07-12 16:40:29 -0400504#define SCR_TRNDR_BIT (UL(1) << 40)
johpow019baade32021-07-08 14:14:00 -0500505#define SCR_HXEn_BIT (UL(1) << 38)
506#define SCR_ENTP2_SHIFT U(41)
507#define SCR_ENTP2_BIT (UL(1) << SCR_ENTP2_SHIFT)
John Powellcc799272022-03-29 00:25:59 -0500508#define SCR_AMVOFFEN_SHIFT U(35)
509#define SCR_AMVOFFEN_BIT (UL(1) << SCR_AMVOFFEN_SHIFT)
johpow013e24c162020-04-22 14:05:13 -0500510#define SCR_TWEDEn_BIT (UL(1) << 29)
johpow01fa59c6f2020-10-02 13:41:11 -0500511#define SCR_ECVEN_BIT (UL(1) << 28)
512#define SCR_FGTEN_BIT (UL(1) << 27)
Jimmy Brissoned202072020-08-04 16:18:52 -0500513#define SCR_ATA_BIT (UL(1) << 26)
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500514#define SCR_EnSCXT_BIT (UL(1) << 25)
Jimmy Brissoned202072020-08-04 16:18:52 -0500515#define SCR_FIEN_BIT (UL(1) << 21)
516#define SCR_EEL2_BIT (UL(1) << 18)
517#define SCR_API_BIT (UL(1) << 17)
518#define SCR_APK_BIT (UL(1) << 16)
519#define SCR_TERR_BIT (UL(1) << 15)
520#define SCR_TWE_BIT (UL(1) << 13)
521#define SCR_TWI_BIT (UL(1) << 12)
522#define SCR_ST_BIT (UL(1) << 11)
523#define SCR_RW_BIT (UL(1) << 10)
524#define SCR_SIF_BIT (UL(1) << 9)
525#define SCR_HCE_BIT (UL(1) << 8)
526#define SCR_SMD_BIT (UL(1) << 7)
527#define SCR_EA_BIT (UL(1) << 3)
528#define SCR_FIQ_BIT (UL(1) << 2)
529#define SCR_IRQ_BIT (UL(1) << 1)
530#define SCR_NS_BIT (UL(1) << 0)
johpow019baade32021-07-08 14:14:00 -0500531#define SCR_VALID_BIT_MASK U(0x24000002F8F)
David Cunadofee86532017-04-13 22:38:29 +0100532#define SCR_RESET_VAL SCR_RES1_BITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100533
David Cunadofee86532017-04-13 22:38:29 +0100534/* MDCR_EL3 definitions */
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100535#define MDCR_EnPMSN_BIT (ULL(1) << 36)
536#define MDCR_MPMX_BIT (ULL(1) << 35)
537#define MDCR_MCCD_BIT (ULL(1) << 34)
johpow0181865962022-01-28 17:06:20 -0600538#define MDCR_SBRBE_SHIFT U(32)
539#define MDCR_SBRBE_MASK ULL(0x3)
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100540#define MDCR_NSTB(x) ((x) << 24)
541#define MDCR_NSTB_EL1 ULL(0x3)
542#define MDCR_NSTBE (ULL(1) << 26)
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000543#define MDCR_MTPME_BIT (ULL(1) << 28)
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100544#define MDCR_TDCC_BIT (ULL(1) << 27)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100545#define MDCR_SCCD_BIT (ULL(1) << 23)
Alexei Fedorov307f34b2021-05-14 11:21:56 +0100546#define MDCR_EPMAD_BIT (ULL(1) << 21)
547#define MDCR_EDAD_BIT (ULL(1) << 20)
548#define MDCR_TTRF_BIT (ULL(1) << 19)
549#define MDCR_STE_BIT (ULL(1) << 18)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100550#define MDCR_SPME_BIT (ULL(1) << 17)
551#define MDCR_SDD_BIT (ULL(1) << 16)
dp-arm595d0d52017-02-08 11:51:50 +0000552#define MDCR_SPD32(x) ((x) << 14)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000553#define MDCR_SPD32_LEGACY ULL(0x0)
554#define MDCR_SPD32_DISABLE ULL(0x2)
555#define MDCR_SPD32_ENABLE ULL(0x3)
dp-armee3457b2017-05-23 09:32:49 +0100556#define MDCR_NSPB(x) ((x) << 12)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000557#define MDCR_NSPB_EL1 ULL(0x3)
558#define MDCR_TDOSA_BIT (ULL(1) << 10)
559#define MDCR_TDA_BIT (ULL(1) << 9)
560#define MDCR_TPM_BIT (ULL(1) << 6)
Antonio Nino Diaz3fbd3f52019-02-18 16:55:43 +0000561#define MDCR_EL3_RESET_VAL ULL(0x0)
dp-arm595d0d52017-02-08 11:51:50 +0000562
David Cunadofee86532017-04-13 22:38:29 +0100563/* MDCR_EL2 definitions */
Javier Almansa Sobrinof3a4c542020-11-23 18:38:15 +0000564#define MDCR_EL2_MTPME (U(1) << 28)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100565#define MDCR_EL2_HLP (U(1) << 26)
Manish V Badarkhee1cccb42021-06-23 20:02:39 +0100566#define MDCR_EL2_E2TB(x) ((x) << 24)
567#define MDCR_EL2_E2TB_EL1 U(0x3)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100568#define MDCR_EL2_HCCD (U(1) << 23)
569#define MDCR_EL2_TTRF (U(1) << 19)
570#define MDCR_EL2_HPMD (U(1) << 17)
dp-armee3457b2017-05-23 09:32:49 +0100571#define MDCR_EL2_TPMS (U(1) << 14)
572#define MDCR_EL2_E2PB(x) ((x) << 12)
573#define MDCR_EL2_E2PB_EL1 U(0x3)
David Cunadofee86532017-04-13 22:38:29 +0100574#define MDCR_EL2_TDRA_BIT (U(1) << 11)
575#define MDCR_EL2_TDOSA_BIT (U(1) << 10)
576#define MDCR_EL2_TDA_BIT (U(1) << 9)
577#define MDCR_EL2_TDE_BIT (U(1) << 8)
578#define MDCR_EL2_HPME_BIT (U(1) << 7)
579#define MDCR_EL2_TPM_BIT (U(1) << 6)
580#define MDCR_EL2_TPMCR_BIT (U(1) << 5)
581#define MDCR_EL2_RESET_VAL U(0x0)
582
583/* HSTR_EL2 definitions */
584#define HSTR_EL2_RESET_VAL U(0x0)
585#define HSTR_EL2_T_MASK U(0xff)
586
587/* CNTHP_CTL_EL2 definitions */
588#define CNTHP_CTL_ENABLE_BIT (U(1) << 0)
589#define CNTHP_CTL_RESET_VAL U(0x0)
590
591/* VTTBR_EL2 definitions */
592#define VTTBR_RESET_VAL ULL(0x0)
593#define VTTBR_VMID_MASK ULL(0xff)
594#define VTTBR_VMID_SHIFT U(48)
595#define VTTBR_BADDR_MASK ULL(0xffffffffffff)
596#define VTTBR_BADDR_SHIFT U(0)
dp-arm595d0d52017-02-08 11:51:50 +0000597
Achin Gupta4f6ad662013-10-25 09:08:21 +0100598/* HCR definitions */
Gary Morrison3d7f6542021-01-27 13:08:47 -0600599#define HCR_RESET_VAL ULL(0x0)
Chris Kaya5fde282021-05-26 11:58:23 +0100600#define HCR_AMVOFFEN_SHIFT U(51)
601#define HCR_AMVOFFEN_BIT (ULL(1) << HCR_AMVOFFEN_SHIFT)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600602#define HCR_TEA_BIT (ULL(1) << 47)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100603#define HCR_API_BIT (ULL(1) << 41)
604#define HCR_APK_BIT (ULL(1) << 40)
Manish V Badarkhe2801ed42020-04-28 04:53:32 +0100605#define HCR_E2H_BIT (ULL(1) << 34)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600606#define HCR_HCD_BIT (ULL(1) << 29)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000607#define HCR_TGE_BIT (ULL(1) << 27)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700608#define HCR_RW_SHIFT U(31)
609#define HCR_RW_BIT (ULL(1) << HCR_RW_SHIFT)
Gary Morrison3d7f6542021-01-27 13:08:47 -0600610#define HCR_TWE_BIT (ULL(1) << 14)
611#define HCR_TWI_BIT (ULL(1) << 13)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100612#define HCR_AMO_BIT (ULL(1) << 5)
613#define HCR_IMO_BIT (ULL(1) << 4)
614#define HCR_FMO_BIT (ULL(1) << 3)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100615
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100616/* ISR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700617#define ISR_A_SHIFT U(8)
618#define ISR_I_SHIFT U(7)
619#define ISR_F_SHIFT U(6)
Gerald Lejeune851dc7e2016-03-22 11:11:46 +0100620
Achin Gupta4f6ad662013-10-25 09:08:21 +0100621/* CNTHCTL_EL2 definitions */
David Cunadofee86532017-04-13 22:38:29 +0100622#define CNTHCTL_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700623#define EVNTEN_BIT (U(1) << 2)
624#define EL1PCEN_BIT (U(1) << 1)
625#define EL1PCTEN_BIT (U(1) << 0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100626
627/* CNTKCTL_EL1 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700628#define EL0PTEN_BIT (U(1) << 9)
629#define EL0VTEN_BIT (U(1) << 8)
630#define EL0PCTEN_BIT (U(1) << 0)
631#define EL0VCTEN_BIT (U(1) << 1)
632#define EVNTEN_BIT (U(1) << 2)
633#define EVNTDIR_BIT (U(1) << 3)
634#define EVNTI_SHIFT U(4)
635#define EVNTI_MASK U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100636
637/* CPTR_EL3 definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700638#define TCPAC_BIT (U(1) << 31)
Chris Kaya5fde282021-05-26 11:58:23 +0100639#define TAM_SHIFT U(30)
640#define TAM_BIT (U(1) << TAM_SHIFT)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700641#define TTA_BIT (U(1) << 20)
johpow019baade32021-07-08 14:14:00 -0500642#define ESM_BIT (U(1) << 12)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700643#define TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100644#define CPTR_EZ_BIT (U(1) << 8)
johpow019baade32021-07-08 14:14:00 -0500645#define CPTR_EL3_RESET_VAL ((TCPAC_BIT | TAM_BIT | TTA_BIT | TFP_BIT) & \
646 ~(CPTR_EZ_BIT | ESM_BIT))
David Cunadofee86532017-04-13 22:38:29 +0100647
648/* CPTR_EL2 definitions */
649#define CPTR_EL2_RES1 ((U(1) << 13) | (U(1) << 12) | (U(0x3ff)))
650#define CPTR_EL2_TCPAC_BIT (U(1) << 31)
Chris Kaya5fde282021-05-26 11:58:23 +0100651#define CPTR_EL2_TAM_SHIFT U(30)
652#define CPTR_EL2_TAM_BIT (U(1) << CPTR_EL2_TAM_SHIFT)
johpow019baade32021-07-08 14:14:00 -0500653#define CPTR_EL2_SMEN_MASK ULL(0x3)
654#define CPTR_EL2_SMEN_SHIFT U(24)
David Cunadofee86532017-04-13 22:38:29 +0100655#define CPTR_EL2_TTA_BIT (U(1) << 20)
johpow019baade32021-07-08 14:14:00 -0500656#define CPTR_EL2_TSM_BIT (U(1) << 12)
David Cunadofee86532017-04-13 22:38:29 +0100657#define CPTR_EL2_TFP_BIT (U(1) << 10)
David Cunadoce88eee2017-10-20 11:30:57 +0100658#define CPTR_EL2_TZ_BIT (U(1) << 8)
David Cunadofee86532017-04-13 22:38:29 +0100659#define CPTR_EL2_RESET_VAL CPTR_EL2_RES1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100660
Manish Pandey5693afe2021-10-06 17:28:09 +0100661/* VTCR_EL2 definitions */
johpow019baade32021-07-08 14:14:00 -0500662#define VTCR_RESET_VAL U(0x0)
663#define VTCR_EL2_MSA (U(1) << 31)
Manish Pandey5693afe2021-10-06 17:28:09 +0100664
Achin Gupta4f6ad662013-10-25 09:08:21 +0100665/* CPSR/SPSR definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700666#define DAIF_FIQ_BIT (U(1) << 0)
667#define DAIF_IRQ_BIT (U(1) << 1)
668#define DAIF_ABT_BIT (U(1) << 2)
669#define DAIF_DBG_BIT (U(1) << 3)
670#define SPSR_DAIF_SHIFT U(6)
671#define SPSR_DAIF_MASK U(0xf)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100672
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700673#define SPSR_AIF_SHIFT U(6)
674#define SPSR_AIF_MASK U(0x7)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100675
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700676#define SPSR_E_SHIFT U(9)
677#define SPSR_E_MASK U(0x1)
678#define SPSR_E_LITTLE U(0x0)
679#define SPSR_E_BIG U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100680
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700681#define SPSR_T_SHIFT U(5)
682#define SPSR_T_MASK U(0x1)
683#define SPSR_T_ARM U(0x0)
684#define SPSR_T_THUMB U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100685
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000686#define SPSR_M_SHIFT U(4)
687#define SPSR_M_MASK U(0x1)
688#define SPSR_M_AARCH64 U(0x0)
689#define SPSR_M_AARCH32 U(0x1)
Zelalem Aweke13dc8f12021-07-09 14:20:03 -0500690#define SPSR_M_EL2H U(0x9)
Dimitris Papastamosc52ebdc2017-12-18 13:46:21 +0000691
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000692#define SPSR_EL_SHIFT U(2)
693#define SPSR_EL_WIDTH U(2)
694
Daniel Boulby44b43332020-11-25 16:36:46 +0000695#define SPSR_SSBS_SHIFT_AARCH64 U(12)
696#define SPSR_SSBS_BIT_AARCH64 (ULL(1) << SPSR_SSBS_SHIFT_AARCH64)
697#define SPSR_SSBS_SHIFT_AARCH32 U(23)
698#define SPSR_SSBS_BIT_AARCH32 (ULL(1) << SPSR_SSBS_SHIFT_AARCH32)
699
700#define SPSR_PAN_BIT BIT_64(22)
701
702#define SPSR_DIT_BIT BIT(24)
703
704#define SPSR_TCO_BIT_AARCH64 BIT_64(25)
John Tsichritzis55534172019-07-23 11:12:41 +0100705
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100706#define DISABLE_ALL_EXCEPTIONS \
707 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT)
708
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000709#define DISABLE_INTERRUPTS (DAIF_FIQ_BIT | DAIF_IRQ_BIT)
710
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000711/*
712 * RMR_EL3 definitions
713 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700714#define RMR_EL3_RR_BIT (U(1) << 1)
715#define RMR_EL3_AA64_BIT (U(1) << 0)
Yatharth Kocharede39cb2016-11-14 12:01:04 +0000716
717/*
718 * HI-VECTOR address for AArch32 state
719 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000720#define HI_VECTOR_BASE U(0xFFFF0000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100721
722/*
723 * TCR defintions
724 */
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000725#define TCR_EL3_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100726#define TCR_EL2_RES1 ((ULL(1) << 31) | (ULL(1) << 23))
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700727#define TCR_EL1_IPS_SHIFT U(32)
Antonio Nino Diaz128de8d2018-08-07 19:59:49 +0100728#define TCR_EL2_PS_SHIFT U(16)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700729#define TCR_EL3_PS_SHIFT U(16)
Lin Ma741a3822014-06-27 16:56:30 -0700730
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100731#define TCR_TxSZ_MIN ULL(16)
732#define TCR_TxSZ_MAX ULL(39)
Sathees Balya74155972019-01-25 11:36:01 +0000733#define TCR_TxSZ_MAX_TTST ULL(48)
Antonio Nino Diazd48ae612016-08-02 09:21:41 +0100734
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000735#define TCR_T0SZ_SHIFT U(0)
736#define TCR_T1SZ_SHIFT U(16)
737
Lin Ma741a3822014-06-27 16:56:30 -0700738/* (internal) physical address size bits in EL3/EL1 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100739#define TCR_PS_BITS_4GB ULL(0x0)
740#define TCR_PS_BITS_64GB ULL(0x1)
741#define TCR_PS_BITS_1TB ULL(0x2)
742#define TCR_PS_BITS_4TB ULL(0x3)
743#define TCR_PS_BITS_16TB ULL(0x4)
744#define TCR_PS_BITS_256TB ULL(0x5)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100745
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700746#define ADDR_MASK_48_TO_63 ULL(0xFFFF000000000000)
747#define ADDR_MASK_44_TO_47 ULL(0x0000F00000000000)
748#define ADDR_MASK_42_TO_43 ULL(0x00000C0000000000)
749#define ADDR_MASK_40_TO_41 ULL(0x0000030000000000)
750#define ADDR_MASK_36_TO_39 ULL(0x000000F000000000)
751#define ADDR_MASK_32_TO_35 ULL(0x0000000F00000000)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100752
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100753#define TCR_RGN_INNER_NC (ULL(0x0) << 8)
754#define TCR_RGN_INNER_WBA (ULL(0x1) << 8)
755#define TCR_RGN_INNER_WT (ULL(0x2) << 8)
756#define TCR_RGN_INNER_WBNA (ULL(0x3) << 8)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100757
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100758#define TCR_RGN_OUTER_NC (ULL(0x0) << 10)
759#define TCR_RGN_OUTER_WBA (ULL(0x1) << 10)
760#define TCR_RGN_OUTER_WT (ULL(0x2) << 10)
761#define TCR_RGN_OUTER_WBNA (ULL(0x3) << 10)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100762
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100763#define TCR_SH_NON_SHAREABLE (ULL(0x0) << 12)
764#define TCR_SH_OUTER_SHAREABLE (ULL(0x2) << 12)
765#define TCR_SH_INNER_SHAREABLE (ULL(0x3) << 12)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100766
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000767#define TCR_RGN1_INNER_NC (ULL(0x0) << 24)
768#define TCR_RGN1_INNER_WBA (ULL(0x1) << 24)
769#define TCR_RGN1_INNER_WT (ULL(0x2) << 24)
770#define TCR_RGN1_INNER_WBNA (ULL(0x3) << 24)
771
772#define TCR_RGN1_OUTER_NC (ULL(0x0) << 26)
773#define TCR_RGN1_OUTER_WBA (ULL(0x1) << 26)
774#define TCR_RGN1_OUTER_WT (ULL(0x2) << 26)
775#define TCR_RGN1_OUTER_WBNA (ULL(0x3) << 26)
776
777#define TCR_SH1_NON_SHAREABLE (ULL(0x0) << 28)
778#define TCR_SH1_OUTER_SHAREABLE (ULL(0x2) << 28)
779#define TCR_SH1_INNER_SHAREABLE (ULL(0x3) << 28)
780
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100781#define TCR_TG0_SHIFT U(14)
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100782#define TCR_TG0_MASK ULL(3)
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100783#define TCR_TG0_4K (ULL(0) << TCR_TG0_SHIFT)
784#define TCR_TG0_64K (ULL(1) << TCR_TG0_SHIFT)
785#define TCR_TG0_16K (ULL(2) << TCR_TG0_SHIFT)
786
Antonio Nino Diaz37f97a52019-03-27 11:10:31 +0000787#define TCR_TG1_SHIFT U(30)
788#define TCR_TG1_MASK ULL(3)
789#define TCR_TG1_16K (ULL(1) << TCR_TG1_SHIFT)
790#define TCR_TG1_4K (ULL(2) << TCR_TG1_SHIFT)
791#define TCR_TG1_64K (ULL(3) << TCR_TG1_SHIFT)
792
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100793#define TCR_EPD0_BIT (ULL(1) << 7)
794#define TCR_EPD1_BIT (ULL(1) << 23)
Antonio Nino Diazc8274a82017-09-15 10:30:34 +0100795
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700796#define MODE_SP_SHIFT U(0x0)
797#define MODE_SP_MASK U(0x1)
798#define MODE_SP_EL0 U(0x0)
799#define MODE_SP_ELX U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100800
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700801#define MODE_RW_SHIFT U(0x4)
802#define MODE_RW_MASK U(0x1)
803#define MODE_RW_64 U(0x0)
804#define MODE_RW_32 U(0x1)
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100805
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700806#define MODE_EL_SHIFT U(0x2)
807#define MODE_EL_MASK U(0x3)
Alexei Fedorov813c9f92020-03-03 13:31:58 +0000808#define MODE_EL_WIDTH U(0x2)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700809#define MODE_EL3 U(0x3)
810#define MODE_EL2 U(0x2)
811#define MODE_EL1 U(0x1)
812#define MODE_EL0 U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100813
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700814#define MODE32_SHIFT U(0)
815#define MODE32_MASK U(0xf)
816#define MODE32_usr U(0x0)
817#define MODE32_fiq U(0x1)
818#define MODE32_irq U(0x2)
819#define MODE32_svc U(0x3)
820#define MODE32_mon U(0x6)
821#define MODE32_abt U(0x7)
822#define MODE32_hyp U(0xa)
823#define MODE32_und U(0xb)
824#define MODE32_sys U(0xf)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100825
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100826#define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK)
827#define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK)
828#define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK)
829#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100830
John Tsichritzis55534172019-07-23 11:12:41 +0100831#define SPSR_64(el, sp, daif) \
832 (((MODE_RW_64 << MODE_RW_SHIFT) | \
833 (((el) & MODE_EL_MASK) << MODE_EL_SHIFT) | \
834 (((sp) & MODE_SP_MASK) << MODE_SP_SHIFT) | \
835 (((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT)) & \
836 (~(SPSR_SSBS_BIT_AARCH64)))
Vikram Kanigiri9851e422014-05-13 14:42:08 +0100837
838#define SPSR_MODE32(mode, isa, endian, aif) \
John Tsichritzis55534172019-07-23 11:12:41 +0100839 (((MODE_RW_32 << MODE_RW_SHIFT) | \
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700840 (((mode) & MODE32_MASK) << MODE32_SHIFT) | \
841 (((isa) & SPSR_T_MASK) << SPSR_T_SHIFT) | \
842 (((endian) & SPSR_E_MASK) << SPSR_E_SHIFT) | \
John Tsichritzis55534172019-07-23 11:12:41 +0100843 (((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)) & \
844 (~(SPSR_SSBS_BIT_AARCH32)))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100845
Dan Handley0cdebbd2015-03-30 17:15:16 +0100846/*
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100847 * TTBR Definitions
848 */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +0100849#define TTBR_CNP_BIT ULL(0x1)
Isla Mitchellc4a1a072017-08-07 11:20:13 +0100850
851/*
Dan Handley0cdebbd2015-03-30 17:15:16 +0100852 * CTR_EL0 definitions
853 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700854#define CTR_CWG_SHIFT U(24)
855#define CTR_CWG_MASK U(0xf)
856#define CTR_ERG_SHIFT U(20)
857#define CTR_ERG_MASK U(0xf)
858#define CTR_DMINLINE_SHIFT U(16)
859#define CTR_DMINLINE_MASK U(0xf)
860#define CTR_L1IP_SHIFT U(14)
861#define CTR_L1IP_MASK U(0x3)
862#define CTR_IMINLINE_SHIFT U(0)
863#define CTR_IMINLINE_MASK U(0xf)
Dan Handley0cdebbd2015-03-30 17:15:16 +0100864
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700865#define MAX_CACHE_LINE_SIZE U(0x800) /* 2KB */
Achin Gupta4f6ad662013-10-25 09:08:21 +0100866
Achin Gupta405406d2014-05-09 12:00:17 +0100867/* Physical timer control register bit fields shifts and masks */
johpow01fa59c6f2020-10-02 13:41:11 -0500868#define CNTP_CTL_ENABLE_SHIFT U(0)
869#define CNTP_CTL_IMASK_SHIFT U(1)
870#define CNTP_CTL_ISTATUS_SHIFT U(2)
Achin Gupta405406d2014-05-09 12:00:17 +0100871
johpow01fa59c6f2020-10-02 13:41:11 -0500872#define CNTP_CTL_ENABLE_MASK U(1)
873#define CNTP_CTL_IMASK_MASK U(1)
874#define CNTP_CTL_ISTATUS_MASK U(1)
Achin Gupta405406d2014-05-09 12:00:17 +0100875
Varun Wadekar787a1292018-06-18 16:15:51 -0700876/* Physical timer control macros */
877#define CNTP_CTL_ENABLE_BIT (U(1) << CNTP_CTL_ENABLE_SHIFT)
878#define CNTP_CTL_IMASK_BIT (U(1) << CNTP_CTL_IMASK_SHIFT)
879
Achin Gupta4f6ad662013-10-25 09:08:21 +0100880/* Exception Syndrome register bits and bobs */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700881#define ESR_EC_SHIFT U(26)
882#define ESR_EC_MASK U(0x3f)
883#define ESR_EC_LENGTH U(6)
Justin Chadwell83e04882019-08-20 11:01:52 +0100884#define ESR_ISS_SHIFT U(0)
885#define ESR_ISS_LENGTH U(25)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700886#define EC_UNKNOWN U(0x0)
887#define EC_WFE_WFI U(0x1)
888#define EC_AARCH32_CP15_MRC_MCR U(0x3)
889#define EC_AARCH32_CP15_MRRC_MCRR U(0x4)
890#define EC_AARCH32_CP14_MRC_MCR U(0x5)
891#define EC_AARCH32_CP14_LDC_STC U(0x6)
892#define EC_FP_SIMD U(0x7)
893#define EC_AARCH32_CP10_MRC U(0x8)
894#define EC_AARCH32_CP14_MRRC_MCRR U(0xc)
895#define EC_ILLEGAL U(0xe)
896#define EC_AARCH32_SVC U(0x11)
897#define EC_AARCH32_HVC U(0x12)
898#define EC_AARCH32_SMC U(0x13)
899#define EC_AARCH64_SVC U(0x15)
900#define EC_AARCH64_HVC U(0x16)
901#define EC_AARCH64_SMC U(0x17)
902#define EC_AARCH64_SYS U(0x18)
903#define EC_IABORT_LOWER_EL U(0x20)
904#define EC_IABORT_CUR_EL U(0x21)
905#define EC_PC_ALIGN U(0x22)
906#define EC_DABORT_LOWER_EL U(0x24)
907#define EC_DABORT_CUR_EL U(0x25)
908#define EC_SP_ALIGN U(0x26)
909#define EC_AARCH32_FP U(0x28)
910#define EC_AARCH64_FP U(0x2c)
911#define EC_SERROR U(0x2f)
Justin Chadwell83e04882019-08-20 11:01:52 +0100912#define EC_BRK U(0x3c)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100913
Jeenu Viswambharan96c7df02017-11-30 12:54:15 +0000914/*
915 * External Abort bit in Instruction and Data Aborts synchronous exception
916 * syndromes.
917 */
918#define ESR_ISS_EABORT_EA_BIT U(9)
919
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700920#define EC_BITS(x) (((x) >> ESR_EC_SHIFT) & ESR_EC_MASK)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100921
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800922/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700923#define RMR_RESET_REQUEST_SHIFT U(0x1)
924#define RMR_WARM_RESET_CPU (U(1) << RMR_RESET_REQUEST_SHIFT)
Vignesh Radhakrishnanb4a72942017-03-03 10:58:05 -0800925
Dan Handleyed6ff952014-05-14 17:44:19 +0100926/*******************************************************************************
Antonio Nino Diazac998032017-02-27 17:23:54 +0000927 * Definitions of register offsets, fields and macros for CPU system
928 * instructions.
929 ******************************************************************************/
930
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700931#define TLBI_ADDR_SHIFT U(12)
Antonio Nino Diazac998032017-02-27 17:23:54 +0000932#define TLBI_ADDR_MASK ULL(0x00000FFFFFFFFFFF)
933#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
934
935/*******************************************************************************
Dan Handleyed6ff952014-05-14 17:44:19 +0100936 * Definitions of register offsets and fields in the CNTCTLBase Frame of the
937 * system level implementation of the Generic Timer.
938 ******************************************************************************/
Soby Mathew2d9f7952018-06-11 16:21:30 +0100939#define CNTCTLBASE_CNTFRQ U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700940#define CNTNSAR U(0x4)
941#define CNTNSAR_NS_SHIFT(x) (x)
Dan Handleyed6ff952014-05-14 17:44:19 +0100942
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700943#define CNTACR_BASE(x) (U(0x40) + ((x) << 2))
944#define CNTACR_RPCT_SHIFT U(0x0)
945#define CNTACR_RVCT_SHIFT U(0x1)
946#define CNTACR_RFRQ_SHIFT U(0x2)
947#define CNTACR_RVOFF_SHIFT U(0x3)
948#define CNTACR_RWVT_SHIFT U(0x4)
949#define CNTACR_RWPT_SHIFT U(0x5)
Dan Handleyed6ff952014-05-14 17:44:19 +0100950
Soby Mathew2d9f7952018-06-11 16:21:30 +0100951/*******************************************************************************
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000952 * Definitions of register offsets and fields in the CNTBaseN Frame of the
Soby Mathew2d9f7952018-06-11 16:21:30 +0100953 * system level implementation of the Generic Timer.
954 ******************************************************************************/
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +0000955/* Physical Count register. */
956#define CNTPCT_LO U(0x0)
957/* Counter Frequency register. */
958#define CNTBASEN_CNTFRQ U(0x10)
959/* Physical Timer CompareValue register. */
960#define CNTP_CVAL_LO U(0x20)
961/* Physical Timer Control register. */
962#define CNTP_CTL U(0x2c)
Soby Mathew2d9f7952018-06-11 16:21:30 +0100963
David Cunado5f55e282016-10-31 17:37:34 +0000964/* PMCR_EL0 definitions */
David Cunado4168f2f2017-10-02 17:41:39 +0100965#define PMCR_EL0_RESET_VAL U(0x0)
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700966#define PMCR_EL0_N_SHIFT U(11)
967#define PMCR_EL0_N_MASK U(0x1f)
David Cunado5f55e282016-10-31 17:37:34 +0000968#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100969#define PMCR_EL0_LP_BIT (U(1) << 7)
David Cunado4168f2f2017-10-02 17:41:39 +0100970#define PMCR_EL0_LC_BIT (U(1) << 6)
971#define PMCR_EL0_DP_BIT (U(1) << 5)
972#define PMCR_EL0_X_BIT (U(1) << 4)
973#define PMCR_EL0_D_BIT (U(1) << 3)
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100974#define PMCR_EL0_C_BIT (U(1) << 2)
975#define PMCR_EL0_P_BIT (U(1) << 1)
976#define PMCR_EL0_E_BIT (U(1) << 0)
David Cunado5f55e282016-10-31 17:37:34 +0000977
Isla Mitchell02c63072017-07-21 14:44:36 +0100978/*******************************************************************************
David Cunadoce88eee2017-10-20 11:30:57 +0100979 * Definitions for system register interface to SVE
980 ******************************************************************************/
981#define ZCR_EL3 S3_6_C1_C2_0
982#define ZCR_EL2 S3_4_C1_C2_0
983
984/* ZCR_EL3 definitions */
985#define ZCR_EL3_LEN_MASK U(0xf)
986
987/* ZCR_EL2 definitions */
988#define ZCR_EL2_LEN_MASK U(0xf)
989
990/*******************************************************************************
johpow019baade32021-07-08 14:14:00 -0500991 * Definitions for system register interface to SME as needed in EL3
992 ******************************************************************************/
993#define ID_AA64SMFR0_EL1 S3_0_C0_C4_5
994#define SMCR_EL3 S3_6_C1_C2_6
995
996/* ID_AA64SMFR0_EL1 definitions */
997#define ID_AA64SMFR0_EL1_FA64_BIT (UL(1) << 63)
998
999/* SMCR_ELx definitions */
1000#define SMCR_ELX_LEN_SHIFT U(0)
1001#define SMCR_ELX_LEN_MASK U(0x1ff)
1002#define SMCR_ELX_FA64_BIT (U(1) << 31)
1003
1004/*******************************************************************************
Isla Mitchell02c63072017-07-21 14:44:36 +01001005 * Definitions of MAIR encodings for device and normal memory
1006 ******************************************************************************/
1007/*
1008 * MAIR encodings for device memory attributes.
1009 */
1010#define MAIR_DEV_nGnRnE ULL(0x0)
1011#define MAIR_DEV_nGnRE ULL(0x4)
1012#define MAIR_DEV_nGRE ULL(0x8)
1013#define MAIR_DEV_GRE ULL(0xc)
1014
1015/*
1016 * MAIR encodings for normal memory attributes.
1017 *
1018 * Cache Policy
1019 * WT: Write Through
1020 * WB: Write Back
1021 * NC: Non-Cacheable
1022 *
1023 * Transient Hint
1024 * NTR: Non-Transient
1025 * TR: Transient
1026 *
1027 * Allocation Policy
1028 * RA: Read Allocate
1029 * WA: Write Allocate
1030 * RWA: Read and Write Allocate
1031 * NA: No Allocation
1032 */
1033#define MAIR_NORM_WT_TR_WA ULL(0x1)
1034#define MAIR_NORM_WT_TR_RA ULL(0x2)
1035#define MAIR_NORM_WT_TR_RWA ULL(0x3)
1036#define MAIR_NORM_NC ULL(0x4)
1037#define MAIR_NORM_WB_TR_WA ULL(0x5)
1038#define MAIR_NORM_WB_TR_RA ULL(0x6)
1039#define MAIR_NORM_WB_TR_RWA ULL(0x7)
1040#define MAIR_NORM_WT_NTR_NA ULL(0x8)
1041#define MAIR_NORM_WT_NTR_WA ULL(0x9)
1042#define MAIR_NORM_WT_NTR_RA ULL(0xa)
1043#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
1044#define MAIR_NORM_WB_NTR_NA ULL(0xc)
1045#define MAIR_NORM_WB_NTR_WA ULL(0xd)
1046#define MAIR_NORM_WB_NTR_RA ULL(0xe)
1047#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
1048
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001049#define MAIR_NORM_OUTER_SHIFT U(4)
Isla Mitchell02c63072017-07-21 14:44:36 +01001050
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001051#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) \
1052 ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
Isla Mitchell02c63072017-07-21 14:44:36 +01001053
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +01001054/* PAR_EL1 fields */
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001055#define PAR_F_SHIFT U(0)
1056#define PAR_F_MASK ULL(0x1)
1057#define PAR_ADDR_SHIFT U(12)
1058#define PAR_ADDR_MASK (BIT(40) - ULL(1)) /* 40-bits-wide page address */
Jeenu Viswambharan1dc771b2017-10-19 09:15:15 +01001059
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +01001060/*******************************************************************************
1061 * Definitions for system register interface to SPE
1062 ******************************************************************************/
1063#define PMBLIMITR_EL1 S3_0_C9_C10_0
1064
Dimitris Papastamose08005a2017-10-12 13:02:29 +01001065/*******************************************************************************
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001066 * Definitions for system register interface to MPAM
1067 ******************************************************************************/
1068#define MPAMIDR_EL1 S3_0_C10_C4_4
1069#define MPAM2_EL2 S3_4_C10_C5_0
1070#define MPAMHCR_EL2 S3_4_C10_C4_0
1071#define MPAM3_EL3 S3_6_C10_C5_0
1072
1073/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -05001074 * Definitions for system register interface to AMU for FEAT_AMUv1
Dimitris Papastamose08005a2017-10-12 13:02:29 +01001075 ******************************************************************************/
1076#define AMCR_EL0 S3_3_C13_C2_0
1077#define AMCFGR_EL0 S3_3_C13_C2_1
1078#define AMCGCR_EL0 S3_3_C13_C2_2
1079#define AMUSERENR_EL0 S3_3_C13_C2_3
1080#define AMCNTENCLR0_EL0 S3_3_C13_C2_4
1081#define AMCNTENSET0_EL0 S3_3_C13_C2_5
1082#define AMCNTENCLR1_EL0 S3_3_C13_C3_0
1083#define AMCNTENSET1_EL0 S3_3_C13_C3_1
1084
1085/* Activity Monitor Group 0 Event Counter Registers */
1086#define AMEVCNTR00_EL0 S3_3_C13_C4_0
1087#define AMEVCNTR01_EL0 S3_3_C13_C4_1
1088#define AMEVCNTR02_EL0 S3_3_C13_C4_2
1089#define AMEVCNTR03_EL0 S3_3_C13_C4_3
1090
1091/* Activity Monitor Group 0 Event Type Registers */
1092#define AMEVTYPER00_EL0 S3_3_C13_C6_0
1093#define AMEVTYPER01_EL0 S3_3_C13_C6_1
1094#define AMEVTYPER02_EL0 S3_3_C13_C6_2
1095#define AMEVTYPER03_EL0 S3_3_C13_C6_3
1096
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001097/* Activity Monitor Group 1 Event Counter Registers */
1098#define AMEVCNTR10_EL0 S3_3_C13_C12_0
1099#define AMEVCNTR11_EL0 S3_3_C13_C12_1
1100#define AMEVCNTR12_EL0 S3_3_C13_C12_2
1101#define AMEVCNTR13_EL0 S3_3_C13_C12_3
1102#define AMEVCNTR14_EL0 S3_3_C13_C12_4
1103#define AMEVCNTR15_EL0 S3_3_C13_C12_5
1104#define AMEVCNTR16_EL0 S3_3_C13_C12_6
1105#define AMEVCNTR17_EL0 S3_3_C13_C12_7
1106#define AMEVCNTR18_EL0 S3_3_C13_C13_0
1107#define AMEVCNTR19_EL0 S3_3_C13_C13_1
1108#define AMEVCNTR1A_EL0 S3_3_C13_C13_2
1109#define AMEVCNTR1B_EL0 S3_3_C13_C13_3
1110#define AMEVCNTR1C_EL0 S3_3_C13_C13_4
1111#define AMEVCNTR1D_EL0 S3_3_C13_C13_5
1112#define AMEVCNTR1E_EL0 S3_3_C13_C13_6
1113#define AMEVCNTR1F_EL0 S3_3_C13_C13_7
1114
1115/* Activity Monitor Group 1 Event Type Registers */
1116#define AMEVTYPER10_EL0 S3_3_C13_C14_0
1117#define AMEVTYPER11_EL0 S3_3_C13_C14_1
1118#define AMEVTYPER12_EL0 S3_3_C13_C14_2
1119#define AMEVTYPER13_EL0 S3_3_C13_C14_3
1120#define AMEVTYPER14_EL0 S3_3_C13_C14_4
1121#define AMEVTYPER15_EL0 S3_3_C13_C14_5
1122#define AMEVTYPER16_EL0 S3_3_C13_C14_6
1123#define AMEVTYPER17_EL0 S3_3_C13_C14_7
1124#define AMEVTYPER18_EL0 S3_3_C13_C15_0
1125#define AMEVTYPER19_EL0 S3_3_C13_C15_1
1126#define AMEVTYPER1A_EL0 S3_3_C13_C15_2
1127#define AMEVTYPER1B_EL0 S3_3_C13_C15_3
1128#define AMEVTYPER1C_EL0 S3_3_C13_C15_4
1129#define AMEVTYPER1D_EL0 S3_3_C13_C15_5
1130#define AMEVTYPER1E_EL0 S3_3_C13_C15_6
1131#define AMEVTYPER1F_EL0 S3_3_C13_C15_7
1132
Chris Kaya5fde282021-05-26 11:58:23 +01001133/* AMCNTENSET0_EL0 definitions */
1134#define AMCNTENSET0_EL0_Pn_SHIFT U(0)
1135#define AMCNTENSET0_EL0_Pn_MASK ULL(0xffff)
1136
1137/* AMCNTENSET1_EL0 definitions */
1138#define AMCNTENSET1_EL0_Pn_SHIFT U(0)
1139#define AMCNTENSET1_EL0_Pn_MASK ULL(0xffff)
1140
1141/* AMCNTENCLR0_EL0 definitions */
1142#define AMCNTENCLR0_EL0_Pn_SHIFT U(0)
1143#define AMCNTENCLR0_EL0_Pn_MASK ULL(0xffff)
1144
1145/* AMCNTENCLR1_EL0 definitions */
1146#define AMCNTENCLR1_EL0_Pn_SHIFT U(0)
1147#define AMCNTENCLR1_EL0_Pn_MASK ULL(0xffff)
1148
Alexei Fedorov7e6306b2020-07-14 08:17:56 +01001149/* AMCFGR_EL0 definitions */
1150#define AMCFGR_EL0_NCG_SHIFT U(28)
1151#define AMCFGR_EL0_NCG_MASK U(0xf)
1152#define AMCFGR_EL0_N_SHIFT U(0)
1153#define AMCFGR_EL0_N_MASK U(0xff)
1154
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001155/* AMCGCR_EL0 definitions */
Chris Kaya40141d2021-05-25 12:33:18 +01001156#define AMCGCR_EL0_CG0NC_SHIFT U(0)
1157#define AMCGCR_EL0_CG0NC_MASK U(0xff)
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001158#define AMCGCR_EL0_CG1NC_SHIFT U(8)
Dimitris Papastamos525c37a2017-11-13 09:49:45 +00001159#define AMCGCR_EL0_CG1NC_MASK U(0xff)
1160
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001161/* MPAM register definitions */
1162#define MPAM3_EL3_MPAMEN_BIT (ULL(1) << 63)
Louis Mayencourtbdfa1032019-02-11 11:25:50 +00001163#define MPAMHCR_EL2_TRAP_MPAMIDR_EL1 (ULL(1) << 31)
1164
1165#define MPAM2_EL2_TRAPMPAM0EL1 (ULL(1) << 49)
1166#define MPAM2_EL2_TRAPMPAM1EL1 (ULL(1) << 48)
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +01001167
1168#define MPAMIDR_HAS_HCR_BIT (ULL(1) << 17)
1169
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001170/*******************************************************************************
johpow01fa59c6f2020-10-02 13:41:11 -05001171 * Definitions for system register interface to AMU for FEAT_AMUv1p1
1172 ******************************************************************************/
1173
1174/* Definition for register defining which virtual offsets are implemented. */
1175#define AMCG1IDR_EL0 S3_3_C13_C2_6
1176#define AMCG1IDR_CTR_MASK ULL(0xffff)
1177#define AMCG1IDR_CTR_SHIFT U(0)
1178#define AMCG1IDR_VOFF_MASK ULL(0xffff)
1179#define AMCG1IDR_VOFF_SHIFT U(16)
1180
1181/* New bit added to AMCR_EL0 */
Chris Kaya5fde282021-05-26 11:58:23 +01001182#define AMCR_CG1RZ_SHIFT U(17)
1183#define AMCR_CG1RZ_BIT (ULL(0x1) << AMCR_CG1RZ_SHIFT)
johpow01fa59c6f2020-10-02 13:41:11 -05001184
1185/*
1186 * Definitions for virtual offset registers for architected activity monitor
1187 * event counters.
1188 * AMEVCNTVOFF01_EL2 intentionally left undefined, as it does not exist.
1189 */
1190#define AMEVCNTVOFF00_EL2 S3_4_C13_C8_0
1191#define AMEVCNTVOFF02_EL2 S3_4_C13_C8_2
1192#define AMEVCNTVOFF03_EL2 S3_4_C13_C8_3
1193
1194/*
1195 * Definitions for virtual offset registers for auxiliary activity monitor event
1196 * counters.
1197 */
1198#define AMEVCNTVOFF10_EL2 S3_4_C13_C10_0
1199#define AMEVCNTVOFF11_EL2 S3_4_C13_C10_1
1200#define AMEVCNTVOFF12_EL2 S3_4_C13_C10_2
1201#define AMEVCNTVOFF13_EL2 S3_4_C13_C10_3
1202#define AMEVCNTVOFF14_EL2 S3_4_C13_C10_4
1203#define AMEVCNTVOFF15_EL2 S3_4_C13_C10_5
1204#define AMEVCNTVOFF16_EL2 S3_4_C13_C10_6
1205#define AMEVCNTVOFF17_EL2 S3_4_C13_C10_7
1206#define AMEVCNTVOFF18_EL2 S3_4_C13_C11_0
1207#define AMEVCNTVOFF19_EL2 S3_4_C13_C11_1
1208#define AMEVCNTVOFF1A_EL2 S3_4_C13_C11_2
1209#define AMEVCNTVOFF1B_EL2 S3_4_C13_C11_3
1210#define AMEVCNTVOFF1C_EL2 S3_4_C13_C11_4
1211#define AMEVCNTVOFF1D_EL2 S3_4_C13_C11_5
1212#define AMEVCNTVOFF1E_EL2 S3_4_C13_C11_6
1213#define AMEVCNTVOFF1F_EL2 S3_4_C13_C11_7
1214
1215/*******************************************************************************
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001216 * Realm management extension register definitions
1217 ******************************************************************************/
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001218#define GPCCR_EL3 S3_6_C2_C1_6
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001219#define GPTBR_EL3 S3_6_C2_C1_4
1220
Zelalem Aweke79e3d292021-07-08 16:51:14 -05001221/*******************************************************************************
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001222 * RAS system registers
Sathees Balya0911df12018-12-06 13:33:24 +00001223 ******************************************************************************/
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001224#define DISR_EL1 S3_0_C12_C1_1
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001225#define DISR_A_BIT U(31)
Jeenu Viswambharan9a7ce2f2018-04-04 16:07:11 +01001226
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001227#define ERRIDR_EL1 S3_0_C5_C3_0
Antonio Nino Diaza3fbeaa2018-07-12 13:23:59 +01001228#define ERRIDR_MASK U(0xffff)
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001229
1230#define ERRSELR_EL1 S3_0_C5_C3_1
1231
1232/* System register access to Standard Error Record registers */
1233#define ERXFR_EL1 S3_0_C5_C4_0
1234#define ERXCTLR_EL1 S3_0_C5_C4_1
1235#define ERXSTATUS_EL1 S3_0_C5_C4_2
1236#define ERXADDR_EL1 S3_0_C5_C4_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001237#define ERXPFGF_EL1 S3_0_C5_C4_4
1238#define ERXPFGCTL_EL1 S3_0_C5_C4_5
1239#define ERXPFGCDN_EL1 S3_0_C5_C4_6
Jan Dabros82ef8bf2018-08-30 13:52:23 +02001240#define ERXMISC0_EL1 S3_0_C5_C5_0
1241#define ERXMISC1_EL1 S3_0_C5_C5_1
Jeenu Viswambharan19f6cf22017-12-07 08:43:05 +00001242
johpow017d52a8f2022-03-09 16:23:04 -06001243#define ERXCTLR_ED_SHIFT U(0)
1244#define ERXCTLR_ED_BIT (U(1) << ERXCTLR_ED_SHIFT)
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001245#define ERXCTLR_UE_BIT (U(1) << 4)
1246
1247#define ERXPFGCTL_UC_BIT (U(1) << 1)
1248#define ERXPFGCTL_UEU_BIT (U(1) << 2)
1249#define ERXPFGCTL_CDEN_BIT (U(1) << 31)
1250
1251/*******************************************************************************
1252 * Armv8.3 Pointer Authentication Registers
Sathees Balya0911df12018-12-06 13:33:24 +00001253 ******************************************************************************/
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001254#define APIAKeyLo_EL1 S3_0_C2_C1_0
1255#define APIAKeyHi_EL1 S3_0_C2_C1_1
1256#define APIBKeyLo_EL1 S3_0_C2_C1_2
1257#define APIBKeyHi_EL1 S3_0_C2_C1_3
1258#define APDAKeyLo_EL1 S3_0_C2_C2_0
1259#define APDAKeyHi_EL1 S3_0_C2_C2_1
1260#define APDBKeyLo_EL1 S3_0_C2_C2_2
1261#define APDBKeyHi_EL1 S3_0_C2_C2_3
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001262#define APGAKeyLo_EL1 S3_0_C2_C3_0
Antonio Nino Diaz594811b2019-01-31 11:58:00 +00001263#define APGAKeyHi_EL1 S3_0_C2_C3_1
Antonio Nino Diaz8257f5b2018-11-22 15:53:17 +00001264
Sathees Balya0911df12018-12-06 13:33:24 +00001265/*******************************************************************************
1266 * Armv8.4 Data Independent Timing Registers
1267 ******************************************************************************/
1268#define DIT S3_3_C4_C2_5
1269#define DIT_BIT BIT(24)
1270
John Tsichritzis1f9ff492019-03-04 16:41:26 +00001271/*******************************************************************************
1272 * Armv8.5 - new MSR encoding to directly access PSTATE.SSBS field
1273 ******************************************************************************/
1274#define SSBS S3_3_C4_C2_6
1275
Justin Chadwell1c7c13a2019-07-18 14:25:33 +01001276/*******************************************************************************
1277 * Armv8.5 - Memory Tagging Extension Registers
1278 ******************************************************************************/
1279#define TFSRE0_EL1 S3_0_C5_C6_1
1280#define TFSR_EL1 S3_0_C5_C6_0
1281#define RGSR_EL1 S3_0_C1_C0_5
1282#define GCR_EL1 S3_0_C1_C0_6
1283
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001284/*******************************************************************************
Andre Przywarabdc76f12022-11-21 17:07:25 +00001285 * Armv8.5 - Random Number Generator Registers
1286 ******************************************************************************/
1287#define RNDR S3_3_C2_C4_0
1288#define RNDRRS S3_3_C2_C4_1
1289
1290/*******************************************************************************
johpow01f91e59f2021-08-04 19:38:18 -05001291 * FEAT_HCX - Extended Hypervisor Configuration Register
1292 ******************************************************************************/
johpow019baade32021-07-08 14:14:00 -05001293#define HCRX_EL2 S3_4_C1_C2_2
1294#define HCRX_EL2_FGTnXS_BIT (UL(1) << 4)
1295#define HCRX_EL2_FnXS_BIT (UL(1) << 3)
1296#define HCRX_EL2_EnASR_BIT (UL(1) << 2)
1297#define HCRX_EL2_EnALS_BIT (UL(1) << 1)
1298#define HCRX_EL2_EnAS0_BIT (UL(1) << 0)
johpow01f91e59f2021-08-04 19:38:18 -05001299
1300/*******************************************************************************
Madhukar Pappireddy90d65322019-10-30 14:24:39 -05001301 * Definitions for DynamicIQ Shared Unit registers
1302 ******************************************************************************/
1303#define CLUSTERPWRDN_EL1 S3_0_c15_c3_6
1304
1305/* CLUSTERPWRDN_EL1 register definitions */
1306#define DSU_CLUSTER_PWR_OFF 0
1307#define DSU_CLUSTER_PWR_ON 1
1308#define DSU_CLUSTER_PWR_MASK U(1)
1309
Chris Kay03be39d2021-05-05 13:38:30 +01001310/*******************************************************************************
1311 * Definitions for CPU Power/Performance Management registers
1312 ******************************************************************************/
1313
1314#define CPUPPMCR_EL3 S3_6_C15_C2_0
1315#define CPUPPMCR_EL3_MPMMPINCTL_SHIFT UINT64_C(0)
1316#define CPUPPMCR_EL3_MPMMPINCTL_MASK UINT64_C(0x1)
1317
1318#define CPUMPMMCR_EL3 S3_6_C15_C2_1
1319#define CPUMPMMCR_EL3_MPMM_EN_SHIFT UINT64_C(0)
1320#define CPUMPMMCR_EL3_MPMM_EN_MASK UINT64_C(0x1)
1321
Antonio Nino Diaz6f3ccc52018-07-20 09:17:26 +01001322#endif /* ARCH_H */