Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __TEGRA_DEF_H__ |
| 8 | #define __TEGRA_DEF_H__ |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | /******************************************************************************* |
| 13 | * These values are used by the PSCI implementation during the `CPU_SUSPEND` |
| 14 | * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' |
| 15 | * parameter. |
| 16 | ******************************************************************************/ |
| 17 | #define PSTATE_ID_CORE_IDLE 6 |
| 18 | #define PSTATE_ID_CORE_POWERDN 7 |
| 19 | #define PSTATE_ID_SOC_POWERDN 2 |
| 20 | |
| 21 | /******************************************************************************* |
| 22 | * Platform power states (used by PSCI framework) |
| 23 | * |
| 24 | * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID |
| 25 | * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID |
| 26 | ******************************************************************************/ |
| 27 | #define PLAT_MAX_RET_STATE 1 |
| 28 | #define PLAT_MAX_OFF_STATE 8 |
| 29 | |
| 30 | /******************************************************************************* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 31 | * Secure IRQ definitions |
| 32 | ******************************************************************************/ |
| 33 | #define TEGRA186_MAX_SEC_IRQS 5 |
| 34 | #define TEGRA186_BPMP_WDT_IRQ 46 |
| 35 | #define TEGRA186_SPE_WDT_IRQ 47 |
| 36 | #define TEGRA186_SCE_WDT_IRQ 48 |
| 37 | #define TEGRA186_TOP_WDT_IRQ 49 |
| 38 | #define TEGRA186_AON_WDT_IRQ 50 |
| 39 | |
| 40 | #define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */ |
| 41 | |
| 42 | /******************************************************************************* |
| 43 | * Tegra Miscellanous register constants |
| 44 | ******************************************************************************/ |
Steven Kao | 7dfbca7 | 2017-07-25 12:44:32 +0800 | [diff] [blame] | 45 | #define TEGRA_MISC_BASE 0x00100000U |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 46 | |
Steven Kao | 7dfbca7 | 2017-07-25 12:44:32 +0800 | [diff] [blame] | 47 | #define HARDWARE_REVISION_OFFSET 0x4U |
| 48 | #define MISCREG_EMU_REVID 0x3160U |
| 49 | #define BOARD_MASK_BITS 0xFFU |
| 50 | #define BOARD_SHIFT_BITS 24U |
| 51 | #define MISCREG_PFCFG 0x200CU |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 52 | |
| 53 | /******************************************************************************* |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 54 | * Tegra Memory Controller constants |
| 55 | ******************************************************************************/ |
| 56 | #define TEGRA_MC_STREAMID_BASE 0x02C00000 |
| 57 | #define TEGRA_MC_BASE 0x02C10000 |
| 58 | |
Varun Wadekar | 07897a9 | 2017-02-13 09:00:04 -0800 | [diff] [blame] | 59 | /* General Security Carveout register macros */ |
| 60 | #define MC_GSC_CONFIG_REGS_SIZE 0x40 |
| 61 | #define MC_GSC_LOCK_CFG_SETTINGS_BIT (1 << 1) |
| 62 | #define MC_GSC_ENABLE_TZ_LOCK_BIT (1 << 0) |
| 63 | #define MC_GSC_SIZE_RANGE_4KB_SHIFT 27 |
| 64 | #define MC_GSC_BASE_LO_SHIFT 12 |
| 65 | #define MC_GSC_BASE_LO_MASK 0xFFFFF |
| 66 | #define MC_GSC_BASE_HI_SHIFT 0 |
| 67 | #define MC_GSC_BASE_HI_MASK 3 |
| 68 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 69 | /* TZDRAM carveout configuration registers */ |
| 70 | #define MC_SECURITY_CFG0_0 0x70 |
| 71 | #define MC_SECURITY_CFG1_0 0x74 |
| 72 | #define MC_SECURITY_CFG3_0 0x9BC |
| 73 | |
Harvey Hsieh | 53fc032 | 2017-08-09 16:26:33 +0800 | [diff] [blame] | 74 | #define MC_SECURITY_BOM_MASK (U(0xFFF) << 20) |
| 75 | #define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0) |
| 76 | #define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0) |
| 77 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 78 | /* Video Memory carveout configuration registers */ |
| 79 | #define MC_VIDEO_PROTECT_BASE_HI 0x978 |
| 80 | #define MC_VIDEO_PROTECT_BASE_LO 0x648 |
| 81 | #define MC_VIDEO_PROTECT_SIZE_MB 0x64c |
| 82 | |
Varun Wadekar | 07897a9 | 2017-02-13 09:00:04 -0800 | [diff] [blame] | 83 | /* |
| 84 | * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the |
| 85 | * non-overlapping Video memory region |
| 86 | */ |
| 87 | #define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0 |
| 88 | #define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4 |
| 89 | #define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8 |
| 90 | #define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC |
| 91 | #define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0 |
| 92 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 93 | /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ |
Varun Wadekar | 07897a9 | 2017-02-13 09:00:04 -0800 | [diff] [blame] | 94 | #define MC_TZRAM_CARVEOUT_CFG 0x2190 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 95 | #define MC_TZRAM_BASE_LO 0x2194 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 96 | #define MC_TZRAM_BASE_HI 0x2198 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 97 | #define MC_TZRAM_SIZE 0x219C |
Varun Wadekar | 07897a9 | 2017-02-13 09:00:04 -0800 | [diff] [blame] | 98 | #define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 99 | |
| 100 | /* Memory Controller Reset Control registers */ |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 101 | #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) |
| 102 | #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29) |
| 103 | #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30) |
| 104 | #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31) |
| 105 | |
| 106 | /******************************************************************************* |
| 107 | * Tegra UART Controller constants |
| 108 | ******************************************************************************/ |
| 109 | #define TEGRA_UARTA_BASE 0x03100000 |
| 110 | #define TEGRA_UARTB_BASE 0x03110000 |
| 111 | #define TEGRA_UARTC_BASE 0x0C280000 |
| 112 | #define TEGRA_UARTD_BASE 0x03130000 |
| 113 | #define TEGRA_UARTE_BASE 0x03140000 |
| 114 | #define TEGRA_UARTF_BASE 0x03150000 |
| 115 | #define TEGRA_UARTG_BASE 0x0C290000 |
| 116 | |
| 117 | /******************************************************************************* |
| 118 | * Tegra Fuse Controller related constants |
| 119 | ******************************************************************************/ |
| 120 | #define TEGRA_FUSE_BASE 0x03820000 |
| 121 | #define OPT_SUBREVISION 0x248 |
| 122 | #define SUBREVISION_MASK 0xF |
| 123 | |
| 124 | /******************************************************************************* |
| 125 | * GICv2 & interrupt handling related constants |
| 126 | ******************************************************************************/ |
| 127 | #define TEGRA_GICD_BASE 0x03881000 |
| 128 | #define TEGRA_GICC_BASE 0x03882000 |
| 129 | |
| 130 | /******************************************************************************* |
| 131 | * Security Engine related constants |
| 132 | ******************************************************************************/ |
| 133 | #define TEGRA_SE0_BASE 0x03AC0000 |
| 134 | #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C |
| 135 | #define TEGRA_PKA1_BASE 0x03AD0000 |
| 136 | #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 |
| 137 | #define TEGRA_RNG1_BASE 0x03AE0000 |
| 138 | #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 |
| 139 | |
| 140 | /******************************************************************************* |
| 141 | * Tegra micro-seconds timer constants |
| 142 | ******************************************************************************/ |
| 143 | #define TEGRA_TMRUS_BASE 0x0C2E0000 |
Steven Kao | 0d87c13 | 2017-03-07 13:13:27 +0800 | [diff] [blame] | 144 | #define TEGRA_TMRUS_SIZE 0x10000 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 145 | |
| 146 | /******************************************************************************* |
| 147 | * Tegra Power Mgmt Controller constants |
| 148 | ******************************************************************************/ |
| 149 | #define TEGRA_PMC_BASE 0x0C360000 |
| 150 | |
| 151 | /******************************************************************************* |
| 152 | * Tegra scratch registers constants |
| 153 | ******************************************************************************/ |
| 154 | #define TEGRA_SCRATCH_BASE 0x0C390000 |
| 155 | #define SECURE_SCRATCH_RSV1_LO 0x06C |
| 156 | #define SECURE_SCRATCH_RSV1_HI 0x070 |
| 157 | #define SECURE_SCRATCH_RSV6 0x094 |
| 158 | #define SECURE_SCRATCH_RSV11_LO 0x0BC |
| 159 | #define SECURE_SCRATCH_RSV11_HI 0x0C0 |
| 160 | #define SECURE_SCRATCH_RSV53_LO 0x20C |
| 161 | #define SECURE_SCRATCH_RSV53_HI 0x210 |
| 162 | #define SECURE_SCRATCH_RSV54_HI 0x218 |
| 163 | #define SECURE_SCRATCH_RSV55_LO 0x21C |
| 164 | #define SECURE_SCRATCH_RSV55_HI 0x220 |
| 165 | |
| 166 | /******************************************************************************* |
| 167 | * Tegra Memory Mapped Control Register Access Bus constants |
| 168 | ******************************************************************************/ |
| 169 | #define TEGRA_MMCRAB_BASE 0x0E000000 |
| 170 | |
| 171 | /******************************************************************************* |
| 172 | * Tegra SMMU Controller constants |
| 173 | ******************************************************************************/ |
Pritesh Raithatha | 1c2b5c7 | 2017-01-24 14:16:07 +0530 | [diff] [blame] | 174 | #define TEGRA_SMMU0_BASE 0x12000000 |
| 175 | #define TEGRA_SMMU1_BASE 0x11000000 |
| 176 | #define TEGRA_SMMU2_BASE 0x10000000 |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 177 | |
| 178 | /******************************************************************************* |
| 179 | * Tegra TZRAM constants |
| 180 | ******************************************************************************/ |
| 181 | #define TEGRA_TZRAM_BASE 0x40000000 |
| 182 | #define TEGRA_TZRAM_SIZE 0x40000 |
| 183 | |
| 184 | /******************************************************************************* |
| 185 | * Tegra Clock and Reset Controller constants |
| 186 | ******************************************************************************/ |
Steven Kao | 86d3a2b | 2017-08-31 13:35:01 +0800 | [diff] [blame] | 187 | #define TEGRA_CAR_RESET_BASE 0x20000000 |
Varun Wadekar | f2d5466 | 2017-04-26 08:57:27 -0700 | [diff] [blame] | 188 | #define TEGRA_GPU_RESET_REG_OFFSET 0x18UL |
| 189 | #define GPU_RESET_BIT (1UL << 0) |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 190 | |
Varun Wadekar | 0075990 | 2017-05-31 11:41:00 -0700 | [diff] [blame] | 191 | /******************************************************************************* |
Ajay Gupta | 8162109 | 2017-08-01 15:53:04 -0700 | [diff] [blame] | 192 | * XUSB PADCTL |
| 193 | ******************************************************************************/ |
| 194 | #define TEGRA_XUSB_PADCTL_BASE (0x3520000U) |
| 195 | #define TEGRA_XUSB_PADCTL_SIZE (0x10000U) |
| 196 | #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU) |
| 197 | #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U) |
| 198 | #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U) |
| 199 | #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U) |
| 200 | #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU) |
| 201 | #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU) |
| 202 | |
| 203 | /******************************************************************************* |
| 204 | * XUSB STREAMIDs |
| 205 | ******************************************************************************/ |
| 206 | #define TEGRA_SID_XUSB_HOST (0x1bU) |
| 207 | #define TEGRA_SID_XUSB_DEV (0x1cU) |
| 208 | #define TEGRA_SID_XUSB_VF0 (0x5dU) |
| 209 | #define TEGRA_SID_XUSB_VF1 (0x5eU) |
| 210 | #define TEGRA_SID_XUSB_VF2 (0x5fU) |
| 211 | #define TEGRA_SID_XUSB_VF3 (0x60U) |
| 212 | |
Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame] | 213 | #endif /* __TEGRA_DEF_H__ */ |