commit 53fc032235a5fe2e2f885598660e6412951a1d1b
author Harvey Hsieh <hhsieh@nvidia.com> Wed Aug 09 16:26:33 2017 +0800
committer Varun Wadekar <vwadekar@nvidia.com> Thu Nov 28 11:14:21 2019 -0800
tree d0b1312220963d151747b5b9486cfdd51e00a044
parent 74813f91a2c83fe5678e997fdbbc6d576dab7163

Tegra194: add MC_SECURITY mask defines

This patch adds masks for the TZDRAM base/size registers.

Change-Id: I5f688793be8cace28d2aa2d177a295e4faffd666
Signed-off-by: Harvey Hsieh <hhsieh@nvidia.com>

plat/nvidia/tegra/include/t194/tegra_def.h

diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 0734429..577ee9b 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -110,6 +110,10 @@
 #define MC_SECURITY_CFG1_0		0x74
 #define MC_SECURITY_CFG3_0		0x9BC
 
+#define MC_SECURITY_BOM_MASK		(U(0xFFF) << 20)
+#define MC_SECURITY_SIZE_MB_MASK	(U(0x1FFF) << 0)
+#define MC_SECURITY_BOM_HI_MASK		(U(0x3) << 0)
+
 /* Video Memory carveout configuration registers */
 #define MC_VIDEO_PROTECT_BASE_HI	0x978
 #define MC_VIDEO_PROTECT_BASE_LO	0x648