| Varun Wadekar | ecd6a5a | 2018-04-09 17:48:58 -0700 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef __TEGRA_DEF_H__ |
| 8 | #define __TEGRA_DEF_H__ |
| 9 | |
| 10 | #include <lib/utils_def.h> |
| 11 | |
| 12 | /******************************************************************************* |
| 13 | * These values are used by the PSCI implementation during the `CPU_SUSPEND` |
| 14 | * and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state' |
| 15 | * parameter. |
| 16 | ******************************************************************************/ |
| 17 | #define PSTATE_ID_CORE_IDLE 6 |
| 18 | #define PSTATE_ID_CORE_POWERDN 7 |
| 19 | #define PSTATE_ID_SOC_POWERDN 2 |
| 20 | |
| 21 | /******************************************************************************* |
| 22 | * Platform power states (used by PSCI framework) |
| 23 | * |
| 24 | * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID |
| 25 | * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID |
| 26 | ******************************************************************************/ |
| 27 | #define PLAT_MAX_RET_STATE 1 |
| 28 | #define PLAT_MAX_OFF_STATE 8 |
| 29 | |
| 30 | /******************************************************************************* |
| 31 | * Implementation defined ACTLR_EL3 bit definitions |
| 32 | ******************************************************************************/ |
| 33 | #define ACTLR_EL3_L2ACTLR_BIT (1 << 6) |
| 34 | #define ACTLR_EL3_L2ECTLR_BIT (1 << 5) |
| 35 | #define ACTLR_EL3_L2CTLR_BIT (1 << 4) |
| 36 | #define ACTLR_EL3_CPUECTLR_BIT (1 << 1) |
| 37 | #define ACTLR_EL3_CPUACTLR_BIT (1 << 0) |
| 38 | #define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \ |
| 39 | ACTLR_EL3_L2ECTLR_BIT | \ |
| 40 | ACTLR_EL3_L2CTLR_BIT | \ |
| 41 | ACTLR_EL3_CPUECTLR_BIT | \ |
| 42 | ACTLR_EL3_CPUACTLR_BIT) |
| 43 | |
| 44 | /******************************************************************************* |
| 45 | * Secure IRQ definitions |
| 46 | ******************************************************************************/ |
| 47 | #define TEGRA186_MAX_SEC_IRQS 5 |
| 48 | #define TEGRA186_BPMP_WDT_IRQ 46 |
| 49 | #define TEGRA186_SPE_WDT_IRQ 47 |
| 50 | #define TEGRA186_SCE_WDT_IRQ 48 |
| 51 | #define TEGRA186_TOP_WDT_IRQ 49 |
| 52 | #define TEGRA186_AON_WDT_IRQ 50 |
| 53 | |
| 54 | #define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */ |
| 55 | |
| 56 | /******************************************************************************* |
| 57 | * Tegra Miscellanous register constants |
| 58 | ******************************************************************************/ |
| 59 | #define TEGRA_MISC_BASE 0x00100000 |
| 60 | #define HARDWARE_REVISION_OFFSET 0x4 |
| 61 | |
| 62 | #define MISCREG_PFCFG 0x200C |
| 63 | |
| 64 | /******************************************************************************* |
| 65 | * Tegra TSA Controller constants |
| 66 | ******************************************************************************/ |
| 67 | #define TEGRA_TSA_BASE 0x02000000 |
| 68 | |
| 69 | #define TSA_CONFIG_STATIC0_CSW_SESWR 0x1010 |
| 70 | #define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100 |
| 71 | #define TSA_CONFIG_STATIC0_CSW_ETRW 0xD034 |
| 72 | #define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100 |
| 73 | #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x3020 |
| 74 | #define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100 |
| 75 | #define TSA_CONFIG_STATIC0_CSW_AXISW 0x8008 |
| 76 | #define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100 |
| 77 | #define TSA_CONFIG_STATIC0_CSW_HDAW 0xD008 |
| 78 | #define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x1100 |
| 79 | #define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xE018 |
| 80 | #define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100 |
| 81 | #define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x9008 |
| 82 | #define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100 |
| 83 | #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9028 |
| 84 | #define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100 |
| 85 | #define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xB008 |
| 86 | #define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100 |
| 87 | #define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6008 |
| 88 | #define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100 |
| 89 | #define TSA_CONFIG_STATIC0_CSW_AFIW 0xF008 |
| 90 | #define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100 |
| 91 | #define TSA_CONFIG_STATIC0_CSW_SATAW 0x4008 |
| 92 | #define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100 |
| 93 | #define TSA_CONFIG_STATIC0_CSW_EQOSW 0x3038 |
| 94 | #define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100 |
| 95 | #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x6018 |
| 96 | #define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100 |
| 97 | #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x6028 |
| 98 | #define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100 |
| 99 | |
| 100 | #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11) |
| 101 | #define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11) |
| 102 | |
| 103 | /******************************************************************************* |
| 104 | * Tegra Memory Controller constants |
| 105 | ******************************************************************************/ |
| 106 | #define TEGRA_MC_STREAMID_BASE 0x02C00000 |
| 107 | #define TEGRA_MC_BASE 0x02C10000 |
| 108 | |
| 109 | /* TZDRAM carveout configuration registers */ |
| 110 | #define MC_SECURITY_CFG0_0 0x70 |
| 111 | #define MC_SECURITY_CFG1_0 0x74 |
| 112 | #define MC_SECURITY_CFG3_0 0x9BC |
| 113 | |
| 114 | /* Video Memory carveout configuration registers */ |
| 115 | #define MC_VIDEO_PROTECT_BASE_HI 0x978 |
| 116 | #define MC_VIDEO_PROTECT_BASE_LO 0x648 |
| 117 | #define MC_VIDEO_PROTECT_SIZE_MB 0x64c |
| 118 | |
| 119 | /* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */ |
| 120 | #define MC_TZRAM_BASE_LO 0x2194 |
| 121 | #define TZRAM_BASE_LO_SHIFT 12 |
| 122 | #define TZRAM_BASE_LO_MASK 0xFFFFF |
| 123 | #define MC_TZRAM_BASE_HI 0x2198 |
| 124 | #define TZRAM_BASE_HI_SHIFT 0 |
| 125 | #define TZRAM_BASE_HI_MASK 3 |
| 126 | #define MC_TZRAM_SIZE 0x219C |
| 127 | #define TZRAM_SIZE_RANGE_4KB_SHIFT 27 |
| 128 | |
| 129 | #define MC_TZRAM_CARVEOUT_CFG 0x2190 |
| 130 | #define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1) |
| 131 | #define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0) |
| 132 | #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0 |
| 133 | #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4 |
| 134 | #define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25) |
| 135 | #define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7) |
| 136 | #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8 |
| 137 | #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC |
| 138 | #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0 |
| 139 | #define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4 |
| 140 | |
| 141 | #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21C0 |
| 142 | #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21C4 |
| 143 | #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C8 |
| 144 | #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21CC |
| 145 | #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21D0 |
| 146 | #define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21D4 |
| 147 | |
| 148 | /* Memory Controller Reset Control registers */ |
| 149 | #define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27) |
| 150 | #define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28) |
| 151 | #define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29) |
| 152 | #define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30) |
| 153 | #define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31) |
| 154 | |
| 155 | /******************************************************************************* |
| 156 | * Tegra UART Controller constants |
| 157 | ******************************************************************************/ |
| 158 | #define TEGRA_UARTA_BASE 0x03100000 |
| 159 | #define TEGRA_UARTB_BASE 0x03110000 |
| 160 | #define TEGRA_UARTC_BASE 0x0C280000 |
| 161 | #define TEGRA_UARTD_BASE 0x03130000 |
| 162 | #define TEGRA_UARTE_BASE 0x03140000 |
| 163 | #define TEGRA_UARTF_BASE 0x03150000 |
| 164 | #define TEGRA_UARTG_BASE 0x0C290000 |
| 165 | |
| 166 | /******************************************************************************* |
| 167 | * Tegra Fuse Controller related constants |
| 168 | ******************************************************************************/ |
| 169 | #define TEGRA_FUSE_BASE 0x03820000 |
| 170 | #define OPT_SUBREVISION 0x248 |
| 171 | #define SUBREVISION_MASK 0xF |
| 172 | |
| 173 | /******************************************************************************* |
| 174 | * GICv2 & interrupt handling related constants |
| 175 | ******************************************************************************/ |
| 176 | #define TEGRA_GICD_BASE 0x03881000 |
| 177 | #define TEGRA_GICC_BASE 0x03882000 |
| 178 | |
| 179 | /******************************************************************************* |
| 180 | * Security Engine related constants |
| 181 | ******************************************************************************/ |
| 182 | #define TEGRA_SE0_BASE 0x03AC0000 |
| 183 | #define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C |
| 184 | #define TEGRA_PKA1_BASE 0x03AD0000 |
| 185 | #define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144 |
| 186 | #define TEGRA_RNG1_BASE 0x03AE0000 |
| 187 | #define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0 |
| 188 | |
| 189 | /******************************************************************************* |
| 190 | * Tegra micro-seconds timer constants |
| 191 | ******************************************************************************/ |
| 192 | #define TEGRA_TMRUS_BASE 0x0C2E0000 |
| 193 | |
| 194 | /******************************************************************************* |
| 195 | * Tegra Power Mgmt Controller constants |
| 196 | ******************************************************************************/ |
| 197 | #define TEGRA_PMC_BASE 0x0C360000 |
| 198 | |
| 199 | /******************************************************************************* |
| 200 | * Tegra scratch registers constants |
| 201 | ******************************************************************************/ |
| 202 | #define TEGRA_SCRATCH_BASE 0x0C390000 |
| 203 | #define SECURE_SCRATCH_RSV1_LO 0x06C |
| 204 | #define SECURE_SCRATCH_RSV1_HI 0x070 |
| 205 | #define SECURE_SCRATCH_RSV6 0x094 |
| 206 | #define SECURE_SCRATCH_RSV11_LO 0x0BC |
| 207 | #define SECURE_SCRATCH_RSV11_HI 0x0C0 |
| 208 | #define SECURE_SCRATCH_RSV53_LO 0x20C |
| 209 | #define SECURE_SCRATCH_RSV53_HI 0x210 |
| 210 | #define SECURE_SCRATCH_RSV54_HI 0x218 |
| 211 | #define SECURE_SCRATCH_RSV55_LO 0x21C |
| 212 | #define SECURE_SCRATCH_RSV55_HI 0x220 |
| 213 | |
| 214 | /******************************************************************************* |
| 215 | * Tegra Memory Mapped Control Register Access Bus constants |
| 216 | ******************************************************************************/ |
| 217 | #define TEGRA_MMCRAB_BASE 0x0E000000 |
| 218 | |
| 219 | /******************************************************************************* |
| 220 | * Tegra SMMU Controller constants |
| 221 | ******************************************************************************/ |
| 222 | #define TEGRA_SMMU_BASE 0x10000000 |
| 223 | |
| 224 | /******************************************************************************* |
| 225 | * Tegra TZRAM constants |
| 226 | ******************************************************************************/ |
| 227 | #define TEGRA_TZRAM_BASE 0x40000000 |
| 228 | #define TEGRA_TZRAM_SIZE 0x40000 |
| 229 | |
| 230 | /******************************************************************************* |
| 231 | * Tegra Clock and Reset Controller constants |
| 232 | ******************************************************************************/ |
| 233 | #define TEGRA_CAR_RESET_BASE 0x200000000 |
| 234 | |
| 235 | #endif /* __TEGRA_DEF_H__ */ |