commit 7dfbca73596a5d6ef745a4cb43d3aac4c8f8ee31
author Steven Kao <skao@nvidia.com> Tue Jul 25 12:44:32 2017 +0800
committer Varun Wadekar <vwadekar@nvidia.com> Thu Nov 28 11:14:21 2019 -0800
tree bb5e437a2b44babbb1adb6d19e0fb2d1e62c738c
parent 978887fd5a0efc0adac5427c2a09d44f028ba310

Tegra194: smmu: ISO support

The FPGA configuration is encoded in the high byte of
MISCREG_EMU_REVID. Configs GPU and MAX (encoded as
2 and 3) support the ISO SMMU, while BASE (encoded as 1)
does not. This patch implements this encoding and returns
the proper number of SMMU instances.

Change-Id: I024286b6091120c7602f63065d20ce48bcfd13fe
Signed-off-by: Steven Kao <skao@nvidia.com>

plat/nvidia/tegra/include/t194/tegra_def.h

diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 9b6e18e..a9b7271 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -42,10 +42,13 @@
 /*******************************************************************************
  * Tegra Miscellanous register constants
  ******************************************************************************/
-#define TEGRA_MISC_BASE			0x00100000
-#define  HARDWARE_REVISION_OFFSET	0x4
+#define TEGRA_MISC_BASE				0x00100000U
 
-#define  MISCREG_PFCFG			0x200C
+#define HARDWARE_REVISION_OFFSET	0x4U
+#define MISCREG_EMU_REVID			0x3160U
+#define  BOARD_MASK_BITS			0xFFU
+#define  BOARD_SHIFT_BITS			24U
+#define MISCREG_PFCFG				0x200CU
 
 /*******************************************************************************
  * Tegra TSA Controller constants