Tegra194: add macros for security carveout configuration registers
This patch adds macros defining the generalised security carveout
registers. These macros help us program the TZRAM carveout access
and the Video Protect Clear carveout access.
Change-Id: I8f7b24b653fdb702fb57a4097801cb3eae050294
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 6d19839..a1b70db 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -106,6 +106,16 @@
#define TEGRA_MC_STREAMID_BASE 0x02C00000
#define TEGRA_MC_BASE 0x02C10000
+/* General Security Carveout register macros */
+#define MC_GSC_CONFIG_REGS_SIZE 0x40
+#define MC_GSC_LOCK_CFG_SETTINGS_BIT (1 << 1)
+#define MC_GSC_ENABLE_TZ_LOCK_BIT (1 << 0)
+#define MC_GSC_SIZE_RANGE_4KB_SHIFT 27
+#define MC_GSC_BASE_LO_SHIFT 12
+#define MC_GSC_BASE_LO_MASK 0xFFFFF
+#define MC_GSC_BASE_HI_SHIFT 0
+#define MC_GSC_BASE_HI_MASK 3
+
/* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 0x70
#define MC_SECURITY_CFG1_0 0x74
@@ -116,34 +126,22 @@
#define MC_VIDEO_PROTECT_BASE_LO 0x648
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
+/*
+ * Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
+ * non-overlapping Video memory region
+ */
+#define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0
+#define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4
+#define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8
+#define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC
+#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0
+
/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
+#define MC_TZRAM_CARVEOUT_CFG 0x2190
#define MC_TZRAM_BASE_LO 0x2194
-#define TZRAM_BASE_LO_SHIFT 12
-#define TZRAM_BASE_LO_MASK 0xFFFFF
#define MC_TZRAM_BASE_HI 0x2198
-#define TZRAM_BASE_HI_SHIFT 0
-#define TZRAM_BASE_HI_MASK 3
#define MC_TZRAM_SIZE 0x219C
-#define TZRAM_SIZE_RANGE_4KB_SHIFT 27
-
-#define MC_TZRAM_CARVEOUT_CFG 0x2190
-#define TZRAM_LOCK_CFG_SETTINGS_BIT (1 << 1)
-#define TZRAM_ENABLE_TZ_LOCK_BIT (1 << 0)
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG0 0x21A0
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1 0x21A4
-#define TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT (1 << 25)
-#define TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT (1 << 7)
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG2 0x21A8
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG3 0x21AC
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG4 0x21B0
-#define MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG5 0x21B4
-
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS0 0x21C0
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS1 0x21C4
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS2 0x21C8
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS3 0x21CC
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS4 0x21D0
-#define MC_TZRAM_CARVEOUT_FORCE_INTERNAL_ACCESS5 0x21D4
+#define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0
/* Memory Controller Reset Control registers */
#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27)