Tegra194: platform support for memctrl/smmu drivers
This patch adds platform support for the Memory Controller and
SMMU drivers, for the Tegra194 SoC.
Change-Id: Id8b482de70f1f93bedbca8d124575c39b469927f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/include/t194/tegra_def.h b/plat/nvidia/tegra/include/t194/tegra_def.h
index 79d776f..300db81 100644
--- a/plat/nvidia/tegra/include/t194/tegra_def.h
+++ b/plat/nvidia/tegra/include/t194/tegra_def.h
@@ -235,4 +235,141 @@
#define TEGRA_GPU_RESET_REG_OFFSET 0x18UL
#define GPU_RESET_BIT (1UL << 0)
+/*******************************************************************************
+ * Stream ID Override Config registers
+ ******************************************************************************/
+#define MC_STREAMID_OVERRIDE_CFG_ISPFALR 0x228U
+#define MC_STREAMID_OVERRIDE_CFG_AXIAPR 0x410U
+#define MC_STREAMID_OVERRIDE_CFG_AXIAPW 0x418U
+#define MC_STREAMID_OVERRIDE_CFG_MIU0R 0x530U
+#define MC_STREAMID_OVERRIDE_CFG_MIU0W 0x538U
+#define MC_STREAMID_OVERRIDE_CFG_MIU1R 0x540U
+#define MC_STREAMID_OVERRIDE_CFG_MIU1W 0x548U
+#define MC_STREAMID_OVERRIDE_CFG_MIU2R 0x570U
+#define MC_STREAMID_OVERRIDE_CFG_MIU2W 0x578U
+#define MC_STREAMID_OVERRIDE_CFG_MIU3R 0x580U
+#define MC_STREAMID_OVERRIDE_CFG_MIU3W 0x588U
+#define MC_STREAMID_OVERRIDE_CFG_VIFALR 0x5E0U
+#define MC_STREAMID_OVERRIDE_CFG_VIFALW 0x5E8U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA 0x5F0U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0FALRDB 0x5F8U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0WRA 0x600U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0FALWRB 0x608U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA 0x610U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1FALRDB 0x618U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1WRA 0x620U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1FALWRB 0x628U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA 0x630U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB 0x638U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDC 0x640U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0WRA 0x648U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0WRB 0x650U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0WRC 0x658U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA 0x660U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB 0x668U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDC 0x670U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1WRA 0x678U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1WRB 0x680U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1WRC 0x688U
+#define MC_STREAMID_OVERRIDE_CFG_RCER 0x690U
+#define MC_STREAMID_OVERRIDE_CFG_RCEW 0x698U
+#define MC_STREAMID_OVERRIDE_CFG_RCEDMAR 0x6A0U
+#define MC_STREAMID_OVERRIDE_CFG_RCEDMAW 0x6A8U
+#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD 0x6B0U
+#define MC_STREAMID_OVERRIDE_CFG_NVENC1SWR 0x6B8U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE0R 0x6C0U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE0W 0x6C8U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE1R 0x6D0U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE1W 0x6D8U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE2AR 0x6E0U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE2AW 0x6E8U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE3R 0x6F0U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE3W 0x6F8U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE4R 0x700U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE4W 0x708U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE5R 0x710U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE5W 0x718U
+#define MC_STREAMID_OVERRIDE_CFG_ISPFALW 0x720U
+#define MC_STREAMID_OVERRIDE_CFG_DLA0RDA1 0x748U
+#define MC_STREAMID_OVERRIDE_CFG_DLA1RDA1 0x750U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDA1 0x758U
+#define MC_STREAMID_OVERRIDE_CFG_PVA0RDB1 0x760U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDA1 0x768U
+#define MC_STREAMID_OVERRIDE_CFG_PVA1RDB1 0x770U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE5R1 0x778U
+#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD1 0x780U
+#define MC_STREAMID_OVERRIDE_CFG_NVENC1SRD1 0x788U
+#define MC_STREAMID_OVERRIDE_CFG_ISPRA1 0x790U
+#define MC_STREAMID_OVERRIDE_CFG_PCIE0R1 0x798U
+#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD 0x7C8U
+#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SRD1 0x7D0U
+#define MC_STREAMID_OVERRIDE_CFG_NVDEC1SWR 0x7D8U
+
+/*******************************************************************************
+ * Memory Controller transaction override config registers
+ ******************************************************************************/
+#define MC_TXN_OVERRIDE_CONFIG_MIU0R 0x1530
+#define MC_TXN_OVERRIDE_CONFIG_MIU0W 0x1538
+#define MC_TXN_OVERRIDE_CONFIG_MIU1R 0x1540
+#define MC_TXN_OVERRIDE_CONFIG_MIU1W 0x1548
+#define MC_TXN_OVERRIDE_CONFIG_MIU2R 0x1570
+#define MC_TXN_OVERRIDE_CONFIG_MIU2W 0x1578
+#define MC_TXN_OVERRIDE_CONFIG_MIU3R 0x1580
+#define MC_TXN_OVERRIDE_CONFIG_MIU3W 0x158C
+#define MC_TXN_OVERRIDE_CONFIG_VIFALR 0x15E4
+#define MC_TXN_OVERRIDE_CONFIG_VIFALW 0x15EC
+#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA 0x15F4
+#define MC_TXN_OVERRIDE_CONFIG_DLA0FALRDB 0x15FC
+#define MC_TXN_OVERRIDE_CONFIG_DLA0WRA 0x1604
+#define MC_TXN_OVERRIDE_CONFIG_DLA0FALWRB 0x160C
+#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA 0x1614
+#define MC_TXN_OVERRIDE_CONFIG_DLA1FALRDB 0x161C
+#define MC_TXN_OVERRIDE_CONFIG_DLA1WRA 0x1624
+#define MC_TXN_OVERRIDE_CONFIG_DLA1FALWRB 0x162C
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA 0x1634
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB 0x163C
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDC 0x1644
+#define MC_TXN_OVERRIDE_CONFIG_PVA0WRA 0x164C
+#define MC_TXN_OVERRIDE_CONFIG_PVA0WRB 0x1654
+#define MC_TXN_OVERRIDE_CONFIG_PVA0WRC 0x165C
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA 0x1664
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB 0x166C
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDC 0x1674
+#define MC_TXN_OVERRIDE_CONFIG_PVA1WRA 0x167C
+#define MC_TXN_OVERRIDE_CONFIG_PVA1WRB 0x1684
+#define MC_TXN_OVERRIDE_CONFIG_PVA1WRC 0x168C
+#define MC_TXN_OVERRIDE_CONFIG_RCER 0x1694
+#define MC_TXN_OVERRIDE_CONFIG_RCEW 0x169C
+#define MC_TXN_OVERRIDE_CONFIG_RCEDMAR 0x16A4
+#define MC_TXN_OVERRIDE_CONFIG_RCEDMAW 0x16AC
+#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD 0x16B4
+#define MC_TXN_OVERRIDE_CONFIG_NVENC1SWR 0x16BC
+#define MC_TXN_OVERRIDE_CONFIG_PCIE0R 0x16C4
+#define MC_TXN_OVERRIDE_CONFIG_PCIE0W 0x16CC
+#define MC_TXN_OVERRIDE_CONFIG_PCIE1R 0x16D4
+#define MC_TXN_OVERRIDE_CONFIG_PCIE1W 0x16DC
+#define MC_TXN_OVERRIDE_CONFIG_PCIE2AR 0x16E4
+#define MC_TXN_OVERRIDE_CONFIG_PCIE2AW 0x16EC
+#define MC_TXN_OVERRIDE_CONFIG_PCIE3R 0x16F4
+#define MC_TXN_OVERRIDE_CONFIG_PCIE3W 0x16FC
+#define MC_TXN_OVERRIDE_CONFIG_PCIE4R 0x1704
+#define MC_TXN_OVERRIDE_CONFIG_PCIE4W 0x170C
+#define MC_TXN_OVERRIDE_CONFIG_PCIE5R 0x1714
+#define MC_TXN_OVERRIDE_CONFIG_PCIE5W 0x171C
+#define MC_TXN_OVERRIDE_CONFIG_ISPFALW 0x1724
+#define MC_TXN_OVERRIDE_CONFIG_DLA0RDA1 0x174C
+#define MC_TXN_OVERRIDE_CONFIG_DLA1RDA1 0x1754
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDA1 0x175C
+#define MC_TXN_OVERRIDE_CONFIG_PVA0RDB1 0x1764
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDA1 0x176C
+#define MC_TXN_OVERRIDE_CONFIG_PVA1RDB1 0x1774
+#define MC_TXN_OVERRIDE_CONFIG_PCIE5R1 0x177C
+#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD1 0x1784
+#define MC_TXN_OVERRIDE_CONFIG_NVENC1SRD1 0x178C
+#define MC_TXN_OVERRIDE_CONFIG_ISPRA1 0x1794
+#define MC_TXN_OVERRIDE_CONFIG_PCIE0R1 0x179C
+#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD 0x17CC
+#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SRD1 0x17D4
+#define MC_TXN_OVERRIDE_CONFIG_NVDEC1SWR 0x17DC
+
#endif /* __TEGRA_DEF_H__ */