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Soren Brinkmann76fcae32016-03-06 20:16:27 -08001/*
Rajan Vaja0ac2be12018-01-17 02:39:21 -08002 * Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
Soren Brinkmann76fcae32016-03-06 20:16:27 -08003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Soren Brinkmann76fcae32016-03-06 20:16:27 -08005 */
6
7#ifndef __ZYNQMP_DEF_H__
8#define __ZYNQMP_DEF_H__
9
10#include <common_def.h>
11
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -070012#define ZYNQMP_CONSOLE_ID_cadence 1
13#define ZYNQMP_CONSOLE_ID_cadence0 1
14#define ZYNQMP_CONSOLE_ID_cadence1 2
15#define ZYNQMP_CONSOLE_ID_dcc 3
16
17#define ZYNQMP_CONSOLE_IS(con) (ZYNQMP_CONSOLE_ID_ ## con == ZYNQMP_CONSOLE)
18
Soren Brinkmann76fcae32016-03-06 20:16:27 -080019/* Firmware Image Package */
20#define ZYNQMP_PRIMARY_CPU 0
21
22/* Memory location options for Shared data and TSP in ZYNQMP */
23#define ZYNQMP_IN_TRUSTED_SRAM 0
24#define ZYNQMP_IN_TRUSTED_DRAM 1
25
26/*******************************************************************************
27 * ZYNQMP memory map related constants
28 ******************************************************************************/
Soren Brinkmann76fcae32016-03-06 20:16:27 -080029/* Aggregate of all devices in the first GB */
Jolly Shah69fb5bf2018-02-07 16:25:41 -080030#define DEVICE0_BASE U(0xFF000000)
31#define DEVICE0_SIZE U(0x00E00000)
32#define DEVICE1_BASE U(0xF9000000)
33#define DEVICE1_SIZE U(0x00800000)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080034
35/* For cpu reset APU space here too 0xFE5F1000 CRF_APB*/
Jolly Shah69fb5bf2018-02-07 16:25:41 -080036#define CRF_APB_BASE U(0xFD1A0000)
37#define CRF_APB_SIZE U(0x00600000)
38#define CRF_APB_CLK_BASE U(0xFD1A0020)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080039
40/* CRF registers and bitfields */
41#define CRF_APB_RST_FPD_APU (CRF_APB_BASE + 0X00000104)
42
Jolly Shah69fb5bf2018-02-07 16:25:41 -080043#define CRF_APB_RST_FPD_APU_ACPU_RESET (U(1) << 0)
44#define CRF_APB_RST_FPD_APU_ACPU_PWRON_RESET (U(1) << 10)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080045
46/* CRL registers and bitfields */
Jolly Shah69fb5bf2018-02-07 16:25:41 -080047#define CRL_APB_BASE U(0xFF5E0000)
Soren Brinkmannb43d9432016-04-18 11:49:42 -070048#define CRL_APB_BOOT_MODE_USER (CRL_APB_BASE + 0x200)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080049#define CRL_APB_RESET_CTRL (CRL_APB_BASE + 0x218)
Rajan Vaja5529a012018-01-17 02:39:23 -080050#define CRL_APB_RST_LPD_TOP (CRL_APB_BASE + 0x23C)
Siva Durga Prasad Paladugued1d5cb2018-09-04 17:03:25 +053051#define CRL_APB_BOOT_PIN_CTRL (CRL_APB_BASE + U(0x250))
Jolly Shah69fb5bf2018-02-07 16:25:41 -080052#define CRL_APB_CLK_BASE U(0xFF5E0020)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080053
Jolly Shah69fb5bf2018-02-07 16:25:41 -080054#define CRL_APB_RPU_AMBA_RESET (U(1) << 2)
55#define CRL_APB_RPLL_CTRL_BYPASS (U(1) << 3)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080056
Jolly Shah69fb5bf2018-02-07 16:25:41 -080057#define CRL_APB_RESET_CTRL_SOFT_RESET (U(1) << 4)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080058
Jolly Shah69fb5bf2018-02-07 16:25:41 -080059#define CRL_APB_BOOT_MODE_MASK (U(0xf) << 0)
Siva Durga Prasad Paladugued1d5cb2018-09-04 17:03:25 +053060#define CRL_APB_BOOT_PIN_MASK (U(0xf0f) << 0)
61#define CRL_APB_BOOT_DRIVE_PIN_1_SHIFT U(9)
62#define CRL_APB_BOOT_ENABLE_PIN_1_SHIFT U(1)
63#define CRL_APB_BOOT_ENABLE_PIN_1 (U(0x1) << CRL_APB_BOOT_ENABLE_PIN_1_SHIFT)
64#define CRL_APB_BOOT_DRIVE_PIN_1 (U(0x1) << CRL_APB_BOOT_DRIVE_PIN_1_SHIFT)
Jolly Shah69fb5bf2018-02-07 16:25:41 -080065#define ZYNQMP_BOOTMODE_JTAG U(0)
Siva Durga Prasad Paladugued1d5cb2018-09-04 17:03:25 +053066#define ZYNQMP_ULPI_RESET_VAL_HIGH (CRL_APB_BOOT_ENABLE_PIN_1 | \
67 CRL_APB_BOOT_DRIVE_PIN_1)
68#define ZYNQMP_ULPI_RESET_VAL_LOW CRL_APB_BOOT_ENABLE_PIN_1
Soren Brinkmannb43d9432016-04-18 11:49:42 -070069
Soren Brinkmann76fcae32016-03-06 20:16:27 -080070/* system counter registers and bitfields */
71#define IOU_SCNTRS_BASE 0xFF260000
Soren Brinkmann76fcae32016-03-06 20:16:27 -080072#define IOU_SCNTRS_BASEFREQ (IOU_SCNTRS_BASE + 0x20)
73
Soren Brinkmann76fcae32016-03-06 20:16:27 -080074/* APU registers and bitfields */
75#define APU_BASE 0xFD5C0000
76#define APU_CONFIG_0 (APU_BASE + 0x20)
77#define APU_RVBAR_L_0 (APU_BASE + 0x40)
78#define APU_RVBAR_H_0 (APU_BASE + 0x44)
79#define APU_PWRCTL (APU_BASE + 0x90)
80
81#define APU_CONFIG_0_VINITHI_SHIFT 8
82#define APU_0_PWRCTL_CPUPWRDWNREQ_MASK 1
83#define APU_1_PWRCTL_CPUPWRDWNREQ_MASK 2
84#define APU_2_PWRCTL_CPUPWRDWNREQ_MASK 4
85#define APU_3_PWRCTL_CPUPWRDWNREQ_MASK 8
86
87/* PMU registers and bitfields */
88#define PMU_GLOBAL_BASE 0xFFD80000
89#define PMU_GLOBAL_CNTRL (PMU_GLOBAL_BASE + 0)
Michal Simekef8f5592015-06-15 14:22:50 +020090#define PMU_GLOBAL_GEN_STORAGE6 (PMU_GLOBAL_BASE + 0x48)
Soren Brinkmann76fcae32016-03-06 20:16:27 -080091#define PMU_GLOBAL_REQ_PWRUP_STATUS (PMU_GLOBAL_BASE + 0x110)
92#define PMU_GLOBAL_REQ_PWRUP_EN (PMU_GLOBAL_BASE + 0x118)
93#define PMU_GLOBAL_REQ_PWRUP_DIS (PMU_GLOBAL_BASE + 0x11c)
94#define PMU_GLOBAL_REQ_PWRUP_TRIG (PMU_GLOBAL_BASE + 0x120)
95
96#define PMU_GLOBAL_CNTRL_FW_IS_PRESENT (1 << 4)
97
Soren Brinkmann76fcae32016-03-06 20:16:27 -080098/*******************************************************************************
99 * CCI-400 related constants
100 ******************************************************************************/
101#define PLAT_ARM_CCI_BASE 0xFD6E0000
102#define PLAT_ARM_CCI_CLUSTER0_SL_IFACE_IX 3
103#define PLAT_ARM_CCI_CLUSTER1_SL_IFACE_IX 4
104
105/*******************************************************************************
106 * GIC-400 & interrupt handling related constants
107 ******************************************************************************/
108#define BASE_GICD_BASE 0xF9010000
109#define BASE_GICC_BASE 0xF9020000
110#define BASE_GICH_BASE 0xF9040000
111#define BASE_GICV_BASE 0xF9060000
112
Siva Durga Prasad Paladuguefd431b2018-04-30 20:12:12 +0530113#if ZYNQMP_WDT_RESTART
114#define IRQ_SEC_IPI_APU 67
115#define IRQ_TTC3_1 77
116#define TTC3_BASE_ADDR 0xFF140000
117#define TTC3_INTR_REGISTER_1 (TTC3_BASE_ADDR + 0x54)
118#define TTC3_INTR_ENABLE_1 (TTC3_BASE_ADDR + 0x60)
119#endif
120
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800121#define ARM_IRQ_SEC_PHY_TIMER 29
122
123#define ARM_IRQ_SEC_SGI_0 8
124#define ARM_IRQ_SEC_SGI_1 9
125#define ARM_IRQ_SEC_SGI_2 10
126#define ARM_IRQ_SEC_SGI_3 11
127#define ARM_IRQ_SEC_SGI_4 12
128#define ARM_IRQ_SEC_SGI_5 13
129#define ARM_IRQ_SEC_SGI_6 14
130#define ARM_IRQ_SEC_SGI_7 15
131
132#define MAX_INTR_EL3 128
133
134/*******************************************************************************
135 * UART related constants
136 ******************************************************************************/
137#define ZYNQMP_UART0_BASE 0xFF000000
Soren Brinkmann836418d2016-05-27 08:56:53 -0700138#define ZYNQMP_UART1_BASE 0xFF010000
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800139
Soren Brinkmann99c0d7b2016-06-10 09:57:14 -0700140#if ZYNQMP_CONSOLE_IS(cadence)
141# define ZYNQMP_UART_BASE ZYNQMP_UART0_BASE
142#elif ZYNQMP_CONSOLE_IS(cadence1)
143# define ZYNQMP_UART_BASE ZYNQMP_UART1_BASE
144#else
145# error "invalid ZYNQMP_CONSOLE"
146#endif
147
148#define PLAT_ARM_CRASH_UART_BASE ZYNQMP_UART_BASE
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800149/* impossible to call C routine how it is done now - hardcode any value */
150#define PLAT_ARM_CRASH_UART_CLK_IN_HZ 100000000 /* FIXME */
151
152/* Must be non zero */
153#define ZYNQMP_UART_BAUDRATE 115200
154#define ARM_CONSOLE_BAUDRATE ZYNQMP_UART_BAUDRATE
155
156/* Silicon version detection */
157#define ZYNQMP_SILICON_VER_MASK 0xF000
158#define ZYNQMP_SILICON_VER_SHIFT 12
159#define ZYNQMP_CSU_VERSION_SILICON 0
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800160#define ZYNQMP_CSU_VERSION_QEMU 3
161
162#define ZYNQMP_RTL_VER_MASK 0xFF0
163#define ZYNQMP_RTL_VER_SHIFT 4
164
165#define ZYNQMP_PS_VER_MASK 0xF
166#define ZYNQMP_PS_VER_SHIFT 0
167
168#define ZYNQMP_CSU_BASEADDR 0xFFCA0000
169#define ZYNQMP_CSU_IDCODE_OFFSET 0x40
170
171#define ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT 0
172#define ZYNQMP_CSU_IDCODE_XILINX_ID_MASK (0xFFF << ZYNQMP_CSU_IDCODE_XILINX_ID_SHIFT)
173#define ZYNQMP_CSU_IDCODE_XILINX_ID 0x093
174
175#define ZYNQMP_CSU_IDCODE_SVD_SHIFT 12
Siva Durga Prasad Paladugub982d162017-08-01 10:23:19 +0530176#define ZYNQMP_CSU_IDCODE_SVD_MASK (0x7 << \
177 ZYNQMP_CSU_IDCODE_SVD_SHIFT)
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800178#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT 15
179#define ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK (0xF << ZYNQMP_CSU_IDCODE_DEVICE_CODE_SHIFT)
180#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT 19
181#define ZYNQMP_CSU_IDCODE_SUB_FAMILY_MASK (0x3 << ZYNQMP_CSU_IDCODE_SUB_FAMILY_SHIFT)
182#define ZYNQMP_CSU_IDCODE_FAMILY_SHIFT 21
183#define ZYNQMP_CSU_IDCODE_FAMILY_MASK (0x7F << ZYNQMP_CSU_IDCODE_FAMILY_SHIFT)
184#define ZYNQMP_CSU_IDCODE_FAMILY 0x23
185
186#define ZYNQMP_CSU_IDCODE_REVISION_SHIFT 28
187#define ZYNQMP_CSU_IDCODE_REVISION_MASK (0xF << ZYNQMP_CSU_IDCODE_REVISION_SHIFT)
188#define ZYNQMP_CSU_IDCODE_REVISION 0
189
190#define ZYNQMP_CSU_VERSION_OFFSET 0x44
191
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530192/* Efuse */
193#define EFUSE_BASEADDR 0xFFCC0000
194#define EFUSE_IPDISABLE_OFFSET 0x1018
195#define EFUSE_IPDISABLE_VERSION 0x1FFU
Siva Durga Prasad Paladugub76656d2018-03-05 18:47:15 +0530196#define ZYNQMP_EFUSE_IPDISABLE_SHIFT 20
Siva Durga Prasad Paladugu83e37252018-05-01 11:10:25 +0530197
Naga Sureshkumar Rellicf4e7142016-07-01 12:46:43 +0530198/* Access control register defines */
199#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
200#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
201
Siva Durga Prasad Paladugu90539cd2018-09-04 17:33:19 +0530202#define FPD_SLCR_BASEADDR U(0xFD610000)
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800203#define IOU_SLCR_BASEADDR U(0xFF180000)
Rajan Vaja0ac2be12018-01-17 02:39:21 -0800204
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800205#define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000)
206#define ZYNQMP_RPU0_CFG U(0xFF9A0100)
207#define ZYNQMP_RPU1_CFG U(0xFF9A0200)
208#define ZYNQMP_SLSPLIT_MASK U(0x08)
209#define ZYNQMP_TCM_COMB_MASK U(0x40)
210#define ZYNQMP_SLCLAMP_MASK U(0x10)
211#define ZYNQMP_VINITHI_MASK U(0x04)
Rajan Vaja5529a012018-01-17 02:39:23 -0800212
Rajan Vajaaea41bb2018-01-17 02:39:24 -0800213/* Tap delay bypass */
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800214#define IOU_TAPDLY_BYPASS U(0XFF180390)
215#define TAP_DELAY_MASK U(0x7)
Rajan Vajaaea41bb2018-01-17 02:39:24 -0800216
217/* SGMII mode */
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800218#define IOU_GEM_CTRL U(0xFF180360)
219#define IOU_GEM_CLK_CTRL U(0xFF180308)
220#define SGMII_SD_MASK U(0x3)
221#define SGMII_SD_OFFSET U(2)
222#define SGMII_PCS_SD_0 U(0x0)
223#define SGMII_PCS_SD_1 U(0x1)
224#define SGMII_PCS_SD_PHY U(0x2)
225#define GEM_SGMII_MASK U(0x4)
226#define GEM_CLK_CTRL_MASK U(0xF)
227#define GEM_CLK_CTRL_OFFSET U(5)
228#define GEM_RX_SRC_SEL_GTR U(0x1)
229#define GEM_SGMII_MODE U(0x4)
Rajan Vajaaea41bb2018-01-17 02:39:24 -0800230
231/* SD DLL reset */
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800232#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
233#define ZYNQMP_SD0_DLL_RST_MASK U(0x00000004)
234#define ZYNQMP_SD0_DLL_RST U(0x00000004)
235#define ZYNQMP_SD1_DLL_RST_MASK U(0x00040000)
236#define ZYNQMP_SD1_DLL_RST U(0x00040000)
Rajan Vajaaea41bb2018-01-17 02:39:24 -0800237
238/* SD tap delay */
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800239#define ZYNQMP_SD_DLL_CTRL U(0xFF180358)
240#define ZYNQMP_SD_ITAP_DLY U(0xFF180314)
241#define ZYNQMP_SD_OTAP_DLY U(0xFF180318)
242#define ZYNQMP_SD_TAP_OFFSET U(16)
243#define ZYNQMP_SD_ITAPCHGWIN_MASK U(0x200)
244#define ZYNQMP_SD_ITAPCHGWIN U(0x200)
245#define ZYNQMP_SD_ITAPDLYENA_MASK U(0x100)
246#define ZYNQMP_SD_ITAPDLYENA U(0x100)
247#define ZYNQMP_SD_ITAPDLYSEL_MASK U(0xFF)
248#define ZYNQMP_SD_OTAPDLYSEL_MASK U(0x3F)
249#define ZYNQMP_SD_OTAPDLYENA_MASK U(0x40)
250#define ZYNQMP_SD_OTAPDLYENA U(0x40)
Rajan Vajaaea41bb2018-01-17 02:39:24 -0800251
Rajan Vajad98455b2018-01-17 02:39:26 -0800252/* Clock control registers */
253/* Full power domain clocks */
254#define CRF_APB_APLL_CTRL (CRF_APB_CLK_BASE + 0x00)
255#define CRF_APB_DPLL_CTRL (CRF_APB_CLK_BASE + 0x0c)
256#define CRF_APB_VPLL_CTRL (CRF_APB_CLK_BASE + 0x18)
257#define CRF_APB_PLL_STATUS (CRF_APB_CLK_BASE + 0x24)
258#define CRF_APB_APLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x28)
259#define CRF_APB_DPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x2c)
260#define CRF_APB_VPLL_TO_LPD_CTRL (CRF_APB_CLK_BASE + 0x30)
261/* Peripheral clocks */
262#define CRF_APB_ACPU_CTRL (CRF_APB_CLK_BASE + 0x40)
263#define CRF_APB_DBG_TRACE_CTRL (CRF_APB_CLK_BASE + 0x44)
264#define CRF_APB_DBG_FPD_CTRL (CRF_APB_CLK_BASE + 0x48)
265#define CRF_APB_DP_VIDEO_REF_CTRL (CRF_APB_CLK_BASE + 0x50)
266#define CRF_APB_DP_AUDIO_REF_CTRL (CRF_APB_CLK_BASE + 0x54)
267#define CRF_APB_DP_STC_REF_CTRL (CRF_APB_CLK_BASE + 0x5c)
268#define CRF_APB_DDR_CTRL (CRF_APB_CLK_BASE + 0x60)
269#define CRF_APB_GPU_REF_CTRL (CRF_APB_CLK_BASE + 0x64)
270#define CRF_APB_SATA_REF_CTRL (CRF_APB_CLK_BASE + 0x80)
271#define CRF_APB_PCIE_REF_CTRL (CRF_APB_CLK_BASE + 0x94)
272#define CRF_APB_GDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x98)
273#define CRF_APB_DPDMA_REF_CTRL (CRF_APB_CLK_BASE + 0x9c)
274#define CRF_APB_TOPSW_MAIN_CTRL (CRF_APB_CLK_BASE + 0xa0)
275#define CRF_APB_TOPSW_LSBUS_CTRL (CRF_APB_CLK_BASE + 0xa4)
276#define CRF_APB_GTGREF0_REF_CTRL (CRF_APB_CLK_BASE + 0xa8)
277#define CRF_APB_DBG_TSTMP_CTRL (CRF_APB_CLK_BASE + 0xd8)
278
279/* Low power domain clocks */
280#define CRL_APB_IOPLL_CTRL (CRL_APB_CLK_BASE + 0x00)
281#define CRL_APB_RPLL_CTRL (CRL_APB_CLK_BASE + 0x10)
282#define CRL_APB_PLL_STATUS (CRL_APB_CLK_BASE + 0x20)
283#define CRL_APB_IOPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x24)
284#define CRL_APB_RPLL_TO_FPD_CTRL (CRL_APB_CLK_BASE + 0x28)
285/* Peripheral clocks */
286#define CRL_APB_USB3_DUAL_REF_CTRL (CRL_APB_CLK_BASE + 0x2c)
287#define CRL_APB_GEM0_REF_CTRL (CRL_APB_CLK_BASE + 0x30)
288#define CRL_APB_GEM1_REF_CTRL (CRL_APB_CLK_BASE + 0x34)
289#define CRL_APB_GEM2_REF_CTRL (CRL_APB_CLK_BASE + 0x38)
290#define CRL_APB_GEM3_REF_CTRL (CRL_APB_CLK_BASE + 0x3c)
291#define CRL_APB_USB0_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x40)
292#define CRL_APB_USB1_BUS_REF_CTRL (CRL_APB_CLK_BASE + 0x44)
293#define CRL_APB_QSPI_REF_CTRL (CRL_APB_CLK_BASE + 0x48)
294#define CRL_APB_SDIO0_REF_CTRL (CRL_APB_CLK_BASE + 0x4c)
295#define CRL_APB_SDIO1_REF_CTRL (CRL_APB_CLK_BASE + 0x50)
296#define CRL_APB_UART0_REF_CTRL (CRL_APB_CLK_BASE + 0x54)
297#define CRL_APB_UART1_REF_CTRL (CRL_APB_CLK_BASE + 0x58)
298#define CRL_APB_SPI0_REF_CTRL (CRL_APB_CLK_BASE + 0x5c)
299#define CRL_APB_SPI1_REF_CTRL (CRL_APB_CLK_BASE + 0x60)
300#define CRL_APB_CAN0_REF_CTRL (CRL_APB_CLK_BASE + 0x64)
301#define CRL_APB_CAN1_REF_CTRL (CRL_APB_CLK_BASE + 0x68)
302#define CRL_APB_CPU_R5_CTRL (CRL_APB_CLK_BASE + 0x70)
303#define CRL_APB_IOU_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x7c)
304#define CRL_APB_CSU_PLL_CTRL (CRL_APB_CLK_BASE + 0x80)
305#define CRL_APB_PCAP_CTRL (CRL_APB_CLK_BASE + 0x84)
306#define CRL_APB_LPD_SWITCH_CTRL (CRL_APB_CLK_BASE + 0x88)
307#define CRL_APB_LPD_LSBUS_CTRL (CRL_APB_CLK_BASE + 0x8c)
308#define CRL_APB_DBG_LPD_CTRL (CRL_APB_CLK_BASE + 0x90)
309#define CRL_APB_NAND_REF_CTRL (CRL_APB_CLK_BASE + 0x94)
310#define CRL_APB_ADMA_REF_CTRL (CRL_APB_CLK_BASE + 0x98)
311#define CRL_APB_PL0_REF_CTRL (CRL_APB_CLK_BASE + 0xa0)
312#define CRL_APB_PL1_REF_CTRL (CRL_APB_CLK_BASE + 0xa4)
313#define CRL_APB_PL2_REF_CTRL (CRL_APB_CLK_BASE + 0xa8)
314#define CRL_APB_PL3_REF_CTRL (CRL_APB_CLK_BASE + 0xac)
315#define CRL_APB_PL0_THR_CNT (CRL_APB_CLK_BASE + 0xb4)
316#define CRL_APB_PL1_THR_CNT (CRL_APB_CLK_BASE + 0xbc)
317#define CRL_APB_PL2_THR_CNT (CRL_APB_CLK_BASE + 0xc4)
318#define CRL_APB_PL3_THR_CNT (CRL_APB_CLK_BASE + 0xdc)
319#define CRL_APB_GEM_TSU_REF_CTRL (CRL_APB_CLK_BASE + 0xe0)
320#define CRL_APB_DLL_REF_CTRL (CRL_APB_CLK_BASE + 0xe4)
321#define CRL_APB_AMS_REF_CTRL (CRL_APB_CLK_BASE + 0xe8)
322#define CRL_APB_I2C0_REF_CTRL (CRL_APB_CLK_BASE + 0x100)
323#define CRL_APB_I2C1_REF_CTRL (CRL_APB_CLK_BASE + 0x104)
324#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108)
325#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
326#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
Siva Durga Prasad Paladugu90539cd2018-09-04 17:33:19 +0530327#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100)
Rajan Vajad98455b2018-01-17 02:39:26 -0800328
Rajan Vaja393c0a22018-01-17 02:39:27 -0800329/* Global general storage register base address */
330#define GGS_BASEADDR (0xFFD80030U)
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800331#define GGS_NUM_REGS U(4)
Rajan Vaja393c0a22018-01-17 02:39:27 -0800332
333/* Persistent global general storage register base address */
334#define PGGS_BASEADDR (0xFFD80050U)
Jolly Shah69fb5bf2018-02-07 16:25:41 -0800335#define PGGS_NUM_REGS U(4)
Rajan Vaja393c0a22018-01-17 02:39:27 -0800336
Siva Durga Prasad Paladuguac8526f2018-09-04 17:12:51 +0530337/* Warm restart boot health status register and mask */
338#define PM_BOOT_HEALTH_STATUS_REG (GGS_BASEADDR + U(0x10))
339#define PM_BOOT_HEALTH_STATUS_MASK U(0x01)
340
Siva Durga Prasad Paladugua22b8852018-09-04 17:27:12 +0530341/*AFI registers */
342#define AFIFM6_WRCTRL U(13)
343#define FABRIC_WIDTH U(3)
344
Soren Brinkmann76fcae32016-03-06 20:16:27 -0800345#endif /* __ZYNQMP_DEF_H__ */