developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020 MediaTek Inc. |
| 3 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 17 | #include <dt-bindings/phy/phy.h> |
| 18 | #include <dt-bindings/reset/ti-syscon.h> |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 19 | #include <dt-bindings/clock/mt7986-clk.h> |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 20 | #include <dt-bindings/thermal/thermal.h> |
developer | 7f4cdcd | 2021-08-03 19:29:43 +0800 | [diff] [blame] | 21 | #include <dt-bindings/pinctrl/mt65xx.h> |
developer | e138bcd | 2021-12-06 09:20:47 +0800 | [diff] [blame] | 22 | #include <dt-bindings/reset/mt7986-resets.h> |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 23 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 24 | / { |
| 25 | compatible = "mediatek,mt7986a-rfb"; |
| 26 | interrupt-parent = <&gic>; |
| 27 | #address-cells = <2>; |
| 28 | #size-cells = <2>; |
| 29 | cpus { |
| 30 | #address-cells = <1>; |
| 31 | #size-cells = <0>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 32 | cpu0: cpu@0 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 33 | device_type = "cpu"; |
| 34 | compatible = "arm,cortex-a53"; |
| 35 | enable-method = "psci"; |
| 36 | reg = <0x0>; |
| 37 | }; |
| 38 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 39 | cpu1: cpu@1 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 40 | device_type = "cpu"; |
| 41 | compatible = "arm,cortex-a53"; |
| 42 | enable-method = "psci"; |
| 43 | reg = <0x1>; |
| 44 | }; |
| 45 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 46 | cpu2: cpu@2 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 47 | device_type = "cpu"; |
| 48 | compatible = "arm,cortex-a53"; |
| 49 | enable-method = "psci"; |
| 50 | reg = <0x2>; |
| 51 | }; |
| 52 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 53 | cpu3: cpu@3 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 54 | device_type = "cpu"; |
| 55 | enable-method = "psci"; |
| 56 | compatible = "arm,cortex-a53"; |
| 57 | reg = <0x3>; |
| 58 | }; |
| 59 | }; |
| 60 | |
| 61 | wed: wed@15010000 { |
| 62 | compatible = "mediatek,wed"; |
| 63 | wed_num = <2>; |
| 64 | /* add this property for wed get the pci slot number. */ |
| 65 | pci_slot_map = <0>, <1>; |
| 66 | reg = <0 0x15010000 0 0x1000>, |
| 67 | <0 0x15011000 0 0x1000>; |
| 68 | interrupt-parent = <&gic>; |
| 69 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 70 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 71 | }; |
| 72 | |
| 73 | wed2: wed2@15011000 { |
| 74 | compatible = "mediatek,wed2"; |
| 75 | wed_num = <2>; |
| 76 | reg = <0 0x15010000 0 0x1000>, |
| 77 | <0 0x15011000 0 0x1000>; |
| 78 | interrupt-parent = <&gic>; |
| 79 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 80 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 81 | }; |
| 82 | |
| 83 | wdma: wdma@15104800 { |
| 84 | compatible = "mediatek,wed-wdma"; |
| 85 | reg = <0 0x15104800 0 0x400>, |
| 86 | <0 0x15104c00 0 0x400>; |
| 87 | }; |
| 88 | |
| 89 | ap2woccif: ap2woccif@151A5000 { |
| 90 | compatible = "mediatek,ap2woccif"; |
| 91 | reg = <0 0x151A5000 0 0x1000>, |
| 92 | <0 0x151AD000 0 0x1000>; |
| 93 | interrupt-parent = <&gic>; |
| 94 | interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
| 95 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; |
| 96 | }; |
| 97 | |
| 98 | wocpu0_ilm: wocpu0_ilm@151E0000 { |
| 99 | compatible = "mediatek,wocpu0_ilm"; |
| 100 | reg = <0 0x151E0000 0 0x8000>; |
| 101 | }; |
| 102 | |
| 103 | wocpu1_ilm: wocpu1_ilm@151F0000 { |
| 104 | compatible = "mediatek,wocpu1_ilm"; |
| 105 | reg = <0 0x151F0000 0 0x8000>; |
| 106 | }; |
| 107 | |
| 108 | wocpu_dlm: wocpu_dlm@151E8000 { |
| 109 | compatible = "mediatek,wocpu_dlm"; |
| 110 | reg = <0 0x151E8000 0 0x2000>, |
| 111 | <0 0x151F8000 0 0x2000>; |
| 112 | |
| 113 | resets = <ðsysrst 0>; |
| 114 | reset-names = "wocpu_rst"; |
| 115 | }; |
| 116 | |
| 117 | cpu_boot: wocpu_boot@15194000 { |
| 118 | compatible = "mediatek,wocpu_boot"; |
| 119 | reg = <0 0x15194000 0 0x1000>; |
| 120 | }; |
| 121 | |
| 122 | reserved-memory { |
| 123 | #address-cells = <2>; |
| 124 | #size-cells = <2>; |
| 125 | ranges; |
| 126 | |
| 127 | /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ |
| 128 | secmon_reserved: secmon@43000000 { |
| 129 | reg = <0 0x43000000 0 0x30000>; |
| 130 | no-map; |
| 131 | }; |
| 132 | |
| 133 | wmcpu_emi: wmcpu-reserved@4FC00000 { |
| 134 | compatible = "mediatek,wmcpu-reserved"; |
| 135 | no-map; |
| 136 | reg = <0 0x4FC00000 0 0x00100000>; |
| 137 | }; |
| 138 | |
| 139 | wocpu0_emi: wocpu0_emi@4FD00000 { |
| 140 | compatible = "mediatek,wocpu0_emi"; |
| 141 | no-map; |
| 142 | reg = <0 0x4FD00000 0 0x40000>; |
| 143 | shared = <0>; |
| 144 | }; |
| 145 | |
developer | 86423f0 | 2021-10-12 15:20:50 +0800 | [diff] [blame] | 146 | wocpu1_emi: wocpu1_emi@4FD40000 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 147 | compatible = "mediatek,wocpu1_emi"; |
| 148 | no-map; |
| 149 | reg = <0 0x4FD40000 0 0x40000>; |
| 150 | shared = <0>; |
| 151 | }; |
| 152 | |
developer | 86423f0 | 2021-10-12 15:20:50 +0800 | [diff] [blame] | 153 | wocpu_data: wocpu_data@4FD80000 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 154 | compatible = "mediatek,wocpu_data"; |
| 155 | no-map; |
developer | 8be272e | 2021-07-29 13:15:07 +0800 | [diff] [blame] | 156 | reg = <0 0x4FD80000 0 0x240000>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 157 | shared = <1>; |
| 158 | }; |
| 159 | }; |
| 160 | |
| 161 | psci { |
| 162 | compatible = "arm,psci-0.2"; |
| 163 | method = "smc"; |
| 164 | }; |
| 165 | |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 166 | clk40m: oscillator@0 { |
| 167 | compatible = "fixed-clock"; |
| 168 | #clock-cells = <0>; |
| 169 | clock-frequency = <40000000>; |
| 170 | clock-output-names = "clkxtal"; |
| 171 | }; |
| 172 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 173 | system_clk: dummy_system_clk { |
| 174 | compatible = "fixed-clock"; |
| 175 | clock-frequency = <40000000>; |
| 176 | #clock-cells = <0>; |
| 177 | }; |
| 178 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 179 | timer { |
| 180 | compatible = "arm,armv8-timer"; |
| 181 | interrupt-parent = <&gic>; |
developer | f39022a | 2021-05-06 13:31:52 +0800 | [diff] [blame] | 182 | clock-frequency = <13000000>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 183 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 184 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 185 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 186 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 187 | }; |
| 188 | |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 189 | infracfg_ao: infracfg_ao@10001000 { |
| 190 | compatible = "mediatek,mt7986-infracfg_ao", "syscon"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 191 | reg = <0 0x10001000 0 0x68>; |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 192 | #clock-cells = <1>; |
| 193 | }; |
| 194 | |
| 195 | infracfg: infracfg@10001040 { |
| 196 | compatible = "mediatek,mt7986-infracfg", "syscon"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 197 | reg = <0 0x1000106c 0 0x1000>; |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 198 | #clock-cells = <1>; |
| 199 | }; |
| 200 | |
| 201 | topckgen: topckgen@1001B000 { |
| 202 | compatible = "mediatek,mt7986-topckgen", "syscon"; |
| 203 | reg = <0 0x1001B000 0 0x1000>; |
| 204 | #clock-cells = <1>; |
| 205 | }; |
| 206 | |
| 207 | apmixedsys: apmixedsys@1001E000 { |
| 208 | compatible = "mediatek,mt7986-apmixedsys", "syscon"; |
| 209 | reg = <0 0x1001E000 0 0x1000>; |
| 210 | #clock-cells = <1>; |
| 211 | }; |
| 212 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 213 | watchdog: watchdog@1001c000 { |
developer | e138bcd | 2021-12-06 09:20:47 +0800 | [diff] [blame] | 214 | compatible = "mediatek,mt7986-wdt"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 215 | reg = <0 0x1001c000 0 0x1000>; |
| 216 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 217 | #reset-cells = <1>; |
| 218 | }; |
| 219 | |
| 220 | gic: interrupt-controller@c000000 { |
| 221 | compatible = "arm,gic-v3"; |
| 222 | #interrupt-cells = <3>; |
| 223 | interrupt-parent = <&gic>; |
| 224 | interrupt-controller; |
| 225 | reg = <0 0x0c000000 0 0x40000>, /* GICD */ |
| 226 | <0 0x0c080000 0 0x200000>; /* GICR */ |
| 227 | |
| 228 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 229 | }; |
| 230 | |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 231 | pwm: pwm@10048000 { |
| 232 | compatible = "mediatek,mt7986-pwm"; |
| 233 | reg = <0 0x10048000 0 0x1000>; |
| 234 | #clock-cells = <1>; |
| 235 | #pwm-cells = <2>; |
| 236 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| 237 | clocks = <&infracfg CK_INFRA_PWM>, |
| 238 | <&infracfg_ao CK_INFRA_PWM_BSEL>, |
| 239 | <&infracfg_ao CK_INFRA_PWM1_CK>, |
| 240 | <&infracfg_ao CK_INFRA_PWM2_CK>; |
| 241 | assigned-clocks = <&topckgen CK_TOP_PWM_SEL>, |
| 242 | <&infracfg_ao CK_INFRA_PWM_BSEL>, |
| 243 | <&infracfg_ao CK_INFRA_PWM1_SEL>, |
| 244 | <&infracfg_ao CK_INFRA_PWM2_SEL>; |
| 245 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>, |
| 246 | <&infracfg CK_INFRA_PWM>, |
| 247 | <&infracfg CK_INFRA_PWM>, |
| 248 | <&infracfg CK_INFRA_PWM>; |
| 249 | clock-names = "top", "main", "pwm1", "pwm2"; |
| 250 | status = "disabled"; |
| 251 | }; |
| 252 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 253 | uart0: serial@11002000 { |
| 254 | compatible = "mediatek,mt7986-uart", |
| 255 | "mediatek,mt6577-uart"; |
| 256 | reg = <0 0x11002000 0 0x400>; |
| 257 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 258 | clocks = <&infracfg_ao CK_INFRA_UART0_CK>; |
| 259 | assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| 260 | <&infracfg_ao CK_INFRA_UART0_SEL>; |
| 261 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 262 | <&infracfg CK_INFRA_UART>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 263 | status = "disabled"; |
| 264 | }; |
| 265 | |
| 266 | uart1: serial@11003000 { |
| 267 | compatible = "mediatek,mt7986-uart", |
| 268 | "mediatek,mt6577-uart"; |
| 269 | reg = <0 0x11003000 0 0x400>; |
| 270 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 271 | clocks = <&infracfg_ao CK_INFRA_UART1_CK>; |
| 272 | assigned-clocks = <&infracfg_ao CK_INFRA_UART1_SEL>; |
| 273 | assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 274 | status = "disabled"; |
| 275 | }; |
| 276 | |
| 277 | uart2: serial@11004000 { |
| 278 | compatible = "mediatek,mt7986-uart", |
| 279 | "mediatek,mt6577-uart"; |
| 280 | reg = <0 0x11004000 0 0x400>; |
| 281 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 282 | clocks = <&infracfg_ao CK_INFRA_UART2_CK>; |
| 283 | assigned-clocks = <&infracfg_ao CK_INFRA_UART2_SEL>; |
| 284 | assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 285 | status = "disabled"; |
| 286 | }; |
| 287 | |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 288 | i2c0: i2c@11008000 { |
| 289 | compatible = "mediatek,mt7986-i2c"; |
| 290 | reg = <0 0x11008000 0 0x90>, |
| 291 | <0 0x10217080 0 0x80>; |
| 292 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
developer | ccffa94 | 2021-09-22 15:57:01 +0800 | [diff] [blame] | 293 | clock-div = <5>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 294 | clocks = <&infracfg_ao CK_INFRA_I2CO_CK>, |
| 295 | <&infracfg_ao CK_INFRA_AP_DMA_CK>; |
| 296 | clock-names = "main", "dma"; |
| 297 | #address-cells = <1>; |
| 298 | #size-cells = <0>; |
| 299 | status = "disabled"; |
| 300 | }; |
| 301 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 302 | thermal-zones { |
| 303 | cpu_thermal: cpu-thermal { |
| 304 | polling-delay-passive = <1000>; |
| 305 | polling-delay = <1000>; |
| 306 | thermal-sensors = <&thermal 0>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 307 | }; |
| 308 | }; |
| 309 | |
| 310 | thermal: thermal@1100c800 { |
| 311 | #thermal-sensor-cells = <1>; |
| 312 | compatible = "mediatek,mt7986-thermal"; |
developer | 4173d3c | 2021-08-12 11:21:49 +0800 | [diff] [blame] | 313 | reg = <0 0x1100c800 0 0x800>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 314 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| 315 | clocks = <&infracfg_ao CK_INFRA_THERM_CK>, |
developer | df32d11 | 2021-08-29 11:58:01 +0800 | [diff] [blame] | 316 | <&infracfg_ao CK_INFRA_ADC_26M_CK>, |
| 317 | <&infracfg_ao CK_INFRA_ADC_FRC_CK>; |
| 318 | clock-names = "therm", "auxadc", "adc_32k"; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 319 | mediatek,auxadc = <&auxadc>; |
| 320 | mediatek,apmixedsys = <&apmixedsys>; |
| 321 | nvmem-cells = <&thermal_calibration>; |
| 322 | nvmem-cell-names = "calibration-data"; |
| 323 | }; |
| 324 | |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 325 | pcie0: pcie@11280000 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 326 | compatible = "mediatek,mt7986-pcie"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 327 | reg = <0 0x11280000 0 0x5000>; |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 328 | reg-names = "pcie-mac"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 329 | #address-cells = <3>; |
| 330 | #size-cells = <2>; |
| 331 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| 332 | bus-range = <0x00 0xff>; |
| 333 | ranges = <0x82000000 0 0x20000000 |
| 334 | 0x0 0x20000000 0 0x10000000>; |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 335 | status = "disabled"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 336 | |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 337 | clocks = <&infracfg_ao CK_INFRA_PCIE_SEL>, |
| 338 | <&infracfg_ao CK_INFRA_IPCIE_CK>, |
| 339 | <&infracfg_ao CK_INFRA_IPCIE_PIPE_CK>, |
| 340 | <&infracfg_ao CK_INFRA_IPCIER_CK>, |
| 341 | <&infracfg_ao CK_INFRA_IPCIEB_CK>; |
| 342 | |
developer | 604b5ac | 2021-12-30 14:35:44 +0800 | [diff] [blame] | 343 | phys = <&pcieport PHY_TYPE_PCIE>; |
| 344 | phy-names = "pcie-phy"; |
| 345 | |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 346 | #interrupt-cells = <1>; |
| 347 | interrupt-map-mask = <0 0 0 7>; |
| 348 | interrupt-map = <0 0 0 1 &pcie_intc0 0>, |
| 349 | <0 0 0 2 &pcie_intc0 1>, |
| 350 | <0 0 0 3 &pcie_intc0 2>, |
| 351 | <0 0 0 4 &pcie_intc0 3>; |
| 352 | pcie_intc0: interrupt-controller { |
| 353 | interrupt-controller; |
| 354 | #address-cells = <0>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 355 | #interrupt-cells = <1>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 356 | }; |
developer | 472b74d | 2022-05-31 18:17:18 +0800 | [diff] [blame^] | 357 | |
| 358 | slot0: pcie@0,0 { |
| 359 | reg = <0x0000 0 0 0 0>; |
| 360 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 361 | }; |
| 362 | |
developer | 3e91642 | 2021-05-27 16:40:29 +0800 | [diff] [blame] | 363 | crypto: crypto@10320000 { |
| 364 | compatible = "inside-secure,safexcel-eip97"; |
| 365 | reg = <0 0x10320000 0 0x40000>; |
| 366 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 367 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 368 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 369 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| 370 | interrupt-names = "ring0", "ring1", "ring2", "ring3"; |
developer | e1993bd | 2021-07-06 13:48:40 +0800 | [diff] [blame] | 371 | clocks = <&infracfg_ao CK_INFRA_EIP97_CK>; |
| 372 | clock-names = "infra_eip97_ck"; |
| 373 | assigned-clocks = <&topckgen CK_TOP_EIP_B_SEL>; |
| 374 | assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>; |
developer | 3e91642 | 2021-05-27 16:40:29 +0800 | [diff] [blame] | 375 | }; |
| 376 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 377 | pio: pinctrl@1001f000 { |
| 378 | compatible = "mediatek,mt7986-pinctrl"; |
| 379 | reg = <0 0x1001f000 0 0x1000>, |
| 380 | <0 0x11c30000 0 0x1000>, |
| 381 | <0 0x11c40000 0 0x1000>, |
| 382 | <0 0x11e20000 0 0x1000>, |
| 383 | <0 0x11e30000 0 0x1000>, |
| 384 | <0 0x11f00000 0 0x1000>, |
| 385 | <0 0x11f10000 0 0x1000>, |
| 386 | <0 0x1000b000 0 0x1000>; |
| 387 | reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base", |
| 388 | "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base", |
| 389 | "iocfg_tl_base", "eint"; |
| 390 | gpio-controller; |
| 391 | #gpio-cells = <2>; |
| 392 | gpio-ranges = <&pio 0 0 100>; |
| 393 | interrupt-controller; |
developer | a7f8fa4 | 2021-06-07 16:46:34 +0800 | [diff] [blame] | 394 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 395 | interrupt-parent = <&gic>; |
| 396 | #interrupt-cells = <2>; |
| 397 | }; |
| 398 | |
| 399 | ethsys: syscon@15000000 { |
| 400 | #address-cells = <1>; |
| 401 | #size-cells = <1>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 402 | compatible = "mediatek,mt7986-ethsys_ck", |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 403 | "syscon"; |
| 404 | reg = <0 0x15000000 0 0x1000>; |
| 405 | #clock-cells = <1>; |
| 406 | #reset-cells = <1>; |
| 407 | |
| 408 | ethsysrst: reset-controller { |
| 409 | compatible = "ti,syscon-reset"; |
| 410 | #reset-cells = <1>; |
| 411 | ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; |
| 412 | }; |
| 413 | }; |
| 414 | |
| 415 | eth: ethernet@15100000 { |
| 416 | compatible = "mediatek,mt7986-eth"; |
| 417 | reg = <0 0x15100000 0 0x80000>; |
| 418 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| 419 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
| 420 | <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| 421 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 422 | clocks = <ðsys CK_ETH_FE_EN>, |
| 423 | <ðsys CK_ETH_GP2_EN>, |
| 424 | <ðsys CK_ETH_GP1_EN>, |
| 425 | <ðsys CK_ETH_WOCPU1_EN>, |
| 426 | <ðsys CK_ETH_WOCPU0_EN>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 427 | <&sgmiisys0 CK_SGM0_TX_EN>, |
| 428 | <&sgmiisys0 CK_SGM0_RX_EN>, |
| 429 | <&sgmiisys0 CK_SGM0_CK0_EN>, |
| 430 | <&sgmiisys0 CK_SGM0_CDR_CK0_EN>, |
| 431 | <&sgmiisys1 CK_SGM1_TX_EN>, |
| 432 | <&sgmiisys1 CK_SGM1_RX_EN>, |
| 433 | <&sgmiisys1 CK_SGM1_CK1_EN>, |
| 434 | <&sgmiisys1 CK_SGM1_CDR_CK1_EN>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 435 | clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", |
| 436 | "sgmii_tx250m", "sgmii_rx250m", |
| 437 | "sgmii_cdr_ref", "sgmii_cdr_fb", |
| 438 | "sgmii2_tx250m", "sgmii2_rx250m", |
| 439 | "sgmii2_cdr_ref", "sgmii2_cdr_fb"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 440 | assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>, |
| 441 | <&topckgen CK_TOP_SGM_325M_SEL>; |
| 442 | assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>, |
| 443 | <&topckgen CK_TOP_CB_SGM_325M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 444 | mediatek,ethsys = <ðsys>; |
| 445 | mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
| 446 | #reset-cells = <1>; |
| 447 | #address-cells = <1>; |
| 448 | #size-cells = <0>; |
| 449 | status = "disabled"; |
| 450 | }; |
| 451 | |
| 452 | hnat: hnat@15000000 { |
| 453 | compatible = "mediatek,mtk-hnat_v4"; |
| 454 | reg = <0 0x15100000 0 0x80000>; |
| 455 | resets = <ðsys 0>; |
| 456 | reset-names = "mtketh"; |
| 457 | status = "disabled"; |
| 458 | }; |
| 459 | |
| 460 | sgmiisys0: syscon@10060000 { |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 461 | compatible = "mediatek,mt7986-sgmiisys", |
| 462 | "mediatek,mt7986-sgmiisys_0", |
| 463 | "syscon"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 464 | reg = <0 0x10060000 0 0x1000>; |
| 465 | #clock-cells = <1>; |
| 466 | }; |
| 467 | |
| 468 | sgmiisys1: syscon@10070000 { |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 469 | compatible = "mediatek,mt7986-sgmiisys", |
| 470 | "mediatek,mt7986-sgmiisys_1", |
| 471 | "syscon"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 472 | reg = <0 0x10070000 0 0x1000>; |
| 473 | #clock-cells = <1>; |
| 474 | }; |
| 475 | |
| 476 | snand: snfi@11005000 { |
| 477 | compatible = "mediatek,mt7986-snand"; |
| 478 | reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; |
| 479 | reg-names = "nfi", "ecc"; |
| 480 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
developer | 248c10b | 2021-07-14 16:11:19 +0800 | [diff] [blame] | 481 | clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, |
| 482 | <&infracfg_ao CK_INFRA_NFI1_CK>, |
| 483 | <&infracfg_ao CK_INFRA_NFI_HCK_CK>; |
| 484 | clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 485 | assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, |
| 486 | <&topckgen CK_TOP_NFI1X_SEL>; |
developer | e556261 | 2021-08-05 15:50:40 +0800 | [diff] [blame] | 487 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, |
| 488 | <&topckgen CK_TOP_CB_M_D8>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 489 | #address-cells = <1>; |
| 490 | #size-cells = <0>; |
| 491 | status = "disabled"; |
| 492 | }; |
| 493 | |
| 494 | wbsys: wbsys@18000000 { |
developer | eb527ef | 2022-01-12 10:38:12 +0800 | [diff] [blame] | 495 | compatible = "mediatek,wbsys", |
| 496 | "mediatek,mt7986-wmac"; |
developer | e138bcd | 2021-12-06 09:20:47 +0800 | [diff] [blame] | 497 | resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>; |
| 498 | reset-names = "consys"; |
| 499 | reg = <0 0x18000000 0 0x1000000>, |
| 500 | <0 0x10003000 0 0x1000>, |
developer | a5ea3d2 | 2022-02-17 09:23:09 +0800 | [diff] [blame] | 501 | <0 0x11d10000 0 0x1000>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 502 | interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
| 503 | <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| 504 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, |
| 505 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; |
| 506 | chip_id = <0x7986>; |
developer | e138bcd | 2021-12-06 09:20:47 +0800 | [diff] [blame] | 507 | memory-region = <&wmcpu_emi>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 508 | }; |
| 509 | |
| 510 | wed_pcie: wed_pcie@10003000 { |
| 511 | compatible = "mediatek,wed_pcie"; |
| 512 | reg = <0 0x10003000 0 0x10>; |
| 513 | }; |
| 514 | |
| 515 | spi0: spi@1100a000 { |
developer | 44700a2 | 2021-07-13 19:06:49 +0800 | [diff] [blame] | 516 | compatible = "mediatek,ipm-spi-quad"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 517 | reg = <0 0x1100a000 0 0x100>; |
| 518 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 519 | clocks = <&topckgen CK_TOP_CB_M_D2>, |
developer | 44700a2 | 2021-07-13 19:06:49 +0800 | [diff] [blame] | 520 | <&topckgen CK_TOP_SPI_SEL>, |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 521 | <&infracfg_ao CK_INFRA_SPI0_CK>, |
developer | 44700a2 | 2021-07-13 19:06:49 +0800 | [diff] [blame] | 522 | <&infracfg_ao CK_INFRA_SPI0_HCK_CK>; |
| 523 | clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 524 | status = "disabled"; |
| 525 | }; |
| 526 | |
| 527 | spi1: spi@1100b000 { |
developer | 44700a2 | 2021-07-13 19:06:49 +0800 | [diff] [blame] | 528 | compatible = "mediatek,ipm-spi-single"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 529 | reg = <0 0x1100b000 0 0x100>; |
| 530 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 531 | clocks = <&topckgen CK_TOP_CB_M_D2>, |
developer | 44700a2 | 2021-07-13 19:06:49 +0800 | [diff] [blame] | 532 | <&topckgen CK_TOP_SPIM_MST_SEL>, |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 533 | <&infracfg_ao CK_INFRA_SPI1_CK>, |
developer | 44700a2 | 2021-07-13 19:06:49 +0800 | [diff] [blame] | 534 | <&infracfg_ao CK_INFRA_SPI1_HCK_CK>; |
| 535 | clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 536 | status = "disabled"; |
| 537 | }; |
| 538 | |
developer | 637f555 | 2021-05-27 17:45:27 +0800 | [diff] [blame] | 539 | mmc0: mmc@11230000 { |
| 540 | compatible = "mediatek,mt7986-mmc"; |
| 541 | reg = <0 0x11230000 0 0x1000>, |
| 542 | <0 0x11c20000 0 0x1000>; |
| 543 | interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 544 | clocks = <&topckgen CK_TOP_EMMC_416M>, |
developer | 30389d9 | 2022-05-10 09:35:17 +0800 | [diff] [blame] | 545 | <&infracfg_ao CK_INFRA_MSDC_HCK_CK>, |
| 546 | <&infracfg_ao CK_INFRA_MSDC_CK>, |
| 547 | <&infracfg_ao CK_INFRA_MSDC_66M_CK>, |
| 548 | <&infracfg_ao CK_INFRA_MSDC_133M_CK>; |
| 549 | clock-names = "source", "hclk", "source_cg", "sys_cg", "axi_cg"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 550 | assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>, |
| 551 | <&topckgen CK_TOP_EMMC_250M_SEL>; |
developer | f089cc0 | 2021-09-11 17:23:41 +0800 | [diff] [blame] | 552 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>, |
| 553 | <&topckgen CK_TOP_NET1_D5_D2>; |
developer | 637f555 | 2021-05-27 17:45:27 +0800 | [diff] [blame] | 554 | status = "disabled"; |
| 555 | }; |
| 556 | |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 557 | auxadc: adc@1100d000 { |
| 558 | compatible = "mediatek,mt7986-auxadc", |
| 559 | "mediatek,mt7622-auxadc"; |
| 560 | reg = <0 0x1100d000 0 0x1000>; |
developer | 2cdfa05 | 2021-08-12 10:41:52 +0800 | [diff] [blame] | 561 | clocks = <&infracfg_ao CK_INFRA_ADC_26M_CK>, |
| 562 | <&infracfg_ao CK_INFRA_ADC_FRC_CK>; |
| 563 | clock-names = "main", "32k"; |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 564 | #io-channel-cells = <1>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 565 | status = "disabled"; |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 566 | }; |
| 567 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 568 | consys: consys@10000000 { |
| 569 | compatible = "mediatek,mt7986-consys"; |
| 570 | reg = <0 0x10000000 0 0x8600000>; |
| 571 | memory-region = <&wmcpu_emi>; |
| 572 | }; |
| 573 | |
| 574 | xhci: xhci@11200000 { |
| 575 | compatible = "mediatek,mt7986-xhci", |
| 576 | "mediatek,mtk-xhci"; |
| 577 | reg = <0 0x11200000 0 0x2e00>, |
| 578 | <0 0x11203e00 0 0x0100>; |
| 579 | reg-names = "mac", "ippc"; |
| 580 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| 581 | phys = <&u2port0 PHY_TYPE_USB2>, |
| 582 | <&u3port0 PHY_TYPE_USB3>, |
| 583 | <&u2port1 PHY_TYPE_USB2>; |
| 584 | clocks = <&system_clk>, |
| 585 | <&system_clk>, |
| 586 | <&system_clk>, |
| 587 | <&system_clk>, |
| 588 | <&system_clk>; |
| 589 | clock-names = "sys_ck", |
| 590 | "xhci_ck", |
| 591 | "ref_ck", |
| 592 | "mcu_ck", |
| 593 | "dma_ck"; |
| 594 | #address-cells = <2>; |
| 595 | #size-cells = <2>; |
developer | 604b5ac | 2021-12-30 14:35:44 +0800 | [diff] [blame] | 596 | status = "okay"; |
| 597 | }; |
| 598 | |
| 599 | pcietphy: pcie-phy@11c00000 { |
| 600 | compatible = "mediatek,mt7986", |
developer | 98e5cb2 | 2022-01-28 17:31:23 +0800 | [diff] [blame] | 601 | "mediatek,generic-tphy-v4"; |
developer | 604b5ac | 2021-12-30 14:35:44 +0800 | [diff] [blame] | 602 | #address-cells = <2>; |
| 603 | #size-cells = <2>; |
| 604 | ranges; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 605 | status = "okay"; |
developer | 604b5ac | 2021-12-30 14:35:44 +0800 | [diff] [blame] | 606 | |
| 607 | pcieport: pcie-phy@11c00000 { |
| 608 | reg = <0 0x11c00000 0 0x20000>; |
| 609 | clocks = <&system_clk>; |
| 610 | clock-names = "ref"; |
| 611 | #phy-cells = <1>; |
developer | 98e5cb2 | 2022-01-28 17:31:23 +0800 | [diff] [blame] | 612 | auto_load_valid; |
| 613 | auto_load_valid_ln1; |
| 614 | nvmem-cells = <&pcie_intr_ln0>, |
| 615 | <&pcie_rx_imp_ln0>, |
| 616 | <&pcie_tx_imp_ln0>, |
| 617 | <&pcie_auto_load_valid_ln0>, |
| 618 | <&pcie_intr_ln1>, |
| 619 | <&pcie_rx_imp_ln1>, |
| 620 | <&pcie_tx_imp_ln1>, |
| 621 | <&pcie_auto_load_valid_ln1>; |
| 622 | nvmem-cell-names = "intr", |
| 623 | "rx_imp", |
| 624 | "tx_imp", |
| 625 | "auto_load_valid", |
| 626 | "intr_ln1", |
| 627 | "rx_imp_ln1", |
| 628 | "tx_imp_ln1", |
| 629 | "auto_load_valid_ln1"; |
developer | 604b5ac | 2021-12-30 14:35:44 +0800 | [diff] [blame] | 630 | status = "okay"; |
| 631 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 632 | }; |
| 633 | |
| 634 | usbtphy: usb-phy@11e10000 { |
| 635 | compatible = "mediatek,mt7986", |
| 636 | "mediatek,generic-tphy-v2"; |
| 637 | #address-cells = <2>; |
| 638 | #size-cells = <2>; |
| 639 | ranges; |
| 640 | status = "okay"; |
| 641 | |
| 642 | u2port0: usb-phy@11e10000 { |
| 643 | reg = <0 0x11e10000 0 0x700>; |
| 644 | clocks = <&system_clk>; |
| 645 | clock-names = "ref"; |
| 646 | #phy-cells = <1>; |
developer | 98e5cb2 | 2022-01-28 17:31:23 +0800 | [diff] [blame] | 647 | auto_load_valid; |
| 648 | nvmem-cells = <&u2_intr_p0>, <&u2_auto_load_valid_p0>; |
| 649 | nvmem-cell-names = "intr", "auto_load_valid"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 650 | status = "okay"; |
| 651 | }; |
| 652 | |
| 653 | u3port0: usb-phy@11e10700 { |
| 654 | reg = <0 0x11e10700 0 0x900>; |
| 655 | clocks = <&system_clk>; |
| 656 | clock-names = "ref"; |
| 657 | #phy-cells = <1>; |
developer | 98e5cb2 | 2022-01-28 17:31:23 +0800 | [diff] [blame] | 658 | auto_load_valid; |
| 659 | nvmem-cells = <&comb_intr_p0>, |
| 660 | <&comb_rx_imp_p0>, |
| 661 | <&comb_tx_imp_p0>, |
| 662 | <&comb_auto_load_valid>; |
| 663 | nvmem-cell-names = "intr", "rx_imp", "tx_imp", "auto_load_valid"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 664 | status = "okay"; |
| 665 | }; |
| 666 | |
| 667 | u2port1: usb-phy@11e11000 { |
| 668 | reg = <0 0x11e11000 0 0x700>; |
| 669 | clocks = <&system_clk>; |
| 670 | clock-names = "ref"; |
| 671 | #phy-cells = <1>; |
developer | 98e5cb2 | 2022-01-28 17:31:23 +0800 | [diff] [blame] | 672 | auto_load_valid; |
| 673 | nvmem-cells = <&u2_intr_p1>, <&u2_auto_load_valid_p1>; |
| 674 | nvmem-cell-names = "intr", "auto_load_valid"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 675 | status = "okay"; |
| 676 | }; |
| 677 | }; |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 678 | |
| 679 | clkitg: clkitg { |
| 680 | compatible = "simple-bus"; |
| 681 | }; |
developer | fbbf02b | 2021-06-25 09:30:28 +0800 | [diff] [blame] | 682 | |
developer | e1993bd | 2021-07-06 13:48:40 +0800 | [diff] [blame] | 683 | afe: audio-controller@11210000 { |
developer | be797a3 | 2021-12-16 16:56:09 +0800 | [diff] [blame] | 684 | compatible = "mediatek,mt79xx-audio"; |
developer | e1993bd | 2021-07-06 13:48:40 +0800 | [diff] [blame] | 685 | reg = <0 0x11210000 0 0x9000>; |
| 686 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| 687 | clocks = <&infracfg_ao CK_INFRA_AUD_BUS_CK>, |
| 688 | <&infracfg_ao CK_INFRA_AUD_26M_CK>, |
| 689 | <&infracfg_ao CK_INFRA_AUD_L_CK>, |
| 690 | <&infracfg_ao CK_INFRA_AUD_AUD_CK>, |
| 691 | <&infracfg_ao CK_INFRA_AUD_EG2_CK>; |
| 692 | clock-names = "aud_bus_ck", |
| 693 | "aud_26m_ck", |
| 694 | "aud_l_ck", |
| 695 | "aud_aud_ck", |
| 696 | "aud_eg2_ck"; |
| 697 | assigned-clocks = <&topckgen CK_TOP_A1SYS_SEL>, |
| 698 | <&topckgen CK_TOP_AUD_L_SEL>, |
| 699 | <&topckgen CK_TOP_A_TUNER_SEL>; |
| 700 | assigned-clock-parents = <&topckgen CK_TOP_APLL2_D4>, |
| 701 | <&topckgen CK_TOP_CB_APLL2_196M>, |
| 702 | <&topckgen CK_TOP_APLL2_D4>; |
| 703 | }; |
| 704 | |
developer | fbbf02b | 2021-06-25 09:30:28 +0800 | [diff] [blame] | 705 | trng: trng@1020f000 { |
| 706 | compatible = "mediatek,mt7986-rng", |
| 707 | "mediatek,mt7623-rng"; |
| 708 | reg = <0 0x1020f000 0 0x100>; |
| 709 | clocks = <&infracfg_ao CK_INFRA_TRNG_CK>; |
| 710 | clock-names = "rng"; |
| 711 | }; |
developer | 86ee1e1 | 2021-06-30 11:18:53 +0800 | [diff] [blame] | 712 | |
| 713 | ice: ice_debug { |
| 714 | compatible = "mediatek,mt7986-ice_debug", |
| 715 | "mediatek,mt2701-ice_debug"; |
developer | 66b5c8d | 2021-07-16 14:02:47 +0800 | [diff] [blame] | 716 | clocks = <&infracfg_ao CK_INFRA_DBG_CK>, |
| 717 | <&topckgen CK_TOP_ARM_DB_JTSEL>; |
| 718 | clock-names = "ice_dbg", "dbg_jtsel"; |
developer | 86ee1e1 | 2021-06-30 11:18:53 +0800 | [diff] [blame] | 719 | }; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 720 | |
| 721 | efuse: efuse@11d00000 { |
| 722 | compatible = "mediatek,mt7986-efuse", |
| 723 | "mediatek,efuse"; |
| 724 | reg = <0 0x11d00000 0 0x1000>; |
| 725 | #address-cells = <1>; |
| 726 | #size-cells = <1>; |
| 727 | |
| 728 | thermal_calibration: calib@274 { |
| 729 | reg = <0x274 0xc>; |
| 730 | }; |
developer | 98e5cb2 | 2022-01-28 17:31:23 +0800 | [diff] [blame] | 731 | |
| 732 | comb_auto_load_valid: usb3-alv-imp@8da { |
| 733 | reg = <0x8da 1>; |
| 734 | bits = <0 1>; |
| 735 | }; |
| 736 | |
| 737 | comb_rx_imp_p0: usb3-rx-imp@8d8 { |
| 738 | reg = <0x8d8 1>; |
| 739 | bits = <0 5>; |
| 740 | }; |
| 741 | |
| 742 | comb_tx_imp_p0: usb3-tx-imp@8d8 { |
| 743 | reg = <0x8d8 2>; |
| 744 | bits = <5 5>; |
| 745 | }; |
| 746 | |
| 747 | comb_intr_p0: usb3-intr@8d9 { |
| 748 | reg = <0x8d9 1>; |
| 749 | bits = <2 6>; |
| 750 | }; |
| 751 | |
| 752 | u2_auto_load_valid_p0: usb2-alv-p0@8e0 { |
| 753 | reg = <0x8e0 1>; |
| 754 | bits = <0 1>; |
| 755 | }; |
| 756 | |
| 757 | u2_intr_p0: usb2-intr-p0@8e0 { |
| 758 | reg = <0x8e0 1>; |
| 759 | bits = <1 5>; |
| 760 | }; |
| 761 | |
| 762 | u2_auto_load_valid_p1: usb2-alv-p1@8e0 { |
| 763 | reg = <0x8e0 2>; |
| 764 | bits = <6 1>; |
| 765 | }; |
| 766 | |
| 767 | u2_intr_p1: usb2-intr-p1@8e0 { |
| 768 | reg = <0x8e0 2>; |
| 769 | bits = <7 5>; |
| 770 | }; |
| 771 | |
| 772 | pcie_rx_imp_ln0: pcie-rx-imp@8d0 { |
| 773 | reg = <0x8d0 1>; |
| 774 | bits = <0 5>; |
| 775 | }; |
| 776 | |
| 777 | pcie_tx_imp_ln0: pcie-tx-imp@8d0 { |
| 778 | reg = <0x8d0 2>; |
| 779 | bits = <5 5>; |
| 780 | }; |
| 781 | |
| 782 | pcie_intr_ln0: pcie-intr@8d1 { |
| 783 | reg = <0x8d1 1>; |
| 784 | bits = <2 6>; |
| 785 | }; |
| 786 | |
| 787 | pcie_auto_load_valid_ln0: pcie-ln0-alv@8d4 { |
| 788 | reg = <0x8d4 1>; |
| 789 | bits = <0 1>; |
| 790 | }; |
| 791 | |
| 792 | pcie_rx_imp_ln1: pcie-rx-imp@8d2 { |
| 793 | reg = <0x8d2 1>; |
| 794 | bits = <0 5>; |
| 795 | }; |
| 796 | |
| 797 | pcie_tx_imp_ln1: pcie-tx-imp@8d2 { |
| 798 | reg = <0x8d2 2>; |
| 799 | bits = <5 5>; |
| 800 | }; |
| 801 | |
| 802 | pcie_intr_ln1: pcie-intr@8d3 { |
| 803 | reg = <0x8d3 1>; |
| 804 | bits = <2 6>; |
| 805 | }; |
| 806 | |
| 807 | pcie_auto_load_valid_ln1: pcie-ln1-alv@8d4 { |
| 808 | reg = <0x8d4 1>; |
| 809 | bits = <1 1>; |
| 810 | }; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 811 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 812 | }; |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 813 | |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 814 | #include "mt7986-clkitg.dtsi" |