| commit | 604b5ac721cf32ded1bcfc685957864905853d11 | [log] [tgz] |
|---|---|---|
| author | developer <developer@mediatek.com> | Thu Dec 30 14:35:44 2021 +0800 |
| committer | developer <developer@mediatek.com> | Thu Jan 06 12:25:25 2022 +0800 |
| tree | c5c6ba93c0c4aad63f30c3edd0b3719f734d84e0 | |
| parent | 17ab9eea096d4471a3374ebd40931abab90b4a25 [diff] [blame] |
[][Enable PCIe PHY for mt7986] [Description] Add PCIe PHY for mt7986. [Release-log] N/A Change-Id: I0b065ff71ce325bfabc942f0e033111522784047 Reviewed-on: https://gerrit.mediatek.inc/c/openwrt/feeds/mtk_openwrt_feeds/+/5456938
diff --git a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 8d41d80..9468315 100644 --- a/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/target/linux/mediatek/files-5.4/arch/arm64/boot/dts/mediatek/mt7986a.dtsi
@@ -340,6 +340,9 @@ <&infracfg_ao CK_INFRA_IPCIER_CK>, <&infracfg_ao CK_INFRA_IPCIEB_CK>; + phys = <&pcieport PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; interrupt-map = <0 0 0 1 &pcie_intc0 0>, @@ -583,7 +586,24 @@ "dma_ck"; #address-cells = <2>; #size-cells = <2>; + status = "okay"; + }; + + pcietphy: pcie-phy@11c00000 { + compatible = "mediatek,mt7986", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + ranges; status = "okay"; + + pcieport: pcie-phy@11c00000 { + reg = <0 0x11c00000 0 0x20000>; + clocks = <&system_clk>; + clock-names = "ref"; + #phy-cells = <1>; + status = "okay"; + }; }; usbtphy: usb-phy@11e10000 {