blob: c93d479cc1b880fd47fd9715b5b5f3cecf7638c3 [file] [log] [blame]
developerfd40db22021-04-29 10:08:25 +08001/*
2 * Copyright (c) 2020 MediaTek Inc.
3 * Author: Sam.Shih <sam.shih@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <dt-bindings/interrupt-controller/irq.h>
16#include <dt-bindings/interrupt-controller/arm-gic.h>
17#include <dt-bindings/phy/phy.h>
18#include <dt-bindings/reset/ti-syscon.h>
developer15adbbf2021-05-24 22:20:07 +080019#include <dt-bindings/clock/mt7986-clk.h>
developer3e9ad9d2021-07-01 16:42:25 +080020#include <dt-bindings/thermal/thermal.h>
developer7f4cdcd2021-08-03 19:29:43 +080021#include <dt-bindings/pinctrl/mt65xx.h>
developere138bcd2021-12-06 09:20:47 +080022#include <dt-bindings/reset/mt7986-resets.h>
developer15adbbf2021-05-24 22:20:07 +080023
developerfd40db22021-04-29 10:08:25 +080024/ {
25 compatible = "mediatek,mt7986a-rfb";
26 interrupt-parent = <&gic>;
27 #address-cells = <2>;
28 #size-cells = <2>;
29 cpus {
30 #address-cells = <1>;
31 #size-cells = <0>;
developer3e9ad9d2021-07-01 16:42:25 +080032 cpu0: cpu@0 {
developerfd40db22021-04-29 10:08:25 +080033 device_type = "cpu";
34 compatible = "arm,cortex-a53";
35 enable-method = "psci";
36 reg = <0x0>;
37 };
38
developer3e9ad9d2021-07-01 16:42:25 +080039 cpu1: cpu@1 {
developerfd40db22021-04-29 10:08:25 +080040 device_type = "cpu";
41 compatible = "arm,cortex-a53";
42 enable-method = "psci";
43 reg = <0x1>;
44 };
45
developer3e9ad9d2021-07-01 16:42:25 +080046 cpu2: cpu@2 {
developerfd40db22021-04-29 10:08:25 +080047 device_type = "cpu";
48 compatible = "arm,cortex-a53";
49 enable-method = "psci";
50 reg = <0x2>;
51 };
52
developer3e9ad9d2021-07-01 16:42:25 +080053 cpu3: cpu@3 {
developerfd40db22021-04-29 10:08:25 +080054 device_type = "cpu";
55 enable-method = "psci";
56 compatible = "arm,cortex-a53";
57 reg = <0x3>;
58 };
59 };
60
61 wed: wed@15010000 {
62 compatible = "mediatek,wed";
63 wed_num = <2>;
64 /* add this property for wed get the pci slot number. */
65 pci_slot_map = <0>, <1>;
66 reg = <0 0x15010000 0 0x1000>,
67 <0 0x15011000 0 0x1000>;
68 interrupt-parent = <&gic>;
69 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
71 };
72
73 wed2: wed2@15011000 {
74 compatible = "mediatek,wed2";
75 wed_num = <2>;
76 reg = <0 0x15010000 0 0x1000>,
77 <0 0x15011000 0 0x1000>;
78 interrupt-parent = <&gic>;
79 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
80 <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
81 };
82
83 wdma: wdma@15104800 {
84 compatible = "mediatek,wed-wdma";
85 reg = <0 0x15104800 0 0x400>,
86 <0 0x15104c00 0 0x400>;
87 };
88
89 ap2woccif: ap2woccif@151A5000 {
90 compatible = "mediatek,ap2woccif";
91 reg = <0 0x151A5000 0 0x1000>,
92 <0 0x151AD000 0 0x1000>;
93 interrupt-parent = <&gic>;
94 interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>,
95 <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
96 };
97
98 wocpu0_ilm: wocpu0_ilm@151E0000 {
99 compatible = "mediatek,wocpu0_ilm";
100 reg = <0 0x151E0000 0 0x8000>;
101 };
102
103 wocpu1_ilm: wocpu1_ilm@151F0000 {
104 compatible = "mediatek,wocpu1_ilm";
105 reg = <0 0x151F0000 0 0x8000>;
106 };
107
108 wocpu_dlm: wocpu_dlm@151E8000 {
109 compatible = "mediatek,wocpu_dlm";
110 reg = <0 0x151E8000 0 0x2000>,
111 <0 0x151F8000 0 0x2000>;
112
113 resets = <&ethsysrst 0>;
114 reset-names = "wocpu_rst";
115 };
116
117 cpu_boot: wocpu_boot@15194000 {
118 compatible = "mediatek,wocpu_boot";
119 reg = <0 0x15194000 0 0x1000>;
120 };
121
122 reserved-memory {
123 #address-cells = <2>;
124 #size-cells = <2>;
125 ranges;
126
127 /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
128 secmon_reserved: secmon@43000000 {
129 reg = <0 0x43000000 0 0x30000>;
130 no-map;
131 };
132
133 wmcpu_emi: wmcpu-reserved@4FC00000 {
134 compatible = "mediatek,wmcpu-reserved";
135 no-map;
136 reg = <0 0x4FC00000 0 0x00100000>;
137 };
138
139 wocpu0_emi: wocpu0_emi@4FD00000 {
140 compatible = "mediatek,wocpu0_emi";
141 no-map;
142 reg = <0 0x4FD00000 0 0x40000>;
143 shared = <0>;
144 };
145
developer86423f02021-10-12 15:20:50 +0800146 wocpu1_emi: wocpu1_emi@4FD40000 {
developerfd40db22021-04-29 10:08:25 +0800147 compatible = "mediatek,wocpu1_emi";
148 no-map;
149 reg = <0 0x4FD40000 0 0x40000>;
150 shared = <0>;
151 };
152
developer86423f02021-10-12 15:20:50 +0800153 wocpu_data: wocpu_data@4FD80000 {
developerfd40db22021-04-29 10:08:25 +0800154 compatible = "mediatek,wocpu_data";
155 no-map;
developer8be272e2021-07-29 13:15:07 +0800156 reg = <0 0x4FD80000 0 0x240000>;
developerfd40db22021-04-29 10:08:25 +0800157 shared = <1>;
158 };
159 };
160
161 psci {
162 compatible = "arm,psci-0.2";
163 method = "smc";
164 };
165
developer15adbbf2021-05-24 22:20:07 +0800166 clk40m: oscillator@0 {
167 compatible = "fixed-clock";
168 #clock-cells = <0>;
169 clock-frequency = <40000000>;
170 clock-output-names = "clkxtal";
171 };
172
developerfd40db22021-04-29 10:08:25 +0800173 system_clk: dummy_system_clk {
174 compatible = "fixed-clock";
175 clock-frequency = <40000000>;
176 #clock-cells = <0>;
177 };
178
developerfd40db22021-04-29 10:08:25 +0800179 timer {
180 compatible = "arm,armv8-timer";
181 interrupt-parent = <&gic>;
developerf39022a2021-05-06 13:31:52 +0800182 clock-frequency = <13000000>;
developerfd40db22021-04-29 10:08:25 +0800183 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
184 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
185 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
186 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
developerfd40db22021-04-29 10:08:25 +0800187 };
188
developer15adbbf2021-05-24 22:20:07 +0800189 infracfg_ao: infracfg_ao@10001000 {
190 compatible = "mediatek,mt7986-infracfg_ao", "syscon";
developer8b9f2852021-06-03 21:53:08 +0800191 reg = <0 0x10001000 0 0x68>;
developer15adbbf2021-05-24 22:20:07 +0800192 #clock-cells = <1>;
193 };
194
195 infracfg: infracfg@10001040 {
196 compatible = "mediatek,mt7986-infracfg", "syscon";
developer8b9f2852021-06-03 21:53:08 +0800197 reg = <0 0x1000106c 0 0x1000>;
developer15adbbf2021-05-24 22:20:07 +0800198 #clock-cells = <1>;
199 };
200
201 topckgen: topckgen@1001B000 {
202 compatible = "mediatek,mt7986-topckgen", "syscon";
203 reg = <0 0x1001B000 0 0x1000>;
204 #clock-cells = <1>;
205 };
206
207 apmixedsys: apmixedsys@1001E000 {
208 compatible = "mediatek,mt7986-apmixedsys", "syscon";
209 reg = <0 0x1001E000 0 0x1000>;
210 #clock-cells = <1>;
211 };
212
developerfd40db22021-04-29 10:08:25 +0800213 watchdog: watchdog@1001c000 {
developere138bcd2021-12-06 09:20:47 +0800214 compatible = "mediatek,mt7986-wdt";
developerfd40db22021-04-29 10:08:25 +0800215 reg = <0 0x1001c000 0 0x1000>;
216 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
217 #reset-cells = <1>;
218 };
219
220 gic: interrupt-controller@c000000 {
221 compatible = "arm,gic-v3";
222 #interrupt-cells = <3>;
223 interrupt-parent = <&gic>;
224 interrupt-controller;
225 reg = <0 0x0c000000 0 0x40000>, /* GICD */
226 <0 0x0c080000 0 0x200000>; /* GICR */
227
228 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
229 };
230
developer8b9f2852021-06-03 21:53:08 +0800231 pwm: pwm@10048000 {
232 compatible = "mediatek,mt7986-pwm";
233 reg = <0 0x10048000 0 0x1000>;
234 #clock-cells = <1>;
235 #pwm-cells = <2>;
236 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&infracfg CK_INFRA_PWM>,
238 <&infracfg_ao CK_INFRA_PWM_BSEL>,
239 <&infracfg_ao CK_INFRA_PWM1_CK>,
240 <&infracfg_ao CK_INFRA_PWM2_CK>;
241 assigned-clocks = <&topckgen CK_TOP_PWM_SEL>,
242 <&infracfg_ao CK_INFRA_PWM_BSEL>,
243 <&infracfg_ao CK_INFRA_PWM1_SEL>,
244 <&infracfg_ao CK_INFRA_PWM2_SEL>;
245 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>,
246 <&infracfg CK_INFRA_PWM>,
247 <&infracfg CK_INFRA_PWM>,
248 <&infracfg CK_INFRA_PWM>;
249 clock-names = "top", "main", "pwm1", "pwm2";
250 status = "disabled";
251 };
252
developerfd40db22021-04-29 10:08:25 +0800253 uart0: serial@11002000 {
254 compatible = "mediatek,mt7986-uart",
255 "mediatek,mt6577-uart";
256 reg = <0 0x11002000 0 0x400>;
257 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
developer8b9f2852021-06-03 21:53:08 +0800258 clocks = <&infracfg_ao CK_INFRA_UART0_CK>;
259 assigned-clocks = <&topckgen CK_TOP_UART_SEL>,
260 <&infracfg_ao CK_INFRA_UART0_SEL>;
261 assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>,
262 <&infracfg CK_INFRA_UART>;
developerfd40db22021-04-29 10:08:25 +0800263 status = "disabled";
264 };
265
266 uart1: serial@11003000 {
267 compatible = "mediatek,mt7986-uart",
268 "mediatek,mt6577-uart";
269 reg = <0 0x11003000 0 0x400>;
270 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
developer8b9f2852021-06-03 21:53:08 +0800271 clocks = <&infracfg_ao CK_INFRA_UART1_CK>;
272 assigned-clocks = <&infracfg_ao CK_INFRA_UART1_SEL>;
273 assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
developerfd40db22021-04-29 10:08:25 +0800274 status = "disabled";
275 };
276
277 uart2: serial@11004000 {
278 compatible = "mediatek,mt7986-uart",
279 "mediatek,mt6577-uart";
280 reg = <0 0x11004000 0 0x400>;
281 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
developer8b9f2852021-06-03 21:53:08 +0800282 clocks = <&infracfg_ao CK_INFRA_UART2_CK>;
283 assigned-clocks = <&infracfg_ao CK_INFRA_UART2_SEL>;
284 assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>;
developerfd40db22021-04-29 10:08:25 +0800285 status = "disabled";
286 };
287
developer8b9f2852021-06-03 21:53:08 +0800288 i2c0: i2c@11008000 {
289 compatible = "mediatek,mt7986-i2c";
290 reg = <0 0x11008000 0 0x90>,
291 <0 0x10217080 0 0x80>;
292 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
developerccffa942021-09-22 15:57:01 +0800293 clock-div = <5>;
developer8b9f2852021-06-03 21:53:08 +0800294 clocks = <&infracfg_ao CK_INFRA_I2CO_CK>,
295 <&infracfg_ao CK_INFRA_AP_DMA_CK>;
296 clock-names = "main", "dma";
297 #address-cells = <1>;
298 #size-cells = <0>;
299 status = "disabled";
300 };
301
developer3e9ad9d2021-07-01 16:42:25 +0800302 thermal-zones {
303 cpu_thermal: cpu-thermal {
304 polling-delay-passive = <1000>;
305 polling-delay = <1000>;
306 thermal-sensors = <&thermal 0>;
developer3e9ad9d2021-07-01 16:42:25 +0800307 };
308 };
309
310 thermal: thermal@1100c800 {
311 #thermal-sensor-cells = <1>;
312 compatible = "mediatek,mt7986-thermal";
developer4173d3c2021-08-12 11:21:49 +0800313 reg = <0 0x1100c800 0 0x800>;
developer3e9ad9d2021-07-01 16:42:25 +0800314 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&infracfg_ao CK_INFRA_THERM_CK>,
developerdf32d112021-08-29 11:58:01 +0800316 <&infracfg_ao CK_INFRA_ADC_26M_CK>,
317 <&infracfg_ao CK_INFRA_ADC_FRC_CK>;
318 clock-names = "therm", "auxadc", "adc_32k";
developer3e9ad9d2021-07-01 16:42:25 +0800319 mediatek,auxadc = <&auxadc>;
320 mediatek,apmixedsys = <&apmixedsys>;
321 nvmem-cells = <&thermal_calibration>;
322 nvmem-cell-names = "calibration-data";
323 };
324
developere2ed4342021-07-02 16:04:23 +0800325 pcie0: pcie@11280000 {
developerfd40db22021-04-29 10:08:25 +0800326 compatible = "mediatek,mt7986-pcie";
developerfd40db22021-04-29 10:08:25 +0800327 reg = <0 0x11280000 0 0x5000>;
developere2ed4342021-07-02 16:04:23 +0800328 reg-names = "pcie-mac";
developerfd40db22021-04-29 10:08:25 +0800329 #address-cells = <3>;
330 #size-cells = <2>;
331 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
332 bus-range = <0x00 0xff>;
333 ranges = <0x82000000 0 0x20000000
334 0x0 0x20000000 0 0x10000000>;
developere2ed4342021-07-02 16:04:23 +0800335 status = "disabled";
developerfd40db22021-04-29 10:08:25 +0800336
developere2ed4342021-07-02 16:04:23 +0800337 clocks = <&infracfg_ao CK_INFRA_PCIE_SEL>,
338 <&infracfg_ao CK_INFRA_IPCIE_CK>,
339 <&infracfg_ao CK_INFRA_IPCIE_PIPE_CK>,
340 <&infracfg_ao CK_INFRA_IPCIER_CK>,
341 <&infracfg_ao CK_INFRA_IPCIEB_CK>;
342
developer604b5ac2021-12-30 14:35:44 +0800343 phys = <&pcieport PHY_TYPE_PCIE>;
344 phy-names = "pcie-phy";
345
developere2ed4342021-07-02 16:04:23 +0800346 #interrupt-cells = <1>;
347 interrupt-map-mask = <0 0 0 7>;
348 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
349 <0 0 0 2 &pcie_intc0 1>,
350 <0 0 0 3 &pcie_intc0 2>,
351 <0 0 0 4 &pcie_intc0 3>;
352 pcie_intc0: interrupt-controller {
353 interrupt-controller;
354 #address-cells = <0>;
developerfd40db22021-04-29 10:08:25 +0800355 #interrupt-cells = <1>;
developerfd40db22021-04-29 10:08:25 +0800356 };
357 };
358
developer3e916422021-05-27 16:40:29 +0800359 crypto: crypto@10320000 {
360 compatible = "inside-secure,safexcel-eip97";
361 reg = <0 0x10320000 0 0x40000>;
362 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
366 interrupt-names = "ring0", "ring1", "ring2", "ring3";
developere1993bd2021-07-06 13:48:40 +0800367 clocks = <&infracfg_ao CK_INFRA_EIP97_CK>;
368 clock-names = "infra_eip97_ck";
369 assigned-clocks = <&topckgen CK_TOP_EIP_B_SEL>;
370 assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>;
developer3e916422021-05-27 16:40:29 +0800371 };
372
developerfd40db22021-04-29 10:08:25 +0800373 pio: pinctrl@1001f000 {
374 compatible = "mediatek,mt7986-pinctrl";
375 reg = <0 0x1001f000 0 0x1000>,
376 <0 0x11c30000 0 0x1000>,
377 <0 0x11c40000 0 0x1000>,
378 <0 0x11e20000 0 0x1000>,
379 <0 0x11e30000 0 0x1000>,
380 <0 0x11f00000 0 0x1000>,
381 <0 0x11f10000 0 0x1000>,
382 <0 0x1000b000 0 0x1000>;
383 reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base",
384 "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base",
385 "iocfg_tl_base", "eint";
386 gpio-controller;
387 #gpio-cells = <2>;
388 gpio-ranges = <&pio 0 0 100>;
389 interrupt-controller;
developera7f8fa42021-06-07 16:46:34 +0800390 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
developerfd40db22021-04-29 10:08:25 +0800391 interrupt-parent = <&gic>;
392 #interrupt-cells = <2>;
393 };
394
395 ethsys: syscon@15000000 {
396 #address-cells = <1>;
397 #size-cells = <1>;
developer8b9f2852021-06-03 21:53:08 +0800398 compatible = "mediatek,mt7986-ethsys_ck",
developerfd40db22021-04-29 10:08:25 +0800399 "syscon";
400 reg = <0 0x15000000 0 0x1000>;
401 #clock-cells = <1>;
402 #reset-cells = <1>;
403
404 ethsysrst: reset-controller {
405 compatible = "ti,syscon-reset";
406 #reset-cells = <1>;
407 ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>;
408 };
409 };
410
411 eth: ethernet@15100000 {
412 compatible = "mediatek,mt7986-eth";
413 reg = <0 0x15100000 0 0x80000>;
414 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
415 <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
developer8b9f2852021-06-03 21:53:08 +0800418 clocks = <&ethsys CK_ETH_FE_EN>,
419 <&ethsys CK_ETH_GP2_EN>,
420 <&ethsys CK_ETH_GP1_EN>,
421 <&ethsys CK_ETH_WOCPU1_EN>,
422 <&ethsys CK_ETH_WOCPU0_EN>,
developer77bbf432021-06-28 18:39:08 +0800423 <&sgmiisys0 CK_SGM0_TX_EN>,
424 <&sgmiisys0 CK_SGM0_RX_EN>,
425 <&sgmiisys0 CK_SGM0_CK0_EN>,
426 <&sgmiisys0 CK_SGM0_CDR_CK0_EN>,
427 <&sgmiisys1 CK_SGM1_TX_EN>,
428 <&sgmiisys1 CK_SGM1_RX_EN>,
429 <&sgmiisys1 CK_SGM1_CK1_EN>,
430 <&sgmiisys1 CK_SGM1_CDR_CK1_EN>;
developerfd40db22021-04-29 10:08:25 +0800431 clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
432 "sgmii_tx250m", "sgmii_rx250m",
433 "sgmii_cdr_ref", "sgmii_cdr_fb",
434 "sgmii2_tx250m", "sgmii2_rx250m",
435 "sgmii2_cdr_ref", "sgmii2_cdr_fb";
developer8b9f2852021-06-03 21:53:08 +0800436 assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>,
437 <&topckgen CK_TOP_SGM_325M_SEL>;
438 assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>,
439 <&topckgen CK_TOP_CB_SGM_325M>;
developerfd40db22021-04-29 10:08:25 +0800440 mediatek,ethsys = <&ethsys>;
441 mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
442 #reset-cells = <1>;
443 #address-cells = <1>;
444 #size-cells = <0>;
445 status = "disabled";
446 };
447
448 hnat: hnat@15000000 {
449 compatible = "mediatek,mtk-hnat_v4";
450 reg = <0 0x15100000 0 0x80000>;
451 resets = <&ethsys 0>;
452 reset-names = "mtketh";
453 status = "disabled";
454 };
455
456 sgmiisys0: syscon@10060000 {
developer15adbbf2021-05-24 22:20:07 +0800457 compatible = "mediatek,mt7986-sgmiisys",
458 "mediatek,mt7986-sgmiisys_0",
459 "syscon";
developerfd40db22021-04-29 10:08:25 +0800460 reg = <0 0x10060000 0 0x1000>;
461 #clock-cells = <1>;
462 };
463
464 sgmiisys1: syscon@10070000 {
developer15adbbf2021-05-24 22:20:07 +0800465 compatible = "mediatek,mt7986-sgmiisys",
466 "mediatek,mt7986-sgmiisys_1",
467 "syscon";
developerfd40db22021-04-29 10:08:25 +0800468 reg = <0 0x10070000 0 0x1000>;
469 #clock-cells = <1>;
470 };
471
472 snand: snfi@11005000 {
473 compatible = "mediatek,mt7986-snand";
474 reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>;
475 reg-names = "nfi", "ecc";
476 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
developer248c10b2021-07-14 16:11:19 +0800477 clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>,
478 <&infracfg_ao CK_INFRA_NFI1_CK>,
479 <&infracfg_ao CK_INFRA_NFI_HCK_CK>;
480 clock-names = "pad_clk", "nfi_clk", "nfi_hclk";
developer8b9f2852021-06-03 21:53:08 +0800481 assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>,
482 <&topckgen CK_TOP_NFI1X_SEL>;
developere5562612021-08-05 15:50:40 +0800483 assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>,
484 <&topckgen CK_TOP_CB_M_D8>;
developerfd40db22021-04-29 10:08:25 +0800485 #address-cells = <1>;
486 #size-cells = <0>;
487 status = "disabled";
488 };
489
490 wbsys: wbsys@18000000 {
developereb527ef2022-01-12 10:38:12 +0800491 compatible = "mediatek,wbsys",
492 "mediatek,mt7986-wmac";
developere138bcd2021-12-06 09:20:47 +0800493 resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>;
494 reset-names = "consys";
495 reg = <0 0x18000000 0 0x1000000>,
496 <0 0x10003000 0 0x1000>,
497 <0 0x11d1000 0 0x1000>;
developerfd40db22021-04-29 10:08:25 +0800498 interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
499 <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
500 <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
501 <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
502 chip_id = <0x7986>;
developere138bcd2021-12-06 09:20:47 +0800503 memory-region = <&wmcpu_emi>;
developerfd40db22021-04-29 10:08:25 +0800504 };
505
506 wed_pcie: wed_pcie@10003000 {
507 compatible = "mediatek,wed_pcie";
508 reg = <0 0x10003000 0 0x10>;
509 };
510
511 spi0: spi@1100a000 {
developer44700a22021-07-13 19:06:49 +0800512 compatible = "mediatek,ipm-spi-quad";
developerfd40db22021-04-29 10:08:25 +0800513 reg = <0 0x1100a000 0 0x100>;
514 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
developer8b9f2852021-06-03 21:53:08 +0800515 clocks = <&topckgen CK_TOP_CB_M_D2>,
developer44700a22021-07-13 19:06:49 +0800516 <&topckgen CK_TOP_SPI_SEL>,
developer8b9f2852021-06-03 21:53:08 +0800517 <&infracfg_ao CK_INFRA_SPI0_CK>,
developer44700a22021-07-13 19:06:49 +0800518 <&infracfg_ao CK_INFRA_SPI0_HCK_CK>;
519 clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
developerfd40db22021-04-29 10:08:25 +0800520 status = "disabled";
521 };
522
523 spi1: spi@1100b000 {
developer44700a22021-07-13 19:06:49 +0800524 compatible = "mediatek,ipm-spi-single";
developerfd40db22021-04-29 10:08:25 +0800525 reg = <0 0x1100b000 0 0x100>;
526 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
developer8b9f2852021-06-03 21:53:08 +0800527 clocks = <&topckgen CK_TOP_CB_M_D2>,
developer44700a22021-07-13 19:06:49 +0800528 <&topckgen CK_TOP_SPIM_MST_SEL>,
developer8b9f2852021-06-03 21:53:08 +0800529 <&infracfg_ao CK_INFRA_SPI1_CK>,
developer44700a22021-07-13 19:06:49 +0800530 <&infracfg_ao CK_INFRA_SPI1_HCK_CK>;
531 clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk";
developerfd40db22021-04-29 10:08:25 +0800532 status = "disabled";
533 };
534
developer637f5552021-05-27 17:45:27 +0800535 mmc0: mmc@11230000 {
536 compatible = "mediatek,mt7986-mmc";
537 reg = <0 0x11230000 0 0x1000>,
538 <0 0x11c20000 0 0x1000>;
539 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
developer8b9f2852021-06-03 21:53:08 +0800540 clocks = <&topckgen CK_TOP_EMMC_416M>,
541 <&topckgen CK_TOP_EMMC_250M>,
542 <&infracfg_ao CK_INFRA_MSDC_CK>;
developer637f5552021-05-27 17:45:27 +0800543 clock-names = "source", "hclk", "source_cg";
developer8b9f2852021-06-03 21:53:08 +0800544 assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>,
545 <&topckgen CK_TOP_EMMC_250M_SEL>;
developerf089cc02021-09-11 17:23:41 +0800546 assigned-clock-parents = <&topckgen CK_TOP_CB_M_416M>,
547 <&topckgen CK_TOP_NET1_D5_D2>;
developer637f5552021-05-27 17:45:27 +0800548 status = "disabled";
549 };
550
developeree2df732021-05-21 15:19:42 +0800551 auxadc: adc@1100d000 {
552 compatible = "mediatek,mt7986-auxadc",
553 "mediatek,mt7622-auxadc";
554 reg = <0 0x1100d000 0 0x1000>;
developer2cdfa052021-08-12 10:41:52 +0800555 clocks = <&infracfg_ao CK_INFRA_ADC_26M_CK>,
556 <&infracfg_ao CK_INFRA_ADC_FRC_CK>;
557 clock-names = "main", "32k";
developeree2df732021-05-21 15:19:42 +0800558 #io-channel-cells = <1>;
developer8b9f2852021-06-03 21:53:08 +0800559 status = "disabled";
developeree2df732021-05-21 15:19:42 +0800560 };
561
developerfd40db22021-04-29 10:08:25 +0800562 consys: consys@10000000 {
563 compatible = "mediatek,mt7986-consys";
564 reg = <0 0x10000000 0 0x8600000>;
565 memory-region = <&wmcpu_emi>;
566 };
567
568 xhci: xhci@11200000 {
569 compatible = "mediatek,mt7986-xhci",
570 "mediatek,mtk-xhci";
571 reg = <0 0x11200000 0 0x2e00>,
572 <0 0x11203e00 0 0x0100>;
573 reg-names = "mac", "ippc";
574 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
575 phys = <&u2port0 PHY_TYPE_USB2>,
576 <&u3port0 PHY_TYPE_USB3>,
577 <&u2port1 PHY_TYPE_USB2>;
578 clocks = <&system_clk>,
579 <&system_clk>,
580 <&system_clk>,
581 <&system_clk>,
582 <&system_clk>;
583 clock-names = "sys_ck",
584 "xhci_ck",
585 "ref_ck",
586 "mcu_ck",
587 "dma_ck";
588 #address-cells = <2>;
589 #size-cells = <2>;
developer604b5ac2021-12-30 14:35:44 +0800590 status = "okay";
591 };
592
593 pcietphy: pcie-phy@11c00000 {
594 compatible = "mediatek,mt7986",
595 "mediatek,generic-tphy-v2";
596 #address-cells = <2>;
597 #size-cells = <2>;
598 ranges;
developerfd40db22021-04-29 10:08:25 +0800599 status = "okay";
developer604b5ac2021-12-30 14:35:44 +0800600
601 pcieport: pcie-phy@11c00000 {
602 reg = <0 0x11c00000 0 0x20000>;
603 clocks = <&system_clk>;
604 clock-names = "ref";
605 #phy-cells = <1>;
606 status = "okay";
607 };
developerfd40db22021-04-29 10:08:25 +0800608 };
609
610 usbtphy: usb-phy@11e10000 {
611 compatible = "mediatek,mt7986",
612 "mediatek,generic-tphy-v2";
613 #address-cells = <2>;
614 #size-cells = <2>;
615 ranges;
616 status = "okay";
617
618 u2port0: usb-phy@11e10000 {
619 reg = <0 0x11e10000 0 0x700>;
620 clocks = <&system_clk>;
621 clock-names = "ref";
622 #phy-cells = <1>;
623 status = "okay";
624 };
625
626 u3port0: usb-phy@11e10700 {
627 reg = <0 0x11e10700 0 0x900>;
628 clocks = <&system_clk>;
629 clock-names = "ref";
630 #phy-cells = <1>;
631 status = "okay";
632 };
633
634 u2port1: usb-phy@11e11000 {
635 reg = <0 0x11e11000 0 0x700>;
636 clocks = <&system_clk>;
637 clock-names = "ref";
638 #phy-cells = <1>;
639 status = "okay";
640 };
641 };
developer15adbbf2021-05-24 22:20:07 +0800642
643 clkitg: clkitg {
644 compatible = "simple-bus";
645 };
developerfbbf02b2021-06-25 09:30:28 +0800646
developere1993bd2021-07-06 13:48:40 +0800647 afe: audio-controller@11210000 {
developerbe797a32021-12-16 16:56:09 +0800648 compatible = "mediatek,mt79xx-audio";
developere1993bd2021-07-06 13:48:40 +0800649 reg = <0 0x11210000 0 0x9000>;
650 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
651 clocks = <&infracfg_ao CK_INFRA_AUD_BUS_CK>,
652 <&infracfg_ao CK_INFRA_AUD_26M_CK>,
653 <&infracfg_ao CK_INFRA_AUD_L_CK>,
654 <&infracfg_ao CK_INFRA_AUD_AUD_CK>,
655 <&infracfg_ao CK_INFRA_AUD_EG2_CK>;
656 clock-names = "aud_bus_ck",
657 "aud_26m_ck",
658 "aud_l_ck",
659 "aud_aud_ck",
660 "aud_eg2_ck";
661 assigned-clocks = <&topckgen CK_TOP_A1SYS_SEL>,
662 <&topckgen CK_TOP_AUD_L_SEL>,
663 <&topckgen CK_TOP_A_TUNER_SEL>;
664 assigned-clock-parents = <&topckgen CK_TOP_APLL2_D4>,
665 <&topckgen CK_TOP_CB_APLL2_196M>,
666 <&topckgen CK_TOP_APLL2_D4>;
667 };
668
developerfbbf02b2021-06-25 09:30:28 +0800669 trng: trng@1020f000 {
670 compatible = "mediatek,mt7986-rng",
671 "mediatek,mt7623-rng";
672 reg = <0 0x1020f000 0 0x100>;
673 clocks = <&infracfg_ao CK_INFRA_TRNG_CK>;
674 clock-names = "rng";
675 };
developer86ee1e12021-06-30 11:18:53 +0800676
677 ice: ice_debug {
678 compatible = "mediatek,mt7986-ice_debug",
679 "mediatek,mt2701-ice_debug";
developer66b5c8d2021-07-16 14:02:47 +0800680 clocks = <&infracfg_ao CK_INFRA_DBG_CK>,
681 <&topckgen CK_TOP_ARM_DB_JTSEL>;
682 clock-names = "ice_dbg", "dbg_jtsel";
developer86ee1e12021-06-30 11:18:53 +0800683 };
developer3e9ad9d2021-07-01 16:42:25 +0800684
685 efuse: efuse@11d00000 {
686 compatible = "mediatek,mt7986-efuse",
687 "mediatek,efuse";
688 reg = <0 0x11d00000 0 0x1000>;
689 #address-cells = <1>;
690 #size-cells = <1>;
691
692 thermal_calibration: calib@274 {
693 reg = <0x274 0xc>;
694 };
695 };
developerfd40db22021-04-29 10:08:25 +0800696};
developer15adbbf2021-05-24 22:20:07 +0800697
developer8b9f2852021-06-03 21:53:08 +0800698#include "mt7986-clkitg.dtsi"