developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2020 MediaTek Inc. |
| 3 | * Author: Sam.Shih <sam.shih@mediatek.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License version 2 as |
| 7 | * published by the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <dt-bindings/interrupt-controller/irq.h> |
| 16 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 17 | #include <dt-bindings/phy/phy.h> |
| 18 | #include <dt-bindings/reset/ti-syscon.h> |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 19 | #include <dt-bindings/clock/mt7986-clk.h> |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 20 | #include <dt-bindings/thermal/thermal.h> |
developer | 7f4cdcd | 2021-08-03 19:29:43 +0800 | [diff] [blame] | 21 | #include <dt-bindings/pinctrl/mt65xx.h> |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 22 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 23 | / { |
| 24 | compatible = "mediatek,mt7986a-rfb"; |
| 25 | interrupt-parent = <&gic>; |
| 26 | #address-cells = <2>; |
| 27 | #size-cells = <2>; |
| 28 | cpus { |
| 29 | #address-cells = <1>; |
| 30 | #size-cells = <0>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 31 | cpu0: cpu@0 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 32 | device_type = "cpu"; |
| 33 | compatible = "arm,cortex-a53"; |
| 34 | enable-method = "psci"; |
| 35 | reg = <0x0>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 36 | #cooling-cells = <2>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 37 | }; |
| 38 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 39 | cpu1: cpu@1 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 40 | device_type = "cpu"; |
| 41 | compatible = "arm,cortex-a53"; |
| 42 | enable-method = "psci"; |
| 43 | reg = <0x1>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 44 | #cooling-cells = <2>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 45 | }; |
| 46 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 47 | cpu2: cpu@2 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 48 | device_type = "cpu"; |
| 49 | compatible = "arm,cortex-a53"; |
| 50 | enable-method = "psci"; |
| 51 | reg = <0x2>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 52 | #cooling-cells = <2>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 53 | }; |
| 54 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 55 | cpu3: cpu@3 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 56 | device_type = "cpu"; |
| 57 | enable-method = "psci"; |
| 58 | compatible = "arm,cortex-a53"; |
| 59 | reg = <0x3>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 60 | #cooling-cells = <2>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 61 | }; |
| 62 | }; |
| 63 | |
| 64 | wed: wed@15010000 { |
| 65 | compatible = "mediatek,wed"; |
| 66 | wed_num = <2>; |
| 67 | /* add this property for wed get the pci slot number. */ |
| 68 | pci_slot_map = <0>, <1>; |
| 69 | reg = <0 0x15010000 0 0x1000>, |
| 70 | <0 0x15011000 0 0x1000>; |
| 71 | interrupt-parent = <&gic>; |
| 72 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 73 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 74 | }; |
| 75 | |
| 76 | wed2: wed2@15011000 { |
| 77 | compatible = "mediatek,wed2"; |
| 78 | wed_num = <2>; |
| 79 | reg = <0 0x15010000 0 0x1000>, |
| 80 | <0 0x15011000 0 0x1000>; |
| 81 | interrupt-parent = <&gic>; |
| 82 | interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, |
| 83 | <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| 84 | }; |
| 85 | |
| 86 | wdma: wdma@15104800 { |
| 87 | compatible = "mediatek,wed-wdma"; |
| 88 | reg = <0 0x15104800 0 0x400>, |
| 89 | <0 0x15104c00 0 0x400>; |
| 90 | }; |
| 91 | |
| 92 | ap2woccif: ap2woccif@151A5000 { |
| 93 | compatible = "mediatek,ap2woccif"; |
| 94 | reg = <0 0x151A5000 0 0x1000>, |
| 95 | <0 0x151AD000 0 0x1000>; |
| 96 | interrupt-parent = <&gic>; |
| 97 | interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, |
| 98 | <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>; |
| 99 | }; |
| 100 | |
| 101 | wocpu0_ilm: wocpu0_ilm@151E0000 { |
| 102 | compatible = "mediatek,wocpu0_ilm"; |
| 103 | reg = <0 0x151E0000 0 0x8000>; |
| 104 | }; |
| 105 | |
| 106 | wocpu1_ilm: wocpu1_ilm@151F0000 { |
| 107 | compatible = "mediatek,wocpu1_ilm"; |
| 108 | reg = <0 0x151F0000 0 0x8000>; |
| 109 | }; |
| 110 | |
| 111 | wocpu_dlm: wocpu_dlm@151E8000 { |
| 112 | compatible = "mediatek,wocpu_dlm"; |
| 113 | reg = <0 0x151E8000 0 0x2000>, |
| 114 | <0 0x151F8000 0 0x2000>; |
| 115 | |
| 116 | resets = <ðsysrst 0>; |
| 117 | reset-names = "wocpu_rst"; |
| 118 | }; |
| 119 | |
| 120 | cpu_boot: wocpu_boot@15194000 { |
| 121 | compatible = "mediatek,wocpu_boot"; |
| 122 | reg = <0 0x15194000 0 0x1000>; |
| 123 | }; |
| 124 | |
| 125 | reserved-memory { |
| 126 | #address-cells = <2>; |
| 127 | #size-cells = <2>; |
| 128 | ranges; |
| 129 | |
| 130 | /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ |
| 131 | secmon_reserved: secmon@43000000 { |
| 132 | reg = <0 0x43000000 0 0x30000>; |
| 133 | no-map; |
| 134 | }; |
| 135 | |
| 136 | wmcpu_emi: wmcpu-reserved@4FC00000 { |
| 137 | compatible = "mediatek,wmcpu-reserved"; |
| 138 | no-map; |
| 139 | reg = <0 0x4FC00000 0 0x00100000>; |
| 140 | }; |
| 141 | |
| 142 | wocpu0_emi: wocpu0_emi@4FD00000 { |
| 143 | compatible = "mediatek,wocpu0_emi"; |
| 144 | no-map; |
| 145 | reg = <0 0x4FD00000 0 0x40000>; |
| 146 | shared = <0>; |
| 147 | }; |
| 148 | |
| 149 | wocpu1_emi: wocpu1_emi@4FD80000 { |
| 150 | compatible = "mediatek,wocpu1_emi"; |
| 151 | no-map; |
| 152 | reg = <0 0x4FD40000 0 0x40000>; |
| 153 | shared = <0>; |
| 154 | }; |
| 155 | |
| 156 | wocpu_data: wocpu_data@4FE00000 { |
| 157 | compatible = "mediatek,wocpu_data"; |
| 158 | no-map; |
developer | 8be272e | 2021-07-29 13:15:07 +0800 | [diff] [blame] | 159 | reg = <0 0x4FD80000 0 0x240000>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 160 | shared = <1>; |
| 161 | }; |
| 162 | }; |
| 163 | |
| 164 | psci { |
| 165 | compatible = "arm,psci-0.2"; |
| 166 | method = "smc"; |
| 167 | }; |
| 168 | |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 169 | clk40m: oscillator@0 { |
| 170 | compatible = "fixed-clock"; |
| 171 | #clock-cells = <0>; |
| 172 | clock-frequency = <40000000>; |
| 173 | clock-output-names = "clkxtal"; |
| 174 | }; |
| 175 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 176 | system_clk: dummy_system_clk { |
| 177 | compatible = "fixed-clock"; |
| 178 | clock-frequency = <40000000>; |
| 179 | #clock-cells = <0>; |
| 180 | }; |
| 181 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 182 | timer { |
| 183 | compatible = "arm,armv8-timer"; |
| 184 | interrupt-parent = <&gic>; |
developer | f39022a | 2021-05-06 13:31:52 +0800 | [diff] [blame] | 185 | clock-frequency = <13000000>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 186 | interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, |
| 187 | <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, |
| 188 | <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, |
| 189 | <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 190 | }; |
| 191 | |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 192 | infracfg_ao: infracfg_ao@10001000 { |
| 193 | compatible = "mediatek,mt7986-infracfg_ao", "syscon"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 194 | reg = <0 0x10001000 0 0x68>; |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 195 | #clock-cells = <1>; |
| 196 | }; |
| 197 | |
| 198 | infracfg: infracfg@10001040 { |
| 199 | compatible = "mediatek,mt7986-infracfg", "syscon"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 200 | reg = <0 0x1000106c 0 0x1000>; |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 201 | #clock-cells = <1>; |
| 202 | }; |
| 203 | |
| 204 | topckgen: topckgen@1001B000 { |
| 205 | compatible = "mediatek,mt7986-topckgen", "syscon"; |
| 206 | reg = <0 0x1001B000 0 0x1000>; |
| 207 | #clock-cells = <1>; |
| 208 | }; |
| 209 | |
| 210 | apmixedsys: apmixedsys@1001E000 { |
| 211 | compatible = "mediatek,mt7986-apmixedsys", "syscon"; |
| 212 | reg = <0 0x1001E000 0 0x1000>; |
| 213 | #clock-cells = <1>; |
| 214 | }; |
| 215 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 216 | watchdog: watchdog@1001c000 { |
| 217 | compatible = "mediatek,mt7622-wdt", |
| 218 | "mediatek,mt6589-wdt"; |
| 219 | reg = <0 0x1001c000 0 0x1000>; |
| 220 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 221 | #reset-cells = <1>; |
| 222 | }; |
| 223 | |
| 224 | gic: interrupt-controller@c000000 { |
| 225 | compatible = "arm,gic-v3"; |
| 226 | #interrupt-cells = <3>; |
| 227 | interrupt-parent = <&gic>; |
| 228 | interrupt-controller; |
| 229 | reg = <0 0x0c000000 0 0x40000>, /* GICD */ |
| 230 | <0 0x0c080000 0 0x200000>; /* GICR */ |
| 231 | |
| 232 | interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| 233 | }; |
| 234 | |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 235 | pwm: pwm@10048000 { |
| 236 | compatible = "mediatek,mt7986-pwm"; |
| 237 | reg = <0 0x10048000 0 0x1000>; |
| 238 | #clock-cells = <1>; |
| 239 | #pwm-cells = <2>; |
| 240 | interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; |
| 241 | clocks = <&infracfg CK_INFRA_PWM>, |
| 242 | <&infracfg_ao CK_INFRA_PWM_BSEL>, |
| 243 | <&infracfg_ao CK_INFRA_PWM1_CK>, |
| 244 | <&infracfg_ao CK_INFRA_PWM2_CK>; |
| 245 | assigned-clocks = <&topckgen CK_TOP_PWM_SEL>, |
| 246 | <&infracfg_ao CK_INFRA_PWM_BSEL>, |
| 247 | <&infracfg_ao CK_INFRA_PWM1_SEL>, |
| 248 | <&infracfg_ao CK_INFRA_PWM2_SEL>; |
| 249 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_D4>, |
| 250 | <&infracfg CK_INFRA_PWM>, |
| 251 | <&infracfg CK_INFRA_PWM>, |
| 252 | <&infracfg CK_INFRA_PWM>; |
| 253 | clock-names = "top", "main", "pwm1", "pwm2"; |
| 254 | status = "disabled"; |
| 255 | }; |
| 256 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 257 | uart0: serial@11002000 { |
| 258 | compatible = "mediatek,mt7986-uart", |
| 259 | "mediatek,mt6577-uart"; |
| 260 | reg = <0 0x11002000 0 0x400>; |
| 261 | interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 262 | clocks = <&infracfg_ao CK_INFRA_UART0_CK>; |
| 263 | assigned-clocks = <&topckgen CK_TOP_UART_SEL>, |
| 264 | <&infracfg_ao CK_INFRA_UART0_SEL>; |
| 265 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 266 | <&infracfg CK_INFRA_UART>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 267 | status = "disabled"; |
| 268 | }; |
| 269 | |
| 270 | uart1: serial@11003000 { |
| 271 | compatible = "mediatek,mt7986-uart", |
| 272 | "mediatek,mt6577-uart"; |
| 273 | reg = <0 0x11003000 0 0x400>; |
| 274 | interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 275 | clocks = <&infracfg_ao CK_INFRA_UART1_CK>; |
| 276 | assigned-clocks = <&infracfg_ao CK_INFRA_UART1_SEL>; |
| 277 | assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 278 | status = "disabled"; |
| 279 | }; |
| 280 | |
| 281 | uart2: serial@11004000 { |
| 282 | compatible = "mediatek,mt7986-uart", |
| 283 | "mediatek,mt6577-uart"; |
| 284 | reg = <0 0x11004000 0 0x400>; |
| 285 | interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 286 | clocks = <&infracfg_ao CK_INFRA_UART2_CK>; |
| 287 | assigned-clocks = <&infracfg_ao CK_INFRA_UART2_SEL>; |
| 288 | assigned-clock-parents = <&infracfg CK_INFRA_CK_F26M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 289 | status = "disabled"; |
| 290 | }; |
| 291 | |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 292 | i2c0: i2c@11008000 { |
| 293 | compatible = "mediatek,mt7986-i2c"; |
| 294 | reg = <0 0x11008000 0 0x90>, |
| 295 | <0 0x10217080 0 0x80>; |
| 296 | interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| 297 | clock-div = <16>; |
| 298 | clocks = <&infracfg_ao CK_INFRA_I2CO_CK>, |
| 299 | <&infracfg_ao CK_INFRA_AP_DMA_CK>; |
| 300 | clock-names = "main", "dma"; |
| 301 | #address-cells = <1>; |
| 302 | #size-cells = <0>; |
| 303 | status = "disabled"; |
| 304 | }; |
| 305 | |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 306 | thermal-zones { |
| 307 | cpu_thermal: cpu-thermal { |
| 308 | polling-delay-passive = <1000>; |
| 309 | polling-delay = <1000>; |
| 310 | thermal-sensors = <&thermal 0>; |
| 311 | |
| 312 | trips { |
| 313 | cpu_passive: cpu-passive { |
| 314 | temperature = <47000>; |
| 315 | hysteresis = <2000>; |
| 316 | type = "passive"; |
| 317 | }; |
| 318 | |
| 319 | cpu_active: cpu-active { |
| 320 | temperature = <67000>; |
| 321 | hysteresis = <2000>; |
| 322 | type = "active"; |
| 323 | }; |
| 324 | |
| 325 | cpu_hot: cpu-hot { |
| 326 | temperature = <87000>; |
| 327 | hysteresis = <2000>; |
| 328 | type = "hot"; |
| 329 | }; |
| 330 | |
| 331 | cpu-crit { |
| 332 | temperature = <107000>; |
| 333 | hysteresis = <2000>; |
| 334 | type = "critical"; |
| 335 | }; |
| 336 | }; |
| 337 | |
| 338 | cooling-maps { |
| 339 | map0 { |
| 340 | trip = <&cpu_passive>; |
| 341 | cooling-device = <&cpu0 |
| 342 | THERMAL_NO_LIMIT |
| 343 | THERMAL_NO_LIMIT>, |
| 344 | <&cpu1 |
| 345 | THERMAL_NO_LIMIT |
| 346 | THERMAL_NO_LIMIT>, |
| 347 | <&cpu2 |
| 348 | THERMAL_NO_LIMIT |
| 349 | THERMAL_NO_LIMIT>, |
| 350 | <&cpu3 |
| 351 | THERMAL_NO_LIMIT |
| 352 | THERMAL_NO_LIMIT>; |
| 353 | }; |
| 354 | |
| 355 | map1 { |
| 356 | trip = <&cpu_active>; |
| 357 | cooling-device = <&cpu0 |
| 358 | THERMAL_NO_LIMIT |
| 359 | THERMAL_NO_LIMIT>, |
| 360 | <&cpu1 |
| 361 | THERMAL_NO_LIMIT |
| 362 | THERMAL_NO_LIMIT>, |
| 363 | <&cpu2 |
| 364 | THERMAL_NO_LIMIT |
| 365 | THERMAL_NO_LIMIT>, |
| 366 | <&cpu3 |
| 367 | THERMAL_NO_LIMIT |
| 368 | THERMAL_NO_LIMIT>; |
| 369 | }; |
| 370 | |
| 371 | map2 { |
| 372 | trip = <&cpu_hot>; |
| 373 | cooling-device = <&cpu0 |
| 374 | THERMAL_NO_LIMIT |
| 375 | THERMAL_NO_LIMIT>, |
| 376 | <&cpu1 |
| 377 | THERMAL_NO_LIMIT |
| 378 | THERMAL_NO_LIMIT>, |
| 379 | <&cpu2 |
| 380 | THERMAL_NO_LIMIT |
| 381 | THERMAL_NO_LIMIT>, |
| 382 | <&cpu3 |
| 383 | THERMAL_NO_LIMIT |
| 384 | THERMAL_NO_LIMIT>; |
| 385 | }; |
| 386 | }; |
| 387 | }; |
| 388 | }; |
| 389 | |
| 390 | thermal: thermal@1100c800 { |
| 391 | #thermal-sensor-cells = <1>; |
| 392 | compatible = "mediatek,mt7986-thermal"; |
developer | 4173d3c | 2021-08-12 11:21:49 +0800 | [diff] [blame^] | 393 | reg = <0 0x1100c800 0 0x800>; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 394 | interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; |
| 395 | clocks = <&infracfg_ao CK_INFRA_THERM_CK>, |
| 396 | <&infracfg_ao CK_INFRA_ADC_26M_CK>; |
| 397 | clock-names = "therm", "auxadc"; |
| 398 | mediatek,auxadc = <&auxadc>; |
| 399 | mediatek,apmixedsys = <&apmixedsys>; |
| 400 | nvmem-cells = <&thermal_calibration>; |
| 401 | nvmem-cell-names = "calibration-data"; |
| 402 | }; |
| 403 | |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 404 | pcie0: pcie@11280000 { |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 405 | compatible = "mediatek,mt7986-pcie"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 406 | reg = <0 0x11280000 0 0x5000>; |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 407 | reg-names = "pcie-mac"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 408 | #address-cells = <3>; |
| 409 | #size-cells = <2>; |
| 410 | interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>; |
| 411 | bus-range = <0x00 0xff>; |
| 412 | ranges = <0x82000000 0 0x20000000 |
| 413 | 0x0 0x20000000 0 0x10000000>; |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 414 | status = "disabled"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 415 | |
developer | e2ed434 | 2021-07-02 16:04:23 +0800 | [diff] [blame] | 416 | clocks = <&infracfg_ao CK_INFRA_PCIE_SEL>, |
| 417 | <&infracfg_ao CK_INFRA_IPCIE_CK>, |
| 418 | <&infracfg_ao CK_INFRA_IPCIE_PIPE_CK>, |
| 419 | <&infracfg_ao CK_INFRA_IPCIER_CK>, |
| 420 | <&infracfg_ao CK_INFRA_IPCIEB_CK>; |
| 421 | |
| 422 | #interrupt-cells = <1>; |
| 423 | interrupt-map-mask = <0 0 0 7>; |
| 424 | interrupt-map = <0 0 0 1 &pcie_intc0 0>, |
| 425 | <0 0 0 2 &pcie_intc0 1>, |
| 426 | <0 0 0 3 &pcie_intc0 2>, |
| 427 | <0 0 0 4 &pcie_intc0 3>; |
| 428 | pcie_intc0: interrupt-controller { |
| 429 | interrupt-controller; |
| 430 | #address-cells = <0>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 431 | #interrupt-cells = <1>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 432 | }; |
| 433 | }; |
| 434 | |
developer | 3e91642 | 2021-05-27 16:40:29 +0800 | [diff] [blame] | 435 | crypto: crypto@10320000 { |
| 436 | compatible = "inside-secure,safexcel-eip97"; |
| 437 | reg = <0 0x10320000 0 0x40000>; |
| 438 | interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, |
| 439 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, |
| 440 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, |
| 441 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; |
| 442 | interrupt-names = "ring0", "ring1", "ring2", "ring3"; |
developer | e1993bd | 2021-07-06 13:48:40 +0800 | [diff] [blame] | 443 | clocks = <&infracfg_ao CK_INFRA_EIP97_CK>; |
| 444 | clock-names = "infra_eip97_ck"; |
| 445 | assigned-clocks = <&topckgen CK_TOP_EIP_B_SEL>; |
| 446 | assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>; |
developer | 3e91642 | 2021-05-27 16:40:29 +0800 | [diff] [blame] | 447 | }; |
| 448 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 449 | pio: pinctrl@1001f000 { |
| 450 | compatible = "mediatek,mt7986-pinctrl"; |
| 451 | reg = <0 0x1001f000 0 0x1000>, |
| 452 | <0 0x11c30000 0 0x1000>, |
| 453 | <0 0x11c40000 0 0x1000>, |
| 454 | <0 0x11e20000 0 0x1000>, |
| 455 | <0 0x11e30000 0 0x1000>, |
| 456 | <0 0x11f00000 0 0x1000>, |
| 457 | <0 0x11f10000 0 0x1000>, |
| 458 | <0 0x1000b000 0 0x1000>; |
| 459 | reg-names = "gpio_base", "iocfg_rt_base", "iocfg_rb_base", |
| 460 | "iocfg_lt_base", "iocfg_lb_base", "iocfg_tr_base", |
| 461 | "iocfg_tl_base", "eint"; |
| 462 | gpio-controller; |
| 463 | #gpio-cells = <2>; |
| 464 | gpio-ranges = <&pio 0 0 100>; |
| 465 | interrupt-controller; |
developer | a7f8fa4 | 2021-06-07 16:46:34 +0800 | [diff] [blame] | 466 | interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 467 | interrupt-parent = <&gic>; |
| 468 | #interrupt-cells = <2>; |
| 469 | }; |
| 470 | |
| 471 | ethsys: syscon@15000000 { |
| 472 | #address-cells = <1>; |
| 473 | #size-cells = <1>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 474 | compatible = "mediatek,mt7986-ethsys_ck", |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 475 | "syscon"; |
| 476 | reg = <0 0x15000000 0 0x1000>; |
| 477 | #clock-cells = <1>; |
| 478 | #reset-cells = <1>; |
| 479 | |
| 480 | ethsysrst: reset-controller { |
| 481 | compatible = "ti,syscon-reset"; |
| 482 | #reset-cells = <1>; |
| 483 | ti,reset-bits = <0x34 4 0x34 4 0x34 4 (ASSERT_SET | DEASSERT_CLEAR | STATUS_SET)>; |
| 484 | }; |
| 485 | }; |
| 486 | |
| 487 | eth: ethernet@15100000 { |
| 488 | compatible = "mediatek,mt7986-eth"; |
| 489 | reg = <0 0x15100000 0 0x80000>; |
| 490 | interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, |
| 491 | <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, |
| 492 | <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, |
| 493 | <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 494 | clocks = <ðsys CK_ETH_FE_EN>, |
| 495 | <ðsys CK_ETH_GP2_EN>, |
| 496 | <ðsys CK_ETH_GP1_EN>, |
| 497 | <ðsys CK_ETH_WOCPU1_EN>, |
| 498 | <ðsys CK_ETH_WOCPU0_EN>, |
developer | 77bbf43 | 2021-06-28 18:39:08 +0800 | [diff] [blame] | 499 | <&sgmiisys0 CK_SGM0_TX_EN>, |
| 500 | <&sgmiisys0 CK_SGM0_RX_EN>, |
| 501 | <&sgmiisys0 CK_SGM0_CK0_EN>, |
| 502 | <&sgmiisys0 CK_SGM0_CDR_CK0_EN>, |
| 503 | <&sgmiisys1 CK_SGM1_TX_EN>, |
| 504 | <&sgmiisys1 CK_SGM1_RX_EN>, |
| 505 | <&sgmiisys1 CK_SGM1_CK1_EN>, |
| 506 | <&sgmiisys1 CK_SGM1_CDR_CK1_EN>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 507 | clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", |
| 508 | "sgmii_tx250m", "sgmii_rx250m", |
| 509 | "sgmii_cdr_ref", "sgmii_cdr_fb", |
| 510 | "sgmii2_tx250m", "sgmii2_rx250m", |
| 511 | "sgmii2_cdr_ref", "sgmii2_cdr_fb"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 512 | assigned-clocks = <&topckgen CK_TOP_NETSYS_2X_SEL>, |
| 513 | <&topckgen CK_TOP_SGM_325M_SEL>; |
| 514 | assigned-clock-parents = <&topckgen CK_TOP_CB_NET2_800M>, |
| 515 | <&topckgen CK_TOP_CB_SGM_325M>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 516 | mediatek,ethsys = <ðsys>; |
| 517 | mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; |
| 518 | #reset-cells = <1>; |
| 519 | #address-cells = <1>; |
| 520 | #size-cells = <0>; |
| 521 | status = "disabled"; |
| 522 | }; |
| 523 | |
| 524 | hnat: hnat@15000000 { |
| 525 | compatible = "mediatek,mtk-hnat_v4"; |
| 526 | reg = <0 0x15100000 0 0x80000>; |
| 527 | resets = <ðsys 0>; |
| 528 | reset-names = "mtketh"; |
| 529 | status = "disabled"; |
| 530 | }; |
| 531 | |
| 532 | sgmiisys0: syscon@10060000 { |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 533 | compatible = "mediatek,mt7986-sgmiisys", |
| 534 | "mediatek,mt7986-sgmiisys_0", |
| 535 | "syscon"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 536 | reg = <0 0x10060000 0 0x1000>; |
| 537 | #clock-cells = <1>; |
| 538 | }; |
| 539 | |
| 540 | sgmiisys1: syscon@10070000 { |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 541 | compatible = "mediatek,mt7986-sgmiisys", |
| 542 | "mediatek,mt7986-sgmiisys_1", |
| 543 | "syscon"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 544 | reg = <0 0x10070000 0 0x1000>; |
| 545 | #clock-cells = <1>; |
| 546 | }; |
| 547 | |
| 548 | snand: snfi@11005000 { |
| 549 | compatible = "mediatek,mt7986-snand"; |
| 550 | reg = <0 0x11005000 0 0x1000>, <0 0x11006000 0 0x1000>; |
| 551 | reg-names = "nfi", "ecc"; |
| 552 | interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; |
developer | 248c10b | 2021-07-14 16:11:19 +0800 | [diff] [blame] | 553 | clocks = <&infracfg_ao CK_INFRA_SPINFI1_CK>, |
| 554 | <&infracfg_ao CK_INFRA_NFI1_CK>, |
| 555 | <&infracfg_ao CK_INFRA_NFI_HCK_CK>; |
| 556 | clock-names = "pad_clk", "nfi_clk", "nfi_hclk"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 557 | assigned-clocks = <&topckgen CK_TOP_SPINFI_SEL>, |
| 558 | <&topckgen CK_TOP_NFI1X_SEL>; |
developer | e556261 | 2021-08-05 15:50:40 +0800 | [diff] [blame] | 559 | assigned-clock-parents = <&topckgen CK_TOP_CB_M_D8>, |
| 560 | <&topckgen CK_TOP_CB_M_D8>; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 561 | #address-cells = <1>; |
| 562 | #size-cells = <0>; |
| 563 | status = "disabled"; |
| 564 | }; |
| 565 | |
| 566 | wbsys: wbsys@18000000 { |
| 567 | compatible = "mediatek,wbsys"; |
| 568 | reg = <0 0x18000000 0 0x1000000>; |
| 569 | interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, |
| 570 | <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, |
| 571 | <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, |
| 572 | <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; |
| 573 | chip_id = <0x7986>; |
| 574 | }; |
| 575 | |
| 576 | wed_pcie: wed_pcie@10003000 { |
| 577 | compatible = "mediatek,wed_pcie"; |
| 578 | reg = <0 0x10003000 0 0x10>; |
| 579 | }; |
| 580 | |
| 581 | spi0: spi@1100a000 { |
developer | 44700a2 | 2021-07-13 19:06:49 +0800 | [diff] [blame] | 582 | compatible = "mediatek,ipm-spi-quad"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 583 | reg = <0 0x1100a000 0 0x100>; |
| 584 | interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 585 | clocks = <&topckgen CK_TOP_CB_M_D2>, |
developer | 44700a2 | 2021-07-13 19:06:49 +0800 | [diff] [blame] | 586 | <&topckgen CK_TOP_SPI_SEL>, |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 587 | <&infracfg_ao CK_INFRA_SPI0_CK>, |
developer | 44700a2 | 2021-07-13 19:06:49 +0800 | [diff] [blame] | 588 | <&infracfg_ao CK_INFRA_SPI0_HCK_CK>; |
| 589 | clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 590 | status = "disabled"; |
| 591 | }; |
| 592 | |
| 593 | spi1: spi@1100b000 { |
developer | 44700a2 | 2021-07-13 19:06:49 +0800 | [diff] [blame] | 594 | compatible = "mediatek,ipm-spi-single"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 595 | reg = <0 0x1100b000 0 0x100>; |
| 596 | interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 597 | clocks = <&topckgen CK_TOP_CB_M_D2>, |
developer | 44700a2 | 2021-07-13 19:06:49 +0800 | [diff] [blame] | 598 | <&topckgen CK_TOP_SPIM_MST_SEL>, |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 599 | <&infracfg_ao CK_INFRA_SPI1_CK>, |
developer | 44700a2 | 2021-07-13 19:06:49 +0800 | [diff] [blame] | 600 | <&infracfg_ao CK_INFRA_SPI1_HCK_CK>; |
| 601 | clock-names = "parent-clk", "sel-clk", "spi-clk", "spi-hclk"; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 602 | status = "disabled"; |
| 603 | }; |
| 604 | |
developer | 637f555 | 2021-05-27 17:45:27 +0800 | [diff] [blame] | 605 | mmc0: mmc@11230000 { |
| 606 | compatible = "mediatek,mt7986-mmc"; |
| 607 | reg = <0 0x11230000 0 0x1000>, |
| 608 | <0 0x11c20000 0 0x1000>; |
| 609 | interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 610 | clocks = <&topckgen CK_TOP_EMMC_416M>, |
| 611 | <&topckgen CK_TOP_EMMC_250M>, |
| 612 | <&infracfg_ao CK_INFRA_MSDC_CK>; |
developer | 637f555 | 2021-05-27 17:45:27 +0800 | [diff] [blame] | 613 | clock-names = "source", "hclk", "source_cg"; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 614 | assigned-clocks = <&topckgen CK_TOP_EMMC_416M_SEL>, |
| 615 | <&topckgen CK_TOP_EMMC_250M_SEL>; |
| 616 | assigned-clock-parents = <&topckgen CK_TOP_CB_CKSQ_40M>, |
| 617 | <&topckgen CK_TOP_CB_CKSQ_40M>; |
developer | 637f555 | 2021-05-27 17:45:27 +0800 | [diff] [blame] | 618 | status = "disabled"; |
| 619 | }; |
| 620 | |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 621 | auxadc: adc@1100d000 { |
| 622 | compatible = "mediatek,mt7986-auxadc", |
| 623 | "mediatek,mt7622-auxadc"; |
| 624 | reg = <0 0x1100d000 0 0x1000>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 625 | clocks = <&infracfg_ao CK_INFRA_ADC_26M_CK>; |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 626 | clock-names = "main"; |
| 627 | #io-channel-cells = <1>; |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 628 | status = "disabled"; |
developer | ee2df73 | 2021-05-21 15:19:42 +0800 | [diff] [blame] | 629 | }; |
| 630 | |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 631 | consys: consys@10000000 { |
| 632 | compatible = "mediatek,mt7986-consys"; |
| 633 | reg = <0 0x10000000 0 0x8600000>; |
| 634 | memory-region = <&wmcpu_emi>; |
| 635 | }; |
| 636 | |
| 637 | xhci: xhci@11200000 { |
| 638 | compatible = "mediatek,mt7986-xhci", |
| 639 | "mediatek,mtk-xhci"; |
| 640 | reg = <0 0x11200000 0 0x2e00>, |
| 641 | <0 0x11203e00 0 0x0100>; |
| 642 | reg-names = "mac", "ippc"; |
| 643 | interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; |
| 644 | phys = <&u2port0 PHY_TYPE_USB2>, |
| 645 | <&u3port0 PHY_TYPE_USB3>, |
| 646 | <&u2port1 PHY_TYPE_USB2>; |
| 647 | clocks = <&system_clk>, |
| 648 | <&system_clk>, |
| 649 | <&system_clk>, |
| 650 | <&system_clk>, |
| 651 | <&system_clk>; |
| 652 | clock-names = "sys_ck", |
| 653 | "xhci_ck", |
| 654 | "ref_ck", |
| 655 | "mcu_ck", |
| 656 | "dma_ck"; |
| 657 | #address-cells = <2>; |
| 658 | #size-cells = <2>; |
| 659 | status = "okay"; |
| 660 | }; |
| 661 | |
| 662 | usbtphy: usb-phy@11e10000 { |
| 663 | compatible = "mediatek,mt7986", |
| 664 | "mediatek,generic-tphy-v2"; |
| 665 | #address-cells = <2>; |
| 666 | #size-cells = <2>; |
| 667 | ranges; |
| 668 | status = "okay"; |
| 669 | |
| 670 | u2port0: usb-phy@11e10000 { |
| 671 | reg = <0 0x11e10000 0 0x700>; |
| 672 | clocks = <&system_clk>; |
| 673 | clock-names = "ref"; |
| 674 | #phy-cells = <1>; |
| 675 | status = "okay"; |
| 676 | }; |
| 677 | |
| 678 | u3port0: usb-phy@11e10700 { |
| 679 | reg = <0 0x11e10700 0 0x900>; |
| 680 | clocks = <&system_clk>; |
| 681 | clock-names = "ref"; |
| 682 | #phy-cells = <1>; |
| 683 | status = "okay"; |
| 684 | }; |
| 685 | |
| 686 | u2port1: usb-phy@11e11000 { |
| 687 | reg = <0 0x11e11000 0 0x700>; |
| 688 | clocks = <&system_clk>; |
| 689 | clock-names = "ref"; |
| 690 | #phy-cells = <1>; |
| 691 | status = "okay"; |
| 692 | }; |
| 693 | }; |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 694 | |
| 695 | clkitg: clkitg { |
| 696 | compatible = "simple-bus"; |
| 697 | }; |
developer | fbbf02b | 2021-06-25 09:30:28 +0800 | [diff] [blame] | 698 | |
developer | e1993bd | 2021-07-06 13:48:40 +0800 | [diff] [blame] | 699 | afe: audio-controller@11210000 { |
| 700 | compatible = "mediatek,mt7986-audio"; |
| 701 | reg = <0 0x11210000 0 0x9000>; |
| 702 | interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; |
| 703 | clocks = <&infracfg_ao CK_INFRA_AUD_BUS_CK>, |
| 704 | <&infracfg_ao CK_INFRA_AUD_26M_CK>, |
| 705 | <&infracfg_ao CK_INFRA_AUD_L_CK>, |
| 706 | <&infracfg_ao CK_INFRA_AUD_AUD_CK>, |
| 707 | <&infracfg_ao CK_INFRA_AUD_EG2_CK>; |
| 708 | clock-names = "aud_bus_ck", |
| 709 | "aud_26m_ck", |
| 710 | "aud_l_ck", |
| 711 | "aud_aud_ck", |
| 712 | "aud_eg2_ck"; |
| 713 | assigned-clocks = <&topckgen CK_TOP_A1SYS_SEL>, |
| 714 | <&topckgen CK_TOP_AUD_L_SEL>, |
| 715 | <&topckgen CK_TOP_A_TUNER_SEL>; |
| 716 | assigned-clock-parents = <&topckgen CK_TOP_APLL2_D4>, |
| 717 | <&topckgen CK_TOP_CB_APLL2_196M>, |
| 718 | <&topckgen CK_TOP_APLL2_D4>; |
| 719 | }; |
| 720 | |
developer | fbbf02b | 2021-06-25 09:30:28 +0800 | [diff] [blame] | 721 | trng: trng@1020f000 { |
| 722 | compatible = "mediatek,mt7986-rng", |
| 723 | "mediatek,mt7623-rng"; |
| 724 | reg = <0 0x1020f000 0 0x100>; |
| 725 | clocks = <&infracfg_ao CK_INFRA_TRNG_CK>; |
| 726 | clock-names = "rng"; |
| 727 | }; |
developer | 86ee1e1 | 2021-06-30 11:18:53 +0800 | [diff] [blame] | 728 | |
| 729 | ice: ice_debug { |
| 730 | compatible = "mediatek,mt7986-ice_debug", |
| 731 | "mediatek,mt2701-ice_debug"; |
developer | 66b5c8d | 2021-07-16 14:02:47 +0800 | [diff] [blame] | 732 | clocks = <&infracfg_ao CK_INFRA_DBG_CK>, |
| 733 | <&topckgen CK_TOP_ARM_DB_JTSEL>; |
| 734 | clock-names = "ice_dbg", "dbg_jtsel"; |
developer | 86ee1e1 | 2021-06-30 11:18:53 +0800 | [diff] [blame] | 735 | }; |
developer | 3e9ad9d | 2021-07-01 16:42:25 +0800 | [diff] [blame] | 736 | |
| 737 | efuse: efuse@11d00000 { |
| 738 | compatible = "mediatek,mt7986-efuse", |
| 739 | "mediatek,efuse"; |
| 740 | reg = <0 0x11d00000 0 0x1000>; |
| 741 | #address-cells = <1>; |
| 742 | #size-cells = <1>; |
| 743 | |
| 744 | thermal_calibration: calib@274 { |
| 745 | reg = <0x274 0xc>; |
| 746 | }; |
| 747 | }; |
developer | fd40db2 | 2021-04-29 10:08:25 +0800 | [diff] [blame] | 748 | }; |
developer | 15adbbf | 2021-05-24 22:20:07 +0800 | [diff] [blame] | 749 | |
developer | 8b9f285 | 2021-06-03 21:53:08 +0800 | [diff] [blame] | 750 | #include "mt7986-clkitg.dtsi" |