Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 1 | if ARCH_STM32MP |
| 2 | |
| 3 | config SPL |
| 4 | select SPL_BOARD_INIT |
| 5 | select SPL_CLK |
| 6 | select SPL_DM |
| 7 | select SPL_DM_SEQ_ALIAS |
Patrick Delaunay | 636279a | 2018-07-09 15:17:21 +0200 | [diff] [blame] | 8 | select SPL_DRIVERS_MISC_SUPPORT |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 9 | select SPL_FRAMEWORK |
| 10 | select SPL_GPIO_SUPPORT |
| 11 | select SPL_LIBCOMMON_SUPPORT |
| 12 | select SPL_LIBGENERIC_SUPPORT |
| 13 | select SPL_OF_CONTROL |
| 14 | select SPL_OF_TRANSLATE |
| 15 | select SPL_PINCTRL |
| 16 | select SPL_REGMAP |
Ley Foon Tan | 9caf712 | 2018-06-14 18:45:19 +0800 | [diff] [blame] | 17 | select SPL_DM_RESET |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 18 | select SPL_SERIAL_SUPPORT |
Patrick Delaunay | fbe5457 | 2019-07-30 19:16:36 +0200 | [diff] [blame] | 19 | select SPL_SPI_LOAD |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 20 | select SPL_SYSCON |
Patrick Delaunay | 8bbadde | 2019-07-30 19:16:33 +0200 | [diff] [blame] | 21 | select SPL_WATCHDOG_SUPPORT if WATCHDOG |
Patrick Delaunay | f860020 | 2019-04-18 17:32:47 +0200 | [diff] [blame] | 22 | imply BOOTSTAGE_STASH if SPL_BOOTSTAGE |
| 23 | imply SPL_BOOTSTAGE if BOOTSTAGE |
Patrick Delaunay | aa4e685 | 2019-02-27 17:01:14 +0100 | [diff] [blame] | 24 | imply SPL_DISPLAY_PRINT |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 25 | imply SPL_LIBDISK_SUPPORT |
| 26 | |
| 27 | config SYS_SOC |
| 28 | default "stm32mp" |
| 29 | |
Patrick Delaunay | 7e517c6 | 2019-04-18 17:32:36 +0200 | [diff] [blame] | 30 | config SYS_MALLOC_LEN |
| 31 | default 0x2000000 |
| 32 | |
Patrick Delaunay | 088b676 | 2019-04-18 17:32:37 +0200 | [diff] [blame] | 33 | config ENV_SIZE |
Patrice Chotard | d83bba4 | 2019-05-07 18:40:47 +0200 | [diff] [blame] | 34 | default 0x2000 |
Patrick Delaunay | 088b676 | 2019-04-18 17:32:37 +0200 | [diff] [blame] | 35 | |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 36 | config TARGET_STM32MP1 |
| 37 | bool "Support stm32mp1xx" |
Patrick Delaunay | 5d06141 | 2019-02-12 11:44:39 +0100 | [diff] [blame] | 38 | select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED |
Lokesh Vutla | 81b1a67 | 2018-04-26 18:21:26 +0530 | [diff] [blame] | 39 | select CPU_V7A |
Patrick Delaunay | 5d06141 | 2019-02-12 11:44:39 +0100 | [diff] [blame] | 40 | select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED |
Patrick Delaunay | e020737 | 2018-04-16 10:13:24 +0200 | [diff] [blame] | 41 | select CPU_V7_HAS_VIRT |
Patrick Delaunay | de98cbf | 2019-07-02 13:26:07 +0200 | [diff] [blame] | 42 | select OF_BOARD_SETUP |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 43 | select PINCTRL_STM32 |
Patrick Delaunay | b139a5b | 2018-07-09 15:17:20 +0200 | [diff] [blame] | 44 | select STM32_RCC |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 45 | select STM32_RESET |
Patrick Delaunay | 4368e56 | 2019-07-30 19:16:25 +0200 | [diff] [blame] | 46 | select STM32_SERIAL |
Andre Przywara | 7b16925 | 2018-04-12 04:24:46 +0300 | [diff] [blame] | 47 | select SYS_ARCH_TIMER |
Patrick Delaunay | 9c07f4a | 2019-04-18 17:32:45 +0200 | [diff] [blame] | 48 | imply BOOTCOUNT_LIMIT |
Patrick Delaunay | f860020 | 2019-04-18 17:32:47 +0200 | [diff] [blame] | 49 | imply BOOTSTAGE |
Patrick Delaunay | 9c07f4a | 2019-04-18 17:32:45 +0200 | [diff] [blame] | 50 | imply CMD_BOOTCOUNT |
Patrick Delaunay | f860020 | 2019-04-18 17:32:47 +0200 | [diff] [blame] | 51 | imply CMD_BOOTSTAGE |
Patrick Delaunay | f97beae | 2019-12-03 09:38:58 +0100 | [diff] [blame^] | 52 | imply CMD_CLS if CMD_BMP |
Patrick Delaunay | 28a4609 | 2019-07-30 19:16:26 +0200 | [diff] [blame] | 53 | imply DISABLE_CONSOLE |
Patrick Delaunay | fcb4991 | 2019-07-30 19:16:23 +0200 | [diff] [blame] | 54 | imply PRE_CONSOLE_BUFFER |
Patrick Delaunay | 887d9e4 | 2019-07-30 19:16:22 +0200 | [diff] [blame] | 55 | imply SILENT_CONSOLE |
Patrick Delaunay | 5d06141 | 2019-02-12 11:44:39 +0100 | [diff] [blame] | 56 | imply SYSRESET_PSCI if STM32MP1_TRUSTED |
| 57 | imply SYSRESET_SYSCON if !STM32MP1_TRUSTED |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 58 | help |
| 59 | target STMicroelectronics SOC STM32MP1 family |
Patrick Delaunay | 6d3cbf3 | 2019-02-27 17:01:15 +0100 | [diff] [blame] | 60 | STM32MP157, STM32MP153 or STM32MP151 |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 61 | STMicroelectronics MPU with core ARMv7 |
Patrick Delaunay | 6d3cbf3 | 2019-02-27 17:01:15 +0100 | [diff] [blame] | 62 | dual core A7 for STM32MP157/3, monocore for STM32MP151 |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 63 | |
Patrick Delaunay | 5d06141 | 2019-02-12 11:44:39 +0100 | [diff] [blame] | 64 | config STM32MP1_TRUSTED |
| 65 | bool "Support trusted boot with TF-A" |
| 66 | default y if !SPL |
| 67 | select ARM_SMCCC |
| 68 | help |
| 69 | Say Y here to enable boot with TF-A |
| 70 | Trusted boot chain is : |
| 71 | BootRom => TF-A.stm32 (clock & DDR) => U-Boot.stm32 |
Patrick Delaunay | ff215a4 | 2019-07-02 13:26:06 +0200 | [diff] [blame] | 72 | TF-A monitor provides proprietary SMC to manage secure devices |
| 73 | |
| 74 | config STM32MP1_OPTEE |
| 75 | bool "Support trusted boot with TF-A and OP-TEE" |
| 76 | depends on STM32MP1_TRUSTED |
| 77 | default n |
| 78 | help |
| 79 | Say Y here to enable boot with TF-A and OP-TEE |
| 80 | Trusted boot chain is : |
| 81 | BootRom => TF-A.stm32 (clock & DDR) => OP-TEE => U-Boot.stm32 |
| 82 | OP-TEE monitor provides ST SMC to access to secure resources |
Patrick Delaunay | 5d06141 | 2019-02-12 11:44:39 +0100 | [diff] [blame] | 83 | |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 84 | config SYS_TEXT_BASE |
| 85 | prompt "U-Boot base address" |
| 86 | default 0xC0100000 |
| 87 | help |
| 88 | configure the U-Boot base address |
| 89 | when DDR driver is used: |
| 90 | DDR + 1MB (0xC0100000) |
| 91 | |
Patrick Delaunay | 6d3cbf3 | 2019-02-27 17:01:15 +0100 | [diff] [blame] | 92 | config NR_DRAM_BANKS |
| 93 | default 1 |
| 94 | |
Patrick Delaunay | fc69c68 | 2018-03-20 10:54:54 +0100 | [diff] [blame] | 95 | config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2 |
| 96 | hex "Partition on MMC2 to use to load U-Boot from" |
| 97 | depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION |
| 98 | default 1 |
| 99 | help |
| 100 | Partition on the second MMC to load U-Boot from when the MMC is being |
| 101 | used in raw mode |
| 102 | |
Patrick Delaunay | 43f214c | 2019-07-05 17:20:15 +0200 | [diff] [blame] | 103 | config STM32_ETZPC |
| 104 | bool "STM32 Extended TrustZone Protection" |
| 105 | depends on TARGET_STM32MP1 |
| 106 | default y |
| 107 | help |
| 108 | Say y to enable STM32 Extended TrustZone Protection |
| 109 | |
Patrick Delaunay | 109d13f | 2019-07-05 17:20:17 +0200 | [diff] [blame] | 110 | config CMD_STM32KEY |
| 111 | bool "command stm32key to fuse public key hash" |
| 112 | default y |
| 113 | depends on CMD_FUSE |
| 114 | help |
| 115 | fuse public key hash in corresponding fuse used to authenticate |
| 116 | binary. |
| 117 | |
Patrick Delaunay | fcb4991 | 2019-07-30 19:16:23 +0200 | [diff] [blame] | 118 | |
| 119 | config PRE_CON_BUF_ADDR |
| 120 | default 0xC02FF000 |
| 121 | |
| 122 | config PRE_CON_BUF_SZ |
| 123 | default 4096 |
| 124 | |
Patrick Delaunay | f860020 | 2019-04-18 17:32:47 +0200 | [diff] [blame] | 125 | config BOOTSTAGE_STASH_ADDR |
| 126 | default 0xC3000000 |
| 127 | |
Patrick Delaunay | 9c07f4a | 2019-04-18 17:32:45 +0200 | [diff] [blame] | 128 | if BOOTCOUNT_LIMIT |
| 129 | config SYS_BOOTCOUNT_SINGLEWORD |
| 130 | default y |
| 131 | |
| 132 | # TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21) |
| 133 | config SYS_BOOTCOUNT_ADDR |
| 134 | default 0x5C00A154 |
| 135 | endif |
| 136 | |
Patrick Delaunay | 82168e8 | 2018-05-17 14:50:46 +0200 | [diff] [blame] | 137 | if DEBUG_UART |
| 138 | |
| 139 | config DEBUG_UART_BOARD_INIT |
| 140 | default y |
| 141 | |
| 142 | # debug on UART4 by default |
| 143 | config DEBUG_UART_BASE |
| 144 | default 0x40010000 |
| 145 | |
| 146 | # clock source is HSI on reset |
| 147 | config DEBUG_UART_CLOCK |
| 148 | default 64000000 |
| 149 | endif |
| 150 | |
Patrick Delaunay | 6d3cbf3 | 2019-02-27 17:01:15 +0100 | [diff] [blame] | 151 | source "board/st/stm32mp1/Kconfig" |
| 152 | |
Patrick Delaunay | 85b5397 | 2018-03-12 10:46:10 +0100 | [diff] [blame] | 153 | endif |