blob: abceeded24a250622d1b32b0396c9157fae1e06b [file] [log] [blame]
Patrick Delaunay85b53972018-03-12 10:46:10 +01001if ARCH_STM32MP
2
3config SPL
4 select SPL_BOARD_INIT
5 select SPL_CLK
6 select SPL_DM
7 select SPL_DM_SEQ_ALIAS
8 select SPL_FRAMEWORK
9 select SPL_GPIO_SUPPORT
10 select SPL_LIBCOMMON_SUPPORT
11 select SPL_LIBGENERIC_SUPPORT
12 select SPL_OF_CONTROL
13 select SPL_OF_TRANSLATE
14 select SPL_PINCTRL
15 select SPL_REGMAP
16 select SPL_RESET_SUPPORT
17 select SPL_SERIAL_SUPPORT
18 select SPL_SYSCON
Patrick Delaunay32ddd262018-03-20 14:15:06 +010019 select SPL_DRIVERS_MISC_SUPPORT
Patrick Delaunay85b53972018-03-12 10:46:10 +010020 imply SPL_LIBDISK_SUPPORT
21
22config SYS_SOC
23 default "stm32mp"
24
25config TARGET_STM32MP1
26 bool "Support stm32mp1xx"
Patrick Delaunaye0207372018-04-16 10:13:24 +020027 select ARCH_SUPPORT_PSCI
Lokesh Vutla81b1a672018-04-26 18:21:26 +053028 select CPU_V7A
Patrick Delaunaye0207372018-04-16 10:13:24 +020029 select CPU_V7_HAS_NONSEC
30 select CPU_V7_HAS_VIRT
Patrick Delaunay85b53972018-03-12 10:46:10 +010031 select PINCTRL_STM32
32 select STM32_RESET
Andre Przywara7b169252018-04-12 04:24:46 +030033 select SYS_ARCH_TIMER
Patrick Delaunay32ddd262018-03-20 14:15:06 +010034 select SYSRESET_SYSCON
Patrick Delaunay85b53972018-03-12 10:46:10 +010035 help
36 target STMicroelectronics SOC STM32MP1 family
37 STMicroelectronics MPU with core ARMv7
38
39config SYS_TEXT_BASE
40 prompt "U-Boot base address"
41 default 0xC0100000
42 help
43 configure the U-Boot base address
44 when DDR driver is used:
45 DDR + 1MB (0xC0100000)
46
Patrick Delaunayfc69c682018-03-20 10:54:54 +010047config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
48 hex "Partition on MMC2 to use to load U-Boot from"
49 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
50 default 1
51 help
52 Partition on the second MMC to load U-Boot from when the MMC is being
53 used in raw mode
54
Patrick Delaunay8eb3b1e2018-03-12 10:46:18 +010055source "board/st/stm32mp1/Kconfig"
56
Patrick Delaunay82168e82018-05-17 14:50:46 +020057# currently activated for debug / should be deactivated for real product
58if DEBUG_UART
59
60config DEBUG_UART_BOARD_INIT
61 default y
62
63# debug on UART4 by default
64config DEBUG_UART_BASE
65 default 0x40010000
66
67# clock source is HSI on reset
68config DEBUG_UART_CLOCK
69 default 64000000
70endif
71
Patrick Delaunay85b53972018-03-12 10:46:10 +010072endif