blob: e5f05af6ac91e9f341f95a20d405a2026fa09953 [file] [log] [blame]
Patrick Delaunay85b53972018-03-12 10:46:10 +01001if ARCH_STM32MP
2
3config SPL
4 select SPL_BOARD_INIT
5 select SPL_CLK
6 select SPL_DM
7 select SPL_DM_SEQ_ALIAS
Patrick Delaunay636279a2018-07-09 15:17:21 +02008 select SPL_DRIVERS_MISC_SUPPORT
Patrick Delaunay85b53972018-03-12 10:46:10 +01009 select SPL_FRAMEWORK
10 select SPL_GPIO_SUPPORT
11 select SPL_LIBCOMMON_SUPPORT
12 select SPL_LIBGENERIC_SUPPORT
13 select SPL_OF_CONTROL
14 select SPL_OF_TRANSLATE
15 select SPL_PINCTRL
16 select SPL_REGMAP
Ley Foon Tan9caf7122018-06-14 18:45:19 +080017 select SPL_DM_RESET
Patrick Delaunay85b53972018-03-12 10:46:10 +010018 select SPL_SERIAL_SUPPORT
19 select SPL_SYSCON
Patrice Chotard473b2442019-04-30 17:26:22 +020020 select SPL_WATCHDOG_SUPPORT
Patrick Delaunayf8600202019-04-18 17:32:47 +020021 imply BOOTSTAGE_STASH if SPL_BOOTSTAGE
22 imply SPL_BOOTSTAGE if BOOTSTAGE
Patrick Delaunayaa4e6852019-02-27 17:01:14 +010023 imply SPL_DISPLAY_PRINT
Patrick Delaunay85b53972018-03-12 10:46:10 +010024 imply SPL_LIBDISK_SUPPORT
25
26config SYS_SOC
27 default "stm32mp"
28
Patrick Delaunay7e517c62019-04-18 17:32:36 +020029config SYS_MALLOC_LEN
30 default 0x2000000
31
Patrick Delaunay088b6762019-04-18 17:32:37 +020032config ENV_SIZE
Patrice Chotardd83bba42019-05-07 18:40:47 +020033 default 0x2000
Patrick Delaunay088b6762019-04-18 17:32:37 +020034
Patrick Delaunay85b53972018-03-12 10:46:10 +010035config TARGET_STM32MP1
36 bool "Support stm32mp1xx"
Patrick Delaunay5d061412019-02-12 11:44:39 +010037 select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED
Lokesh Vutla81b1a672018-04-26 18:21:26 +053038 select CPU_V7A
Patrick Delaunay5d061412019-02-12 11:44:39 +010039 select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED
Patrick Delaunaye0207372018-04-16 10:13:24 +020040 select CPU_V7_HAS_VIRT
Patrick Delaunayde98cbf2019-07-02 13:26:07 +020041 select OF_BOARD_SETUP
Patrick Delaunay85b53972018-03-12 10:46:10 +010042 select PINCTRL_STM32
Patrick Delaunayb139a5b2018-07-09 15:17:20 +020043 select STM32_RCC
Patrick Delaunay85b53972018-03-12 10:46:10 +010044 select STM32_RESET
Andre Przywara7b169252018-04-12 04:24:46 +030045 select SYS_ARCH_TIMER
Patrick Delaunay9c07f4a2019-04-18 17:32:45 +020046 imply BOOTCOUNT_LIMIT
Patrick Delaunayf8600202019-04-18 17:32:47 +020047 imply BOOTSTAGE
Patrick Delaunay9c07f4a2019-04-18 17:32:45 +020048 imply CMD_BOOTCOUNT
Patrick Delaunayf8600202019-04-18 17:32:47 +020049 imply CMD_BOOTSTAGE
Patrick Delaunay887d9e42019-07-30 19:16:22 +020050 imply SILENT_CONSOLE
Patrick Delaunay5d061412019-02-12 11:44:39 +010051 imply SYSRESET_PSCI if STM32MP1_TRUSTED
52 imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
Patrick Delaunay85b53972018-03-12 10:46:10 +010053 help
54 target STMicroelectronics SOC STM32MP1 family
Patrick Delaunay6d3cbf32019-02-27 17:01:15 +010055 STM32MP157, STM32MP153 or STM32MP151
Patrick Delaunay85b53972018-03-12 10:46:10 +010056 STMicroelectronics MPU with core ARMv7
Patrick Delaunay6d3cbf32019-02-27 17:01:15 +010057 dual core A7 for STM32MP157/3, monocore for STM32MP151
Patrick Delaunay85b53972018-03-12 10:46:10 +010058
Patrick Delaunay5d061412019-02-12 11:44:39 +010059config STM32MP1_TRUSTED
60 bool "Support trusted boot with TF-A"
61 default y if !SPL
62 select ARM_SMCCC
63 help
64 Say Y here to enable boot with TF-A
65 Trusted boot chain is :
66 BootRom => TF-A.stm32 (clock & DDR) => U-Boot.stm32
Patrick Delaunayff215a42019-07-02 13:26:06 +020067 TF-A monitor provides proprietary SMC to manage secure devices
68
69config STM32MP1_OPTEE
70 bool "Support trusted boot with TF-A and OP-TEE"
71 depends on STM32MP1_TRUSTED
72 default n
73 help
74 Say Y here to enable boot with TF-A and OP-TEE
75 Trusted boot chain is :
76 BootRom => TF-A.stm32 (clock & DDR) => OP-TEE => U-Boot.stm32
77 OP-TEE monitor provides ST SMC to access to secure resources
Patrick Delaunay5d061412019-02-12 11:44:39 +010078
Patrick Delaunay85b53972018-03-12 10:46:10 +010079config SYS_TEXT_BASE
80 prompt "U-Boot base address"
81 default 0xC0100000
82 help
83 configure the U-Boot base address
84 when DDR driver is used:
85 DDR + 1MB (0xC0100000)
86
Patrick Delaunay6d3cbf32019-02-27 17:01:15 +010087config NR_DRAM_BANKS
88 default 1
89
Patrick Delaunayfc69c682018-03-20 10:54:54 +010090config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
91 hex "Partition on MMC2 to use to load U-Boot from"
92 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
93 default 1
94 help
95 Partition on the second MMC to load U-Boot from when the MMC is being
96 used in raw mode
97
Patrick Delaunay43f214c2019-07-05 17:20:15 +020098config STM32_ETZPC
99 bool "STM32 Extended TrustZone Protection"
100 depends on TARGET_STM32MP1
101 default y
102 help
103 Say y to enable STM32 Extended TrustZone Protection
104
Patrick Delaunay109d13f2019-07-05 17:20:17 +0200105config CMD_STM32KEY
106 bool "command stm32key to fuse public key hash"
107 default y
108 depends on CMD_FUSE
109 help
110 fuse public key hash in corresponding fuse used to authenticate
111 binary.
112
Patrick Delaunayf8600202019-04-18 17:32:47 +0200113config BOOTSTAGE_STASH_ADDR
114 default 0xC3000000
115
Patrick Delaunay9c07f4a2019-04-18 17:32:45 +0200116if BOOTCOUNT_LIMIT
117config SYS_BOOTCOUNT_SINGLEWORD
118 default y
119
120# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
121config SYS_BOOTCOUNT_ADDR
122 default 0x5C00A154
123endif
124
Patrick Delaunay82168e82018-05-17 14:50:46 +0200125if DEBUG_UART
126
127config DEBUG_UART_BOARD_INIT
128 default y
129
130# debug on UART4 by default
131config DEBUG_UART_BASE
132 default 0x40010000
133
134# clock source is HSI on reset
135config DEBUG_UART_CLOCK
136 default 64000000
137endif
138
Patrick Delaunay6d3cbf32019-02-27 17:01:15 +0100139source "board/st/stm32mp1/Kconfig"
140
Patrick Delaunay85b53972018-03-12 10:46:10 +0100141endif