blob: c9846169610683f5794b54983e9d9f135d18af8e [file] [log] [blame]
Patrick Delaunay85b53972018-03-12 10:46:10 +01001if ARCH_STM32MP
2
3config SPL
4 select SPL_BOARD_INIT
5 select SPL_CLK
6 select SPL_DM
7 select SPL_DM_SEQ_ALIAS
Patrick Delaunay636279a2018-07-09 15:17:21 +02008 select SPL_DRIVERS_MISC_SUPPORT
Patrick Delaunay85b53972018-03-12 10:46:10 +01009 select SPL_FRAMEWORK
10 select SPL_GPIO_SUPPORT
11 select SPL_LIBCOMMON_SUPPORT
12 select SPL_LIBGENERIC_SUPPORT
13 select SPL_OF_CONTROL
14 select SPL_OF_TRANSLATE
15 select SPL_PINCTRL
16 select SPL_REGMAP
Ley Foon Tan9caf7122018-06-14 18:45:19 +080017 select SPL_DM_RESET
Patrick Delaunay85b53972018-03-12 10:46:10 +010018 select SPL_SERIAL_SUPPORT
19 select SPL_SYSCON
Patrick Delaunayaa4e6852019-02-27 17:01:14 +010020 imply SPL_DISPLAY_PRINT
Patrick Delaunay85b53972018-03-12 10:46:10 +010021 imply SPL_LIBDISK_SUPPORT
22
23config SYS_SOC
24 default "stm32mp"
25
Patrick Delaunay7e517c62019-04-18 17:32:36 +020026config SYS_MALLOC_LEN
27 default 0x2000000
28
Patrick Delaunay088b6762019-04-18 17:32:37 +020029config ENV_SIZE
30 default 0x1000
31
Patrick Delaunay85b53972018-03-12 10:46:10 +010032config TARGET_STM32MP1
33 bool "Support stm32mp1xx"
Patrick Delaunay5d061412019-02-12 11:44:39 +010034 select ARCH_SUPPORT_PSCI if !STM32MP1_TRUSTED
Lokesh Vutla81b1a672018-04-26 18:21:26 +053035 select CPU_V7A
Patrick Delaunay5d061412019-02-12 11:44:39 +010036 select CPU_V7_HAS_NONSEC if !STM32MP1_TRUSTED
Patrick Delaunaye0207372018-04-16 10:13:24 +020037 select CPU_V7_HAS_VIRT
Patrick Delaunay85b53972018-03-12 10:46:10 +010038 select PINCTRL_STM32
Patrick Delaunayb139a5b2018-07-09 15:17:20 +020039 select STM32_RCC
Patrick Delaunay85b53972018-03-12 10:46:10 +010040 select STM32_RESET
Andre Przywara7b169252018-04-12 04:24:46 +030041 select SYS_ARCH_TIMER
Patrick Delaunay9c07f4a2019-04-18 17:32:45 +020042 imply BOOTCOUNT_LIMIT
43 imply CMD_BOOTCOUNT
Patrick Delaunay5d061412019-02-12 11:44:39 +010044 imply SYSRESET_PSCI if STM32MP1_TRUSTED
45 imply SYSRESET_SYSCON if !STM32MP1_TRUSTED
Patrick Delaunay85b53972018-03-12 10:46:10 +010046 help
47 target STMicroelectronics SOC STM32MP1 family
Patrick Delaunay6d3cbf32019-02-27 17:01:15 +010048 STM32MP157, STM32MP153 or STM32MP151
Patrick Delaunay85b53972018-03-12 10:46:10 +010049 STMicroelectronics MPU with core ARMv7
Patrick Delaunay6d3cbf32019-02-27 17:01:15 +010050 dual core A7 for STM32MP157/3, monocore for STM32MP151
Patrick Delaunay85b53972018-03-12 10:46:10 +010051
Patrick Delaunay5d061412019-02-12 11:44:39 +010052config STM32MP1_TRUSTED
53 bool "Support trusted boot with TF-A"
54 default y if !SPL
55 select ARM_SMCCC
56 help
57 Say Y here to enable boot with TF-A
58 Trusted boot chain is :
59 BootRom => TF-A.stm32 (clock & DDR) => U-Boot.stm32
60 TF-A monitor provides proprietary smc to manage secure devices
61
Patrick Delaunay85b53972018-03-12 10:46:10 +010062config SYS_TEXT_BASE
63 prompt "U-Boot base address"
64 default 0xC0100000
65 help
66 configure the U-Boot base address
67 when DDR driver is used:
68 DDR + 1MB (0xC0100000)
69
Patrick Delaunay6d3cbf32019-02-27 17:01:15 +010070config NR_DRAM_BANKS
71 default 1
72
Patrick Delaunayfc69c682018-03-20 10:54:54 +010073config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_MMC2
74 hex "Partition on MMC2 to use to load U-Boot from"
75 depends on SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
76 default 1
77 help
78 Partition on the second MMC to load U-Boot from when the MMC is being
79 used in raw mode
80
Patrick Delaunay9c07f4a2019-04-18 17:32:45 +020081if BOOTCOUNT_LIMIT
82config SYS_BOOTCOUNT_SINGLEWORD
83 default y
84
85# TAMP_BOOTCOUNT = TAMP_BACKUP_REGISTER(21)
86config SYS_BOOTCOUNT_ADDR
87 default 0x5C00A154
88endif
89
Patrick Delaunay82168e82018-05-17 14:50:46 +020090if DEBUG_UART
91
92config DEBUG_UART_BOARD_INIT
93 default y
94
95# debug on UART4 by default
96config DEBUG_UART_BASE
97 default 0x40010000
98
99# clock source is HSI on reset
100config DEBUG_UART_CLOCK
101 default 64000000
102endif
103
Patrick Delaunay6d3cbf32019-02-27 17:01:15 +0100104source "board/st/stm32mp1/Kconfig"
105
Patrick Delaunay85b53972018-03-12 10:46:10 +0100106endif