Blame - arch/arm/mach-socfpga/Kconfig - filogic/uboot

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Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	1	if ARCH_SOCFPGA
				2
Simon Glass	f2a8946	2016-09-12 23:18:41 -0600	[diff] [blame]	3	config SPL_LIBCOMMON_SUPPORT
				4	default y
				5
Simon Glass	f6de257	2016-09-12 23:18:42 -0600	[diff] [blame]	6	config SPL_LIBDISK_SUPPORT
				7	default y
				8
Simon Glass	b16c92c	2016-09-12 23:18:43 -0600	[diff] [blame]	9	config SPL_LIBGENERIC_SUPPORT
				10	default y
				11
Simon Glass	bd58f1d	2016-09-12 23:18:44 -0600	[diff] [blame]	12	config SPL_MMC_SUPPORT
				13	default y if DM_MMC
				14
Simon Glass	d5a307a	2016-09-12 23:18:48 -0600	[diff] [blame]	15	config SPL_NAND_SUPPORT
				16	default y if SPL_NAND_DENALI
				17
Simon Glass	e076d6f	2016-09-12 23:18:56 -0600	[diff] [blame]	18	config SPL_SERIAL_SUPPORT
				19	default y
				20
Simon Glass	219d612	2016-09-12 23:18:57 -0600	[diff] [blame]	21	config SPL_SPI_FLASH_SUPPORT
Simon Glass	b24fdca	2016-09-12 23:18:58 -0600	[diff] [blame]	22	default y if SPL_SPI_SUPPORT
				23
				24	config SPL_SPI_SUPPORT
Simon Glass	219d612	2016-09-12 23:18:57 -0600	[diff] [blame]	25	default y if DM_SPI
				26
Simon Glass	6662a9f	2016-09-12 23:19:02 -0600	[diff] [blame]	27	config SPL_WATCHDOG_SUPPORT
				28	default y
				29
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	30	config TARGET_SOCFPGA_ARRIA5
				31	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame]	32	select TARGET_SOCFPGA_GEN5
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	33
				34	config TARGET_SOCFPGA_CYCLONE5
				35	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame]	36	select TARGET_SOCFPGA_GEN5
				37
				38	config TARGET_SOCFPGA_GEN5
				39	bool
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	40
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	41	choice
				42	prompt "Altera SOCFPGA board select"
Joe Hershberger	f069960	2015-05-12 14:46:23 -0500	[diff] [blame]	43	optional
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	44
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	45	config TARGET_SOCFPGA_ARRIA5_SOCDK
				46	bool "Altera SOCFPGA SoCDK (Arria V)"
				47	select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	48
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	49	config TARGET_SOCFPGA_CYCLONE5_SOCDK
				50	bool "Altera SOCFPGA SoCDK (Cyclone V)"
				51	select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	52
Marek Vasut	8e8b62a	2015-08-03 01:37:28 +0200	[diff] [blame]	53	config TARGET_SOCFPGA_DENX_MCVEVK
				54	bool "DENX MCVEVK (Cyclone V)"
				55	select TARGET_SOCFPGA_CYCLONE5
				56
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	57	config TARGET_SOCFPGA_EBV_SOCRATES
				58	bool "EBV SoCrates (Cyclone V)"
				59	select TARGET_SOCFPGA_CYCLONE5
				60
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	61	config TARGET_SOCFPGA_IS1
				62	bool "IS1 (Cyclone V)"
				63	select TARGET_SOCFPGA_CYCLONE5
				64
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	65	config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
				66	bool "samtec VIN\|ING FPGA (Cyclone V)"
				67	select TARGET_SOCFPGA_CYCLONE5
				68
Marek Vasut	2e717ec	2016-06-08 02:57:05 +0200	[diff] [blame]	69	config TARGET_SOCFPGA_SR1500
				70	bool "SR1500 (Cyclone V)"
				71	select TARGET_SOCFPGA_CYCLONE5
				72
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	73	config TARGET_SOCFPGA_TERASIC_DE0_NANO
				74	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
				75	select TARGET_SOCFPGA_CYCLONE5
				76
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	77	config TARGET_SOCFPGA_TERASIC_SOCKIT
				78	bool "Terasic SoCkit (Cyclone V)"
				79	select TARGET_SOCFPGA_CYCLONE5
				80
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	81	endchoice
				82
				83	config SYS_BOARD
Marek Vasut	3f4c561	2015-08-10 21:24:53 +0200	[diff] [blame]	84	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
				85	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	86	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	87	default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut	8e8b62a	2015-08-03 01:37:28 +0200	[diff] [blame]	88	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	89	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	90	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	91	default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	92	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	93
				94	config SYS_VENDOR
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	95	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
				96	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	8e8b62a	2015-08-03 01:37:28 +0200	[diff] [blame]	97	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	98	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	99	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	100	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	101	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	102
				103	config SYS_SOC
				104	default "socfpga"
				105
				106	config SYS_CONFIG_NAME
Dinh Nguyen	16f6ffd	2015-09-22 17:01:32 -0500	[diff] [blame]	107	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
				108	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	109	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	110	default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut	8e8b62a	2015-08-03 01:37:28 +0200	[diff] [blame]	111	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	112	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	113	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	114	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	115	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	116
				117	endif