Blame - arch/arm/mach-socfpga/Kconfig - filogic/uboot

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Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	1	if ARCH_SOCFPGA
				2
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	3	config TARGET_SOCFPGA_ARRIA5
				4	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame^]	5	select TARGET_SOCFPGA_GEN5
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	6
				7	config TARGET_SOCFPGA_CYCLONE5
				8	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame^]	9	select TARGET_SOCFPGA_GEN5
				10
				11	config TARGET_SOCFPGA_GEN5
				12	bool
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	13
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	14	choice
				15	prompt "Altera SOCFPGA board select"
Joe Hershberger	f069960	2015-05-12 14:46:23 -0500	[diff] [blame]	16	optional
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	17
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	18	config TARGET_SOCFPGA_ARRIA5_SOCDK
				19	bool "Altera SOCFPGA SoCDK (Arria V)"
				20	select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	21
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	22	config TARGET_SOCFPGA_CYCLONE5_SOCDK
				23	bool "Altera SOCFPGA SoCDK (Cyclone V)"
				24	select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	25
Marek Vasut	8e8b62a	2015-08-03 01:37:28 +0200	[diff] [blame]	26	config TARGET_SOCFPGA_DENX_MCVEVK
				27	bool "DENX MCVEVK (Cyclone V)"
				28	select TARGET_SOCFPGA_CYCLONE5
				29
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	30	config TARGET_SOCFPGA_SR1500
				31	bool "SR1500 (Cyclone V)"
				32	select TARGET_SOCFPGA_CYCLONE5
				33
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	34	config TARGET_SOCFPGA_EBV_SOCRATES
				35	bool "EBV SoCrates (Cyclone V)"
				36	select TARGET_SOCFPGA_CYCLONE5
				37
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	38	config TARGET_SOCFPGA_TERASIC_DE0_NANO
				39	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
				40	select TARGET_SOCFPGA_CYCLONE5
				41
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	42	config TARGET_SOCFPGA_TERASIC_SOCKIT
				43	bool "Terasic SoCkit (Cyclone V)"
				44	select TARGET_SOCFPGA_CYCLONE5
				45
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	46	endchoice
				47
				48	config SYS_BOARD
Marek Vasut	3f4c561	2015-08-10 21:24:53 +0200	[diff] [blame]	49	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
				50	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	51	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Marek Vasut	8e8b62a	2015-08-03 01:37:28 +0200	[diff] [blame]	52	default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	53	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	54	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	55	default "sr1500" if TARGET_SOCFPGA_SR1500
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	56
				57	config SYS_VENDOR
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	58	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
				59	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	8e8b62a	2015-08-03 01:37:28 +0200	[diff] [blame]	60	default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	61	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	62	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	63	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	64
				65	config SYS_SOC
				66	default "socfpga"
				67
				68	config SYS_CONFIG_NAME
Dinh Nguyen	16f6ffd	2015-09-22 17:01:32 -0500	[diff] [blame]	69	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
				70	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	71	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Marek Vasut	8e8b62a	2015-08-03 01:37:28 +0200	[diff] [blame]	72	default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	73	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	74	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	75	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	76
				77	endif