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git01.mediatek.com / filogic / uboot / bd58f1d8240e2b37bc682b455195816633f07375 / . / arch / arm / mach-socfpga / Kconfig
blob: 6aeabdbb22c4e49927a0a08c7bb6c95730f200ee [file] [log] [blame]
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]1if ARCH_SOCFPGA
2
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]3config SPL_LIBCOMMON_SUPPORT
4 default y
5
Simon Glassf6de2572016-09-12 23:18:42 -0600[diff] [blame]6config SPL_LIBDISK_SUPPORT
7 default y
8
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame]9config SPL_LIBGENERIC_SUPPORT
10 default y
11
Simon Glassbd58f1d2016-09-12 23:18:44 -0600[diff] [blame^]12config SPL_MMC_SUPPORT
13 default y if DM_MMC
14
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]15config TARGET_SOCFPGA_ARRIA5
16 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]17 select TARGET_SOCFPGA_GEN5
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]18
19config TARGET_SOCFPGA_CYCLONE5
20 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]21 select TARGET_SOCFPGA_GEN5
22
23config TARGET_SOCFPGA_GEN5
24 bool
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]25
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]26choice
27 prompt "Altera SOCFPGA board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]28 optional
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]29
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]30config TARGET_SOCFPGA_ARRIA5_SOCDK
31 bool "Altera SOCFPGA SoCDK (Arria V)"
32 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]33
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]34config TARGET_SOCFPGA_CYCLONE5_SOCDK
35 bool "Altera SOCFPGA SoCDK (Cyclone V)"
36 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]37
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]38config TARGET_SOCFPGA_DENX_MCVEVK
39 bool "DENX MCVEVK (Cyclone V)"
40 select TARGET_SOCFPGA_CYCLONE5
41
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]42config TARGET_SOCFPGA_EBV_SOCRATES
43 bool "EBV SoCrates (Cyclone V)"
44 select TARGET_SOCFPGA_CYCLONE5
45
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]46config TARGET_SOCFPGA_IS1
47 bool "IS1 (Cyclone V)"
48 select TARGET_SOCFPGA_CYCLONE5
49
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]50config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
51 bool "samtec VIN|ING FPGA (Cyclone V)"
52 select TARGET_SOCFPGA_CYCLONE5
53
Marek Vasut2e717ec2016-06-08 02:57:05 +0200[diff] [blame]54config TARGET_SOCFPGA_SR1500
55 bool "SR1500 (Cyclone V)"
56 select TARGET_SOCFPGA_CYCLONE5
57
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]58config TARGET_SOCFPGA_TERASIC_DE0_NANO
59 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
60 select TARGET_SOCFPGA_CYCLONE5
61
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]62config TARGET_SOCFPGA_TERASIC_SOCKIT
63 bool "Terasic SoCkit (Cyclone V)"
64 select TARGET_SOCFPGA_CYCLONE5
65
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]66endchoice
67
68config SYS_BOARD
Marek Vasut3f4c5612015-08-10 21:24:53 +0200[diff] [blame]69 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
70 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]71 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]72 default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]73 default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]74 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]75 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]76 default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]77 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]78
79config SYS_VENDOR
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]80 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
81 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]82 default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]83 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]84 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]85 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]86 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]87
88config SYS_SOC
89 default "socfpga"
90
91config SYS_CONFIG_NAME
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500[diff] [blame]92 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
93 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]94 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]95 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]96 default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]97 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]98 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]99 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]100 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]101
102endif