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git01.mediatek.com / filogic / uboot / b16c92c17580330ebcd3514ed2c1becaff2e34b8 / . / arch / arm / mach-socfpga / Kconfig
blob: e2c6c4b9d8a154f58e42859ab14fec30e39f1aa7 [file] [log] [blame]
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]1if ARCH_SOCFPGA
2
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]3config SPL_LIBCOMMON_SUPPORT
4 default y
5
Simon Glassf6de2572016-09-12 23:18:42 -0600[diff] [blame]6config SPL_LIBDISK_SUPPORT
7 default y
8
Simon Glassb16c92c2016-09-12 23:18:43 -0600[diff] [blame^]9config SPL_LIBGENERIC_SUPPORT
10 default y
11
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]12config TARGET_SOCFPGA_ARRIA5
13 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]14 select TARGET_SOCFPGA_GEN5
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]15
16config TARGET_SOCFPGA_CYCLONE5
17 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]18 select TARGET_SOCFPGA_GEN5
19
20config TARGET_SOCFPGA_GEN5
21 bool
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]22
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]23choice
24 prompt "Altera SOCFPGA board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]25 optional
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]26
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]27config TARGET_SOCFPGA_ARRIA5_SOCDK
28 bool "Altera SOCFPGA SoCDK (Arria V)"
29 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]30
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]31config TARGET_SOCFPGA_CYCLONE5_SOCDK
32 bool "Altera SOCFPGA SoCDK (Cyclone V)"
33 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]34
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]35config TARGET_SOCFPGA_DENX_MCVEVK
36 bool "DENX MCVEVK (Cyclone V)"
37 select TARGET_SOCFPGA_CYCLONE5
38
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]39config TARGET_SOCFPGA_EBV_SOCRATES
40 bool "EBV SoCrates (Cyclone V)"
41 select TARGET_SOCFPGA_CYCLONE5
42
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]43config TARGET_SOCFPGA_IS1
44 bool "IS1 (Cyclone V)"
45 select TARGET_SOCFPGA_CYCLONE5
46
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]47config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
48 bool "samtec VIN|ING FPGA (Cyclone V)"
49 select TARGET_SOCFPGA_CYCLONE5
50
Marek Vasut2e717ec2016-06-08 02:57:05 +0200[diff] [blame]51config TARGET_SOCFPGA_SR1500
52 bool "SR1500 (Cyclone V)"
53 select TARGET_SOCFPGA_CYCLONE5
54
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]55config TARGET_SOCFPGA_TERASIC_DE0_NANO
56 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
57 select TARGET_SOCFPGA_CYCLONE5
58
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]59config TARGET_SOCFPGA_TERASIC_SOCKIT
60 bool "Terasic SoCkit (Cyclone V)"
61 select TARGET_SOCFPGA_CYCLONE5
62
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]63endchoice
64
65config SYS_BOARD
Marek Vasut3f4c5612015-08-10 21:24:53 +0200[diff] [blame]66 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
67 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]68 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]69 default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]70 default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]71 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]72 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]73 default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]74 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]75
76config SYS_VENDOR
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]77 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
78 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]79 default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]80 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]81 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]82 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]83 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]84
85config SYS_SOC
86 default "socfpga"
87
88config SYS_CONFIG_NAME
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500[diff] [blame]89 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
90 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]91 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]92 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]93 default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]94 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]95 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]96 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]97 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]98
99endif