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git01.mediatek.com / filogic / uboot / f6de257d251a3ea12836cd6a2d9935d03dfe5c40 / . / arch / arm / mach-socfpga / Kconfig
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Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]1if ARCH_SOCFPGA
2
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame]3config SPL_LIBCOMMON_SUPPORT
4 default y
5
Simon Glassf6de2572016-09-12 23:18:42 -0600[diff] [blame^]6config SPL_LIBDISK_SUPPORT
7 default y
8
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]9config TARGET_SOCFPGA_ARRIA5
10 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]11 select TARGET_SOCFPGA_GEN5
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]12
13config TARGET_SOCFPGA_CYCLONE5
14 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]15 select TARGET_SOCFPGA_GEN5
16
17config TARGET_SOCFPGA_GEN5
18 bool
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]19
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]20choice
21 prompt "Altera SOCFPGA board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]22 optional
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]23
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]24config TARGET_SOCFPGA_ARRIA5_SOCDK
25 bool "Altera SOCFPGA SoCDK (Arria V)"
26 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]27
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]28config TARGET_SOCFPGA_CYCLONE5_SOCDK
29 bool "Altera SOCFPGA SoCDK (Cyclone V)"
30 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]31
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]32config TARGET_SOCFPGA_DENX_MCVEVK
33 bool "DENX MCVEVK (Cyclone V)"
34 select TARGET_SOCFPGA_CYCLONE5
35
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]36config TARGET_SOCFPGA_EBV_SOCRATES
37 bool "EBV SoCrates (Cyclone V)"
38 select TARGET_SOCFPGA_CYCLONE5
39
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]40config TARGET_SOCFPGA_IS1
41 bool "IS1 (Cyclone V)"
42 select TARGET_SOCFPGA_CYCLONE5
43
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]44config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
45 bool "samtec VIN|ING FPGA (Cyclone V)"
46 select TARGET_SOCFPGA_CYCLONE5
47
Marek Vasut2e717ec2016-06-08 02:57:05 +0200[diff] [blame]48config TARGET_SOCFPGA_SR1500
49 bool "SR1500 (Cyclone V)"
50 select TARGET_SOCFPGA_CYCLONE5
51
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]52config TARGET_SOCFPGA_TERASIC_DE0_NANO
53 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
54 select TARGET_SOCFPGA_CYCLONE5
55
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]56config TARGET_SOCFPGA_TERASIC_SOCKIT
57 bool "Terasic SoCkit (Cyclone V)"
58 select TARGET_SOCFPGA_CYCLONE5
59
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]60endchoice
61
62config SYS_BOARD
Marek Vasut3f4c5612015-08-10 21:24:53 +0200[diff] [blame]63 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
64 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]65 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]66 default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]67 default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]68 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]69 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]70 default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]71 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]72
73config SYS_VENDOR
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]74 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
75 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]76 default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]77 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]78 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]79 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]80 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]81
82config SYS_SOC
83 default "socfpga"
84
85config SYS_CONFIG_NAME
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500[diff] [blame]86 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
87 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]88 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]89 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]90 default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]91 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]92 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]93 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]94 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]95
96endif