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git01.mediatek.com / filogic / uboot / f2a8946803f7b8bd3dd3ac5ff3c6680b8677db03 / . / arch / arm / mach-socfpga / Kconfig
blob: a782dafcfb17fed2f7047d8e5e52b07b929d57df [file] [log] [blame]
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]1if ARCH_SOCFPGA
2
Simon Glassf2a89462016-09-12 23:18:41 -0600[diff] [blame^]3config SPL_LIBCOMMON_SUPPORT
4 default y
5
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]6config TARGET_SOCFPGA_ARRIA5
7 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]8 select TARGET_SOCFPGA_GEN5
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]9
10config TARGET_SOCFPGA_CYCLONE5
11 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]12 select TARGET_SOCFPGA_GEN5
13
14config TARGET_SOCFPGA_GEN5
15 bool
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]16
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]17choice
18 prompt "Altera SOCFPGA board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]19 optional
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]20
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]21config TARGET_SOCFPGA_ARRIA5_SOCDK
22 bool "Altera SOCFPGA SoCDK (Arria V)"
23 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]24
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]25config TARGET_SOCFPGA_CYCLONE5_SOCDK
26 bool "Altera SOCFPGA SoCDK (Cyclone V)"
27 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]28
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]29config TARGET_SOCFPGA_DENX_MCVEVK
30 bool "DENX MCVEVK (Cyclone V)"
31 select TARGET_SOCFPGA_CYCLONE5
32
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]33config TARGET_SOCFPGA_EBV_SOCRATES
34 bool "EBV SoCrates (Cyclone V)"
35 select TARGET_SOCFPGA_CYCLONE5
36
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]37config TARGET_SOCFPGA_IS1
38 bool "IS1 (Cyclone V)"
39 select TARGET_SOCFPGA_CYCLONE5
40
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]41config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
42 bool "samtec VIN|ING FPGA (Cyclone V)"
43 select TARGET_SOCFPGA_CYCLONE5
44
Marek Vasut2e717ec2016-06-08 02:57:05 +0200[diff] [blame]45config TARGET_SOCFPGA_SR1500
46 bool "SR1500 (Cyclone V)"
47 select TARGET_SOCFPGA_CYCLONE5
48
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]49config TARGET_SOCFPGA_TERASIC_DE0_NANO
50 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
51 select TARGET_SOCFPGA_CYCLONE5
52
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]53config TARGET_SOCFPGA_TERASIC_SOCKIT
54 bool "Terasic SoCkit (Cyclone V)"
55 select TARGET_SOCFPGA_CYCLONE5
56
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]57endchoice
58
59config SYS_BOARD
Marek Vasut3f4c5612015-08-10 21:24:53 +0200[diff] [blame]60 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
61 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]62 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]63 default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]64 default "mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]65 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]66 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]67 default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]68 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]69
70config SYS_VENDOR
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]71 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
72 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]73 default "denx" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]74 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]75 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]76 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]77 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]78
79config SYS_SOC
80 default "socfpga"
81
82config SYS_CONFIG_NAME
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500[diff] [blame]83 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
84 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]85 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]86 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut8e8b62a2015-08-03 01:37:28 +0200[diff] [blame]87 default "socfpga_mcvevk" if TARGET_SOCFPGA_DENX_MCVEVK
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]88 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]89 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]90 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]91 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]92
93endif