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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Pavel Machek5e2d70a2014-09-08 14:08:45 +02002/*
3 * Copyright (C) 2012 Altera Corporation <www.altera.com>
Pavel Machek5e2d70a2014-09-08 14:08:45 +02004 */
Dinh Nguyenf593acd2015-12-03 16:05:59 -06005#ifndef __CONFIG_SOCFPGA_COMMON_H__
6#define __CONFIG_SOCFPGA_COMMON_H__
Pavel Machek5e2d70a2014-09-08 14:08:45 +02007
Simon Glassfb64e362020-05-10 11:40:09 -06008#include <linux/stringify.h>
9
Pavel Machek5e2d70a2014-09-08 14:08:45 +020010/*
11 * High level configuration
12 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020013#define CONFIG_CLOCKS
14
Pavel Machek5e2d70a2014-09-08 14:08:45 +020015/*
16 * Memory configurations
17 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020018#define PHYS_SDRAM_1 0x0
Ley Foon Tan10b69642017-04-26 02:44:46 +080019#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
Pavel Machek5e2d70a2014-09-08 14:08:45 +020020#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
Ley Foon Tane62883b2020-03-06 16:55:19 +080021#define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE
Ley Foon Tanc28cb932020-12-22 09:53:25 +080022#define CONFIG_SPL_PAD_TO 0x10000
Ley Foon Tan10b69642017-04-26 02:44:46 +080023#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
24#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
Ley Foon Tanc28cb932020-12-22 09:53:25 +080025#define CONFIG_SPL_PAD_TO 0x40000
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020026/* SPL memory allocation configuration, this is for FAT implementation */
27#ifndef CONFIG_SYS_SPL_MALLOC_SIZE
28#define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000
29#endif
Ley Foon Tane62883b2020-03-06 16:55:19 +080030#define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \
31 CONFIG_SYS_SPL_MALLOC_SIZE)
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020032#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \
33 CONFIG_SYS_INIT_RAM_SIZE)
Ley Foon Tan10b69642017-04-26 02:44:46 +080034#endif
Stefan Roesead4105f2018-10-30 10:00:22 +010035
36/*
37 * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal
38 * SRAM as bootcounter storage. Make sure to not put the stack directly
39 * at this address to not overwrite the bootcounter by checking, if the
40 * bootcounter address is located in the internal SRAM.
41 */
42#if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \
43 (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \
44 CONFIG_SYS_INIT_RAM_SIZE)))
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020045#define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR
Stefan Roesead4105f2018-10-30 10:00:22 +010046#else
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020047#define CONFIG_SPL_STACK \
Marek Vasutbb45f272018-04-26 22:23:05 +020048 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
Stefan Roesead4105f2018-10-30 10:00:22 +010049#endif
Pavel Machek5e2d70a2014-09-08 14:08:45 +020050
Simon Goldschmidtfb2965c2019-04-09 21:02:04 +020051/*
52 * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc
53 * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage
54 * in U-Boot pre-reloc is higher than in SPL.
55 */
56#if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR
57#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR
58#else
59#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK
60#endif
61
Pavel Machek5e2d70a2014-09-08 14:08:45 +020062#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Pavel Machek5e2d70a2014-09-08 14:08:45 +020063
64/*
65 * U-Boot general configurations
66 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020067#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020068 /* Print buffer size */
69#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
70#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
71 /* Boot argument buffer size */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020072
73/*
74 * Cache
75 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +020076#define CONFIG_SYS_L2_PL310
77#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
78
79/*
80 * Ethernet on SoC (EMAC)
81 */
Marek Vasut0d5abc92018-04-23 01:26:10 +020082#ifdef CONFIG_CMD_NET
Pavel Machek5e2d70a2014-09-08 14:08:45 +020083#define CONFIG_DW_ALTDESCRIPTOR
Pavel Machek5e2d70a2014-09-08 14:08:45 +020084#endif
85
86/*
87 * FPGA Driver
88 */
89#ifdef CONFIG_CMD_FPGA
Pavel Machek5e2d70a2014-09-08 14:08:45 +020090#define CONFIG_FPGA_COUNT 1
91#endif
Tien Fong Cheec5b16e12017-07-26 13:05:44 +080092
Pavel Machek5e2d70a2014-09-08 14:08:45 +020093/*
94 * L4 OSC1 Timer 0
95 */
Marek Vasutaaa40e72018-08-18 16:00:31 +020096#ifndef CONFIG_TIMER
Pavel Machek5e2d70a2014-09-08 14:08:45 +020097#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
98#define CONFIG_SYS_TIMER_COUNTS_DOWN
99#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
Marek Vasut979de712020-02-15 14:10:02 +0100100#ifndef CONFIG_SYS_TIMER_RATE
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200101#define CONFIG_SYS_TIMER_RATE 25000000
Marek Vasutaaa40e72018-08-18 16:00:31 +0200102#endif
Marek Vasut979de712020-02-15 14:10:02 +0100103#endif
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200104
105/*
106 * L4 Watchdog
107 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200108#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
109#define CONFIG_DW_WDT_CLOCK_KHZ 25000
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200110
111/*
112 * MMC Driver
113 */
114#ifdef CONFIG_CMD_MMC
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200115/* FIXME */
116/* using smaller max blk cnt to avoid flooding the limited stack we have */
117#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
118#endif
119
Stefan Roese9a468c02014-11-07 12:37:52 +0100120/*
Marek Vasut7e442d92015-12-20 04:00:46 +0100121 * NAND Support
122 */
123#ifdef CONFIG_NAND_DENALI
124#define CONFIG_SYS_MAX_NAND_DEVICE 1
Marek Vasut7e442d92015-12-20 04:00:46 +0100125#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
126#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
Marek Vasut7e442d92015-12-20 04:00:46 +0100127#endif
128
129/*
Stefan Roese9a468c02014-11-07 12:37:52 +0100130 * QSPI support
131 */
Stefan Roese9a468c02014-11-07 12:37:52 +0100132/* QSPI reference clock */
133#ifndef __ASSEMBLY__
134unsigned int cm_get_qspi_controller_clk_hz(void);
135#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
136#endif
Stefan Roese9a468c02014-11-07 12:37:52 +0100137
Marek Vasutcabc3b42015-08-19 23:23:53 +0200138/*
Marek Vasut9f193122014-10-24 23:34:25 +0200139 * USB
140 */
Marek Vasut9f193122014-10-24 23:34:25 +0200141
142/*
Marek Vasut40f1d6b2014-11-04 04:25:09 +0100143 * USB Gadget (DFU, UMS)
144 */
145#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
Marek Vasut40f1d6b2014-11-04 04:25:09 +0100146#define DFU_DEFAULT_POLL_TIMEOUT 300
147
148/* USB IDs */
Sam Protsenkob706ffd2016-04-13 14:20:30 +0300149#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
150#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
Marek Vasut40f1d6b2014-11-04 04:25:09 +0100151#endif
152
153/*
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200154 * U-Boot environment
155 */
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200156
Chin Liang Seefb73f6d2015-12-21 21:02:45 +0800157/* Environment for SDMMC boot */
Chin Liang Seefb73f6d2015-12-21 21:02:45 +0800158
Chin Liang See713e5b12016-02-24 16:50:22 +0800159/* Environment for QSPI boot */
Chin Liang See713e5b12016-02-24 16:50:22 +0800160
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200161/*
162 * SPL
Marek Vasutea0123c2014-10-16 12:25:40 +0200163 *
Tien Fong Chee200ae352017-12-05 15:58:04 +0800164 * SRAM Memory layout for gen 5:
Marek Vasutea0123c2014-10-16 12:25:40 +0200165 *
166 * 0xFFFF_0000 ...... Start of SRAM
167 * 0xFFFF_xxxx ...... Top of stack (grows down)
Simon Goldschmidta3e50262019-04-09 21:02:03 +0200168 * 0xFFFF_yyyy ...... Global Data
169 * 0xFFFF_zzzz ...... Malloc area
170 * 0xFFFF_FFFF ...... End of SRAM
Tien Fong Chee200ae352017-12-05 15:58:04 +0800171 *
172 * SRAM Memory layout for Arria 10:
173 * 0xFFE0_0000 ...... Start of SRAM (bottom)
174 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
175 * 0xFFEy_yyyy ...... Global Data
176 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
177 * 0xFFE3_FFFF ...... End of SRAM (top)
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200178 */
Simon Goldschmidt376a8f82019-03-15 20:44:32 +0100179#ifndef CONFIG_SPL_TEXT_BASE
Ley Foon Tan10b69642017-04-26 02:44:46 +0800180#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
Simon Goldschmidt376a8f82019-03-15 20:44:32 +0100181#endif
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200182
Marek Vasut1029caf2015-07-10 00:04:23 +0200183/* SPL SDMMC boot support */
Simon Glassb58bfe02021-08-08 12:20:09 -0600184#ifdef CONFIG_SPL_MMC
Tien Fong Chee6091dd12019-01-23 14:20:05 +0800185#if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
Dalon Westergreen7c4c0c32019-08-07 10:37:36 -0700186#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700187#endif
Marek Vasut1029caf2015-07-10 00:04:23 +0200188#endif
Pavel Machek5e2d70a2014-09-08 14:08:45 +0200189
Marek Vasutcadf2f92015-07-21 07:50:03 +0200190/* SPL QSPI boot support */
Marek Vasutcadf2f92015-07-21 07:50:03 +0200191
Marek Vasut7e442d92015-12-20 04:00:46 +0100192/* SPL NAND boot support */
Marek Vasut7e442d92015-12-20 04:00:46 +0100193
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700194/* Extra Environment */
195#ifndef CONFIG_SPL_BUILD
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700196
Simon Goldschmidt2e5d9a62018-01-25 07:18:27 +0100197#ifdef CONFIG_CMD_DHCP
198#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
199#else
200#define BOOT_TARGET_DEVICES_DHCP(func)
201#endif
202
Joe Hershberger8e8594f2018-04-13 15:26:40 -0500203#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700204#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
205#else
206#define BOOT_TARGET_DEVICES_PXE(func)
207#endif
208
209#ifdef CONFIG_CMD_MMC
210#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
211#else
212#define BOOT_TARGET_DEVICES_MMC(func)
213#endif
214
215#define BOOT_TARGET_DEVICES(func) \
216 BOOT_TARGET_DEVICES_MMC(func) \
217 BOOT_TARGET_DEVICES_PXE(func) \
Simon Goldschmidt2e5d9a62018-01-25 07:18:27 +0100218 BOOT_TARGET_DEVICES_DHCP(func)
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700219
220#include <config_distro_bootcmd.h>
221
222#ifndef CONFIG_EXTRA_ENV_SETTINGS
223#define CONFIG_EXTRA_ENV_SETTINGS \
224 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
225 "bootm_size=0xa000000\0" \
226 "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
227 "fdt_addr_r=0x02000000\0" \
228 "scriptaddr=0x02100000\0" \
229 "pxefile_addr_r=0x02200000\0" \
230 "ramdisk_addr_r=0x02300000\0" \
Simon Goldschmidt0de397b2019-03-01 20:12:31 +0100231 "socfpga_legacy_reset_compat=1\0" \
Dalon Westergreenbfd74c62017-04-13 07:30:29 -0700232 BOOTENV
233
234#endif
235#endif
236
Dinh Nguyenf593acd2015-12-03 16:05:59 -0600237#endif /* __CONFIG_SOCFPGA_COMMON_H__ */