Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 Altera Corporation <www.altera.com> |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 4 | */ |
Dinh Nguyen | f593acd | 2015-12-03 16:05:59 -0600 | [diff] [blame] | 5 | #ifndef __CONFIG_SOCFPGA_COMMON_H__ |
| 6 | #define __CONFIG_SOCFPGA_COMMON_H__ |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 7 | |
Simon Glass | fb64e36 | 2020-05-10 11:40:09 -0600 | [diff] [blame] | 8 | #include <linux/stringify.h> |
| 9 | |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 10 | /* |
| 11 | * High level configuration |
| 12 | */ |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 13 | #define CONFIG_CLOCKS |
| 14 | |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 15 | /* |
| 16 | * Memory configurations |
| 17 | */ |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 18 | #define PHYS_SDRAM_1 0x0 |
Ley Foon Tan | 10b6964 | 2017-04-26 02:44:46 +0800 | [diff] [blame] | 19 | #if defined(CONFIG_TARGET_SOCFPGA_GEN5) |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 20 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000 |
Ley Foon Tan | e62883b | 2020-03-06 16:55:19 +0800 | [diff] [blame] | 21 | #define CONFIG_SYS_INIT_RAM_SIZE SOCFPGA_PHYS_OCRAM_SIZE |
Ley Foon Tan | c28cb93 | 2020-12-22 09:53:25 +0800 | [diff] [blame] | 22 | #define CONFIG_SPL_PAD_TO 0x10000 |
Ley Foon Tan | 10b6964 | 2017-04-26 02:44:46 +0800 | [diff] [blame] | 23 | #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10) |
| 24 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000 |
Ley Foon Tan | c28cb93 | 2020-12-22 09:53:25 +0800 | [diff] [blame] | 25 | #define CONFIG_SPL_PAD_TO 0x40000 |
Simon Goldschmidt | fb2965c | 2019-04-09 21:02:04 +0200 | [diff] [blame] | 26 | /* SPL memory allocation configuration, this is for FAT implementation */ |
| 27 | #ifndef CONFIG_SYS_SPL_MALLOC_SIZE |
| 28 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x10000 |
| 29 | #endif |
Ley Foon Tan | e62883b | 2020-03-06 16:55:19 +0800 | [diff] [blame] | 30 | #define CONFIG_SYS_INIT_RAM_SIZE (SOCFPGA_PHYS_OCRAM_SIZE - \ |
| 31 | CONFIG_SYS_SPL_MALLOC_SIZE) |
Simon Goldschmidt | fb2965c | 2019-04-09 21:02:04 +0200 | [diff] [blame] | 32 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 33 | CONFIG_SYS_INIT_RAM_SIZE) |
Ley Foon Tan | 10b6964 | 2017-04-26 02:44:46 +0800 | [diff] [blame] | 34 | #endif |
Stefan Roese | ad4105f | 2018-10-30 10:00:22 +0100 | [diff] [blame] | 35 | |
| 36 | /* |
| 37 | * Some boards (e.g. socfpga_sr1500) use 8 bytes at the end of the internal |
| 38 | * SRAM as bootcounter storage. Make sure to not put the stack directly |
| 39 | * at this address to not overwrite the bootcounter by checking, if the |
| 40 | * bootcounter address is located in the internal SRAM. |
| 41 | */ |
| 42 | #if ((CONFIG_SYS_BOOTCOUNT_ADDR > CONFIG_SYS_INIT_RAM_ADDR) && \ |
| 43 | (CONFIG_SYS_BOOTCOUNT_ADDR < (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 44 | CONFIG_SYS_INIT_RAM_SIZE))) |
Simon Goldschmidt | fb2965c | 2019-04-09 21:02:04 +0200 | [diff] [blame] | 45 | #define CONFIG_SPL_STACK CONFIG_SYS_BOOTCOUNT_ADDR |
Stefan Roese | ad4105f | 2018-10-30 10:00:22 +0100 | [diff] [blame] | 46 | #else |
Simon Goldschmidt | fb2965c | 2019-04-09 21:02:04 +0200 | [diff] [blame] | 47 | #define CONFIG_SPL_STACK \ |
Marek Vasut | bb45f27 | 2018-04-26 22:23:05 +0200 | [diff] [blame] | 48 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) |
Stefan Roese | ad4105f | 2018-10-30 10:00:22 +0100 | [diff] [blame] | 49 | #endif |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 50 | |
Simon Goldschmidt | fb2965c | 2019-04-09 21:02:04 +0200 | [diff] [blame] | 51 | /* |
| 52 | * U-Boot stack setup: if SPL post-reloc uses DDR stack, use it in pre-reloc |
| 53 | * phase of U-Boot, too. This prevents overwriting SPL data if stack/heap usage |
| 54 | * in U-Boot pre-reloc is higher than in SPL. |
| 55 | */ |
| 56 | #if defined(CONFIG_SPL_STACK_R_ADDR) && CONFIG_SPL_STACK_R_ADDR |
| 57 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK_R_ADDR |
| 58 | #else |
| 59 | #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SPL_STACK |
| 60 | #endif |
| 61 | |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 62 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 63 | |
| 64 | /* |
| 65 | * U-Boot general configurations |
| 66 | */ |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 67 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */ |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 68 | /* Print buffer size */ |
| 69 | #define CONFIG_SYS_MAXARGS 32 /* Max number of command args */ |
| 70 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 71 | /* Boot argument buffer size */ |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 72 | |
| 73 | /* |
| 74 | * Cache |
| 75 | */ |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 76 | #define CONFIG_SYS_L2_PL310 |
| 77 | #define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS |
| 78 | |
| 79 | /* |
| 80 | * Ethernet on SoC (EMAC) |
| 81 | */ |
Marek Vasut | 0d5abc9 | 2018-04-23 01:26:10 +0200 | [diff] [blame] | 82 | #ifdef CONFIG_CMD_NET |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 83 | #define CONFIG_DW_ALTDESCRIPTOR |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 84 | #endif |
| 85 | |
| 86 | /* |
| 87 | * FPGA Driver |
| 88 | */ |
| 89 | #ifdef CONFIG_CMD_FPGA |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 90 | #define CONFIG_FPGA_COUNT 1 |
| 91 | #endif |
Tien Fong Chee | c5b16e1 | 2017-07-26 13:05:44 +0800 | [diff] [blame] | 92 | |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 93 | /* |
| 94 | * L4 OSC1 Timer 0 |
| 95 | */ |
Marek Vasut | aaa40e7 | 2018-08-18 16:00:31 +0200 | [diff] [blame] | 96 | #ifndef CONFIG_TIMER |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 97 | #define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS |
| 98 | #define CONFIG_SYS_TIMER_COUNTS_DOWN |
| 99 | #define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4) |
Marek Vasut | 979de71 | 2020-02-15 14:10:02 +0100 | [diff] [blame] | 100 | #ifndef CONFIG_SYS_TIMER_RATE |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 101 | #define CONFIG_SYS_TIMER_RATE 25000000 |
Marek Vasut | aaa40e7 | 2018-08-18 16:00:31 +0200 | [diff] [blame] | 102 | #endif |
Marek Vasut | 979de71 | 2020-02-15 14:10:02 +0100 | [diff] [blame] | 103 | #endif |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 104 | |
| 105 | /* |
| 106 | * L4 Watchdog |
| 107 | */ |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 108 | #define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS |
| 109 | #define CONFIG_DW_WDT_CLOCK_KHZ 25000 |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 110 | |
| 111 | /* |
| 112 | * MMC Driver |
| 113 | */ |
| 114 | #ifdef CONFIG_CMD_MMC |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 115 | /* FIXME */ |
| 116 | /* using smaller max blk cnt to avoid flooding the limited stack we have */ |
| 117 | #define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ |
| 118 | #endif |
| 119 | |
Stefan Roese | 9a468c0 | 2014-11-07 12:37:52 +0100 | [diff] [blame] | 120 | /* |
Marek Vasut | 7e442d9 | 2015-12-20 04:00:46 +0100 | [diff] [blame] | 121 | * NAND Support |
| 122 | */ |
| 123 | #ifdef CONFIG_NAND_DENALI |
| 124 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
Marek Vasut | 7e442d9 | 2015-12-20 04:00:46 +0100 | [diff] [blame] | 125 | #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS |
| 126 | #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS |
Marek Vasut | 7e442d9 | 2015-12-20 04:00:46 +0100 | [diff] [blame] | 127 | #endif |
| 128 | |
| 129 | /* |
Stefan Roese | 9a468c0 | 2014-11-07 12:37:52 +0100 | [diff] [blame] | 130 | * QSPI support |
| 131 | */ |
Stefan Roese | 9a468c0 | 2014-11-07 12:37:52 +0100 | [diff] [blame] | 132 | /* QSPI reference clock */ |
| 133 | #ifndef __ASSEMBLY__ |
| 134 | unsigned int cm_get_qspi_controller_clk_hz(void); |
| 135 | #define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz() |
| 136 | #endif |
Stefan Roese | 9a468c0 | 2014-11-07 12:37:52 +0100 | [diff] [blame] | 137 | |
Marek Vasut | cabc3b4 | 2015-08-19 23:23:53 +0200 | [diff] [blame] | 138 | /* |
Marek Vasut | 9f19312 | 2014-10-24 23:34:25 +0200 | [diff] [blame] | 139 | * USB |
| 140 | */ |
Marek Vasut | 9f19312 | 2014-10-24 23:34:25 +0200 | [diff] [blame] | 141 | |
| 142 | /* |
Marek Vasut | 40f1d6b | 2014-11-04 04:25:09 +0100 | [diff] [blame] | 143 | * USB Gadget (DFU, UMS) |
| 144 | */ |
| 145 | #if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE) |
Marek Vasut | 40f1d6b | 2014-11-04 04:25:09 +0100 | [diff] [blame] | 146 | #define DFU_DEFAULT_POLL_TIMEOUT 300 |
| 147 | |
| 148 | /* USB IDs */ |
Sam Protsenko | b706ffd | 2016-04-13 14:20:30 +0300 | [diff] [blame] | 149 | #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 |
| 150 | #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5 |
Marek Vasut | 40f1d6b | 2014-11-04 04:25:09 +0100 | [diff] [blame] | 151 | #endif |
| 152 | |
| 153 | /* |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 154 | * U-Boot environment |
| 155 | */ |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 156 | |
Chin Liang See | fb73f6d | 2015-12-21 21:02:45 +0800 | [diff] [blame] | 157 | /* Environment for SDMMC boot */ |
Chin Liang See | fb73f6d | 2015-12-21 21:02:45 +0800 | [diff] [blame] | 158 | |
Chin Liang See | 713e5b1 | 2016-02-24 16:50:22 +0800 | [diff] [blame] | 159 | /* Environment for QSPI boot */ |
Chin Liang See | 713e5b1 | 2016-02-24 16:50:22 +0800 | [diff] [blame] | 160 | |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 161 | /* |
| 162 | * SPL |
Marek Vasut | ea0123c | 2014-10-16 12:25:40 +0200 | [diff] [blame] | 163 | * |
Tien Fong Chee | 200ae35 | 2017-12-05 15:58:04 +0800 | [diff] [blame] | 164 | * SRAM Memory layout for gen 5: |
Marek Vasut | ea0123c | 2014-10-16 12:25:40 +0200 | [diff] [blame] | 165 | * |
| 166 | * 0xFFFF_0000 ...... Start of SRAM |
| 167 | * 0xFFFF_xxxx ...... Top of stack (grows down) |
Simon Goldschmidt | a3e5026 | 2019-04-09 21:02:03 +0200 | [diff] [blame] | 168 | * 0xFFFF_yyyy ...... Global Data |
| 169 | * 0xFFFF_zzzz ...... Malloc area |
| 170 | * 0xFFFF_FFFF ...... End of SRAM |
Tien Fong Chee | 200ae35 | 2017-12-05 15:58:04 +0800 | [diff] [blame] | 171 | * |
| 172 | * SRAM Memory layout for Arria 10: |
| 173 | * 0xFFE0_0000 ...... Start of SRAM (bottom) |
| 174 | * 0xFFEx_xxxx ...... Top of stack (grows down to bottom) |
| 175 | * 0xFFEy_yyyy ...... Global Data |
| 176 | * 0xFFEz_zzzz ...... Malloc area (grows up to top) |
| 177 | * 0xFFE3_FFFF ...... End of SRAM (top) |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 178 | */ |
Simon Goldschmidt | 376a8f8 | 2019-03-15 20:44:32 +0100 | [diff] [blame] | 179 | #ifndef CONFIG_SPL_TEXT_BASE |
Ley Foon Tan | 10b6964 | 2017-04-26 02:44:46 +0800 | [diff] [blame] | 180 | #define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE |
Simon Goldschmidt | 376a8f8 | 2019-03-15 20:44:32 +0100 | [diff] [blame] | 181 | #endif |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 182 | |
Marek Vasut | 1029caf | 2015-07-10 00:04:23 +0200 | [diff] [blame] | 183 | /* SPL SDMMC boot support */ |
Simon Glass | b58bfe0 | 2021-08-08 12:20:09 -0600 | [diff] [blame] | 184 | #ifdef CONFIG_SPL_MMC |
Tien Fong Chee | 6091dd1 | 2019-01-23 14:20:05 +0800 | [diff] [blame] | 185 | #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4) |
Dalon Westergreen | 7c4c0c3 | 2019-08-07 10:37:36 -0700 | [diff] [blame] | 186 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
Dalon Westergreen | bfd74c6 | 2017-04-13 07:30:29 -0700 | [diff] [blame] | 187 | #endif |
Marek Vasut | 1029caf | 2015-07-10 00:04:23 +0200 | [diff] [blame] | 188 | #endif |
Pavel Machek | 5e2d70a | 2014-09-08 14:08:45 +0200 | [diff] [blame] | 189 | |
Marek Vasut | cadf2f9 | 2015-07-21 07:50:03 +0200 | [diff] [blame] | 190 | /* SPL QSPI boot support */ |
Marek Vasut | cadf2f9 | 2015-07-21 07:50:03 +0200 | [diff] [blame] | 191 | |
Marek Vasut | 7e442d9 | 2015-12-20 04:00:46 +0100 | [diff] [blame] | 192 | /* SPL NAND boot support */ |
Marek Vasut | 7e442d9 | 2015-12-20 04:00:46 +0100 | [diff] [blame] | 193 | |
Dalon Westergreen | bfd74c6 | 2017-04-13 07:30:29 -0700 | [diff] [blame] | 194 | /* Extra Environment */ |
| 195 | #ifndef CONFIG_SPL_BUILD |
Dalon Westergreen | bfd74c6 | 2017-04-13 07:30:29 -0700 | [diff] [blame] | 196 | |
Simon Goldschmidt | 2e5d9a6 | 2018-01-25 07:18:27 +0100 | [diff] [blame] | 197 | #ifdef CONFIG_CMD_DHCP |
| 198 | #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) |
| 199 | #else |
| 200 | #define BOOT_TARGET_DEVICES_DHCP(func) |
| 201 | #endif |
| 202 | |
Joe Hershberger | 8e8594f | 2018-04-13 15:26:40 -0500 | [diff] [blame] | 203 | #if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP) |
Dalon Westergreen | bfd74c6 | 2017-04-13 07:30:29 -0700 | [diff] [blame] | 204 | #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) |
| 205 | #else |
| 206 | #define BOOT_TARGET_DEVICES_PXE(func) |
| 207 | #endif |
| 208 | |
| 209 | #ifdef CONFIG_CMD_MMC |
| 210 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) |
| 211 | #else |
| 212 | #define BOOT_TARGET_DEVICES_MMC(func) |
| 213 | #endif |
| 214 | |
| 215 | #define BOOT_TARGET_DEVICES(func) \ |
| 216 | BOOT_TARGET_DEVICES_MMC(func) \ |
| 217 | BOOT_TARGET_DEVICES_PXE(func) \ |
Simon Goldschmidt | 2e5d9a6 | 2018-01-25 07:18:27 +0100 | [diff] [blame] | 218 | BOOT_TARGET_DEVICES_DHCP(func) |
Dalon Westergreen | bfd74c6 | 2017-04-13 07:30:29 -0700 | [diff] [blame] | 219 | |
| 220 | #include <config_distro_bootcmd.h> |
| 221 | |
| 222 | #ifndef CONFIG_EXTRA_ENV_SETTINGS |
| 223 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 224 | "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ |
| 225 | "bootm_size=0xa000000\0" \ |
| 226 | "kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \ |
| 227 | "fdt_addr_r=0x02000000\0" \ |
| 228 | "scriptaddr=0x02100000\0" \ |
| 229 | "pxefile_addr_r=0x02200000\0" \ |
| 230 | "ramdisk_addr_r=0x02300000\0" \ |
Simon Goldschmidt | 0de397b | 2019-03-01 20:12:31 +0100 | [diff] [blame] | 231 | "socfpga_legacy_reset_compat=1\0" \ |
Dalon Westergreen | bfd74c6 | 2017-04-13 07:30:29 -0700 | [diff] [blame] | 232 | BOOTENV |
| 233 | |
| 234 | #endif |
| 235 | #endif |
| 236 | |
Dinh Nguyen | f593acd | 2015-12-03 16:05:59 -0600 | [diff] [blame] | 237 | #endif /* __CONFIG_SOCFPGA_COMMON_H__ */ |