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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
David Feng3b5458c2013-12-14 11:47:37 +08002/*
3 * Configuration for Versatile Express. Parts were derived from other ARM
4 * configurations.
David Feng3b5458c2013-12-14 11:47:37 +08005 */
6
Peter Hoyes32860372021-11-11 09:26:00 +00007#ifndef __VEXPRESS_AEMV8_H
8#define __VEXPRESS_AEMV8_H
David Feng3b5458c2013-12-14 11:47:37 +08009
Peter Hoyes16fff302021-11-11 09:26:01 +000010#include <linux/stringify.h>
11
David Feng3b5458c2013-12-14 11:47:37 +080012/* Link Definitions */
Peter Hoyes32860372021-11-11 09:26:00 +000013#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
14#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7fff0)
15#else
Darwin Rambod32d4112014-06-09 11:12:59 -070016/* ATF loads u-boot here for BASE_FVP model */
Darwin Rambod32d4112014-06-09 11:12:59 -070017#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x03f00000)
Darwin Rambod32d4112014-06-09 11:12:59 -070018#endif
David Feng3b5458c2013-12-14 11:47:37 +080019
Ryan Harkin642aa2c2015-10-09 17:18:01 +010020#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
21
David Feng3b5458c2013-12-14 11:47:37 +080022/* CS register bases for the original memory map. */
Peter Hoyes3ca0ea02022-03-04 16:30:18 +000023#ifdef CONFIG_TARGET_VEXPRESS64_BASER_FVP
24#define V2M_DRAM_BASE 0x00000000
25#define V2M_PA_BASE 0x80000000
26#else
Andre Przywara87de4b72022-03-04 16:30:16 +000027#define V2M_DRAM_BASE 0x80000000
Peter Hoyes32860372021-11-11 09:26:00 +000028#define V2M_PA_BASE 0x00000000
Peter Hoyes3ca0ea02022-03-04 16:30:18 +000029#endif
Peter Hoyes32860372021-11-11 09:26:00 +000030
31#define V2M_PA_CS0 (V2M_PA_BASE + 0x00000000)
32#define V2M_PA_CS1 (V2M_PA_BASE + 0x14000000)
33#define V2M_PA_CS2 (V2M_PA_BASE + 0x18000000)
34#define V2M_PA_CS3 (V2M_PA_BASE + 0x1c000000)
35#define V2M_PA_CS4 (V2M_PA_BASE + 0x0c000000)
36#define V2M_PA_CS5 (V2M_PA_BASE + 0x10000000)
David Feng3b5458c2013-12-14 11:47:37 +080037
38#define V2M_PERIPH_OFFSET(x) (x << 16)
39#define V2M_SYSREGS (V2M_PA_CS3 + V2M_PERIPH_OFFSET(1))
40#define V2M_SYSCTL (V2M_PA_CS3 + V2M_PERIPH_OFFSET(2))
41#define V2M_SERIAL_BUS_PCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(3))
42
David Feng3b5458c2013-12-14 11:47:37 +080043/* Common peripherals relative to CS7. */
44#define V2M_AACI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(4))
45#define V2M_MMCI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(5))
46#define V2M_KMI0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(6))
47#define V2M_KMI1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(7))
48
Linus Walleijc5822502015-01-23 14:41:10 +010049#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
50#define V2M_UART0 0x7ff80000
51#define V2M_UART1 0x7ff70000
52#else /* Not Juno */
David Feng3b5458c2013-12-14 11:47:37 +080053#define V2M_UART0 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(9))
54#define V2M_UART1 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(10))
55#define V2M_UART2 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(11))
56#define V2M_UART3 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(12))
Linus Walleijc5822502015-01-23 14:41:10 +010057#endif
David Feng3b5458c2013-12-14 11:47:37 +080058
59#define V2M_WDT (V2M_PA_CS3 + V2M_PERIPH_OFFSET(15))
60
61#define V2M_TIMER01 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(17))
62#define V2M_TIMER23 (V2M_PA_CS3 + V2M_PERIPH_OFFSET(18))
63
64#define V2M_SERIAL_BUS_DVI (V2M_PA_CS3 + V2M_PERIPH_OFFSET(22))
65#define V2M_RTC (V2M_PA_CS3 + V2M_PERIPH_OFFSET(23))
66
67#define V2M_CF (V2M_PA_CS3 + V2M_PERIPH_OFFSET(26))
68
69#define V2M_CLCD (V2M_PA_CS3 + V2M_PERIPH_OFFSET(31))
70
71/* System register offsets. */
72#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
73#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
74#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
75
76/* Generic Timer Definitions */
Tom Rini3a6d4532021-09-03 10:40:28 -040077#define COUNTER_FREQUENCY 24000000 /* 24MHz */
David Feng3b5458c2013-12-14 11:47:37 +080078
79/* Generic Interrupt Controller Definitions */
David Feng79bbde02014-03-14 14:26:27 +080080#ifdef CONFIG_GICV3
Peter Hoyes32860372021-11-11 09:26:00 +000081#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
82#define GICR_BASE (V2M_PA_BASE + 0x2f100000)
David Feng79bbde02014-03-14 14:26:27 +080083#else
Darwin Rambod32d4112014-06-09 11:12:59 -070084
Peter Hoyes32860372021-11-11 09:26:00 +000085#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Linus Walleijc5822502015-01-23 14:41:10 +010086#define GICD_BASE (0x2C010000)
87#define GICC_BASE (0x2C02f000)
Peter Hoyes32860372021-11-11 09:26:00 +000088#else
89#define GICD_BASE (V2M_PA_BASE + 0x2f000000)
90#define GICC_BASE (V2M_PA_BASE + 0x2c000000)
David Feng79bbde02014-03-14 14:26:27 +080091#endif
Linus Walleija90caa32015-03-23 11:06:14 +010092#endif /* !CONFIG_GICV3 */
David Feng3b5458c2013-12-14 11:47:37 +080093
Peter Hoyes8194cda2021-11-11 09:26:03 +000094#if defined(CONFIG_TARGET_VEXPRESS64_BASE_FVP) && !defined(CONFIG_DM_ETH)
95/* The Vexpress64 BASE_FVP simulator uses SMSC91C111 */
Bhupesh Sharmae997f352014-01-16 09:47:40 -060096#define CONFIG_SMC91111 1
Peter Hoyes32860372021-11-11 09:26:00 +000097#define CONFIG_SMC91111_BASE (V2M_PA_BASE + 0x01A000000)
Linus Walleij48b47552015-02-17 11:35:25 +010098#endif
David Feng3b5458c2013-12-14 11:47:37 +080099
100/* PL011 Serial Configuration */
Linus Walleijc5822502015-01-23 14:41:10 +0100101#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Andre Przywarad3457182020-04-27 19:18:00 +0100102#define CONFIG_PL011_CLOCK 7372800
Linus Walleijc5822502015-01-23 14:41:10 +0100103#else
David Feng3b5458c2013-12-14 11:47:37 +0800104#define CONFIG_PL011_CLOCK 24000000
Linus Walleijc5822502015-01-23 14:41:10 +0100105#endif
David Feng3b5458c2013-12-14 11:47:37 +0800106
David Feng3b5458c2013-12-14 11:47:37 +0800107/* Physical Memory Map */
Andre Przywara87de4b72022-03-04 16:30:16 +0000108#define PHYS_SDRAM_1 (V2M_DRAM_BASE) /* SDRAM Bank #1 */
Linus Walleij0a38bfe2015-05-11 10:03:57 +0200109/* Top 16MB reserved for secure world use */
110#define DRAM_SEC_SIZE 0x01000000
111#define PHYS_SDRAM_1_SIZE 0x80000000 - DRAM_SEC_SIZE
112#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
113
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000114#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000115#define PHYS_SDRAM_2 (0x880000000)
116#define PHYS_SDRAM_2_SIZE 0x180000000
Peter Hoyes32860372021-11-11 09:26:00 +0000117#elif CONFIG_NR_DRAM_BANKS == 2
Diego Sueiro7a02a1b2021-02-15 07:27:57 +0000118#define PHYS_SDRAM_2 (0x880000000)
119#define PHYS_SDRAM_2_SIZE 0x80000000
Ryan Harkin98d2fff2015-11-18 10:39:07 +0000120#endif
121
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000122/* Copy the kernel, initrd and FDT from NOR flash to DRAM memory and boot. */
Andre Przywarabe035312021-07-12 00:25:15 +0100123#define BOOTENV_DEV_AFS(devtypeu, devtypel, instance) \
124 "bootcmd_afs=" \
125 "afs load ${kernel_name} ${kernel_addr_r} ;"\
126 "if test $? -eq 1; then "\
127 " echo Loading ${kernel_alt_name} instead of ${kernel_name}; "\
128 " afs load ${kernel_alt_name} ${kernel_addr_r};"\
129 "fi ; "\
130 "afs load ${fdtfile} ${fdt_addr_r} ;"\
131 "if test $? -eq 1; then "\
132 " echo Loading ${fdt_alt_name} instead of ${fdtfile}; "\
133 " afs load ${fdt_alt_name} ${fdt_addr_r}; "\
134 "fi ; "\
135 "fdt addr ${fdt_addr_r}; fdt resize; " \
136 "if afs load ${ramdisk_name} ${ramdisk_addr_r} ; "\
137 "then "\
138 " setenv ramdisk_param ${ramdisk_addr_r}; "\
139 "else "\
140 " setenv ramdisk_param -; "\
141 "fi ; " \
142 "booti ${kernel_addr_r} ${ramdisk_param} ${fdt_addr_r}\0"
143#define BOOTENV_DEV_NAME_AFS(devtypeu, devtypel, instance) "afs "
144
Andre Przywara019753a2022-03-04 16:30:14 +0000145/* Boot by executing a U-Boot script pre-loaded into DRAM. */
146#define BOOTENV_DEV_MEM(devtypeu, devtypel, instance) \
147 "bootcmd_mem= " \
148 "source ${scriptaddr}; " \
149 "if test $? -eq 1; then " \
150 " env import -t ${scriptaddr}; " \
151 " if test -n $uenvcmd; then " \
152 " echo Running uenvcmd ...; " \
153 " run uenvcmd; " \
154 " fi; " \
155 "fi\0"
156#define BOOTENV_DEV_NAME_MEM(devtypeu, devtypel, instance) "mem "
157
158#ifdef CONFIG_CMD_VIRTIO
159#define FUNC_VIRTIO(func) func(VIRTIO, virtio, 0)
160#else
161#define FUNC_VIRTIO(func)
162#endif
163
164/*
165 * Boot by loading an Android image, or kernel, initrd and FDT through
166 * semihosting into DRAM.
167 */
168#define BOOTENV_DEV_SMH(devtypeu, devtypel, instance) \
169 "bootcmd_smh= " \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400170 "if load hostfs - ${boot_addr_r} ${boot_name}; then" \
Andre Przywara019753a2022-03-04 16:30:14 +0000171 " setenv bootargs;" \
172 " abootimg addr ${boot_addr_r};" \
173 " abootimg get dtb --index=0 fdt_addr_r;" \
174 " bootm ${boot_addr_r} ${boot_addr_r} ${fdt_addr_r};" \
175 "else" \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400176 " if load hostfs - ${kernel_addr_r} ${kernel_name}; then" \
Andre Przywara019753a2022-03-04 16:30:14 +0000177 " setenv fdt_high 0xffffffffffffffff;" \
178 " setenv initrd_high 0xffffffffffffffff;" \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400179 " load hostfs - ${fdt_addr_r} ${fdtfile};" \
180 " load hostfs - ${ramdisk_addr_r} ${ramdisk_name};" \
Andre Przywara019753a2022-03-04 16:30:14 +0000181 " fdt addr ${fdt_addr_r};" \
182 " fdt resize;" \
Sean Anderson3e056ba2022-03-22 16:59:22 -0400183 " fdt chosen ${ramdisk_addr_r} ${filesize};" \
Andre Przywara019753a2022-03-04 16:30:14 +0000184 " booti $kernel_addr_r - $fdt_addr_r;" \
185 " fi;" \
186 "fi\0"
187#define BOOTENV_DEV_NAME_SMH(devtypeu, devtypel, instance) "smh "
188
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000189/* Boot sources for distro boot and load addresses, per board */
190
191#ifdef CONFIG_TARGET_VEXPRESS64_JUNO /* Arm Juno board */
192
Andre Przywarabe035312021-07-12 00:25:15 +0100193#define BOOT_TARGET_DEVICES(func) \
194 func(USB, usb, 0) \
195 func(SATA, sata, 0) \
196 func(SATA, sata, 1) \
197 func(PXE, pxe, na) \
198 func(DHCP, dhcp, na) \
199 func(AFS, afs, na)
200
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000201#define VEXPRESS_KERNEL_ADDR 0x80080000
202#define VEXPRESS_PXEFILE_ADDR 0x8fb00000
203#define VEXPRESS_FDT_ADDR 0x8fc00000
204#define VEXPRESS_SCRIPT_ADDR 0x8fd00000
205#define VEXPRESS_RAMDISK_ADDR 0x8fe00000
Linus Walleijc39566a2015-04-05 01:48:32 +0200206
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000207#define EXTRA_ENV_NAMES \
208 "kernel_name=norkern\0" \
209 "kernel_alt_name=Image\0" \
210 "ramdisk_name=ramdisk.img\0" \
211 "fdtfile=board.dtb\0" \
212 "fdt_alt_name=juno\0"
Peter Hoyes16fff302021-11-11 09:26:01 +0000213
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000214#elif CONFIG_TARGET_VEXPRESS64_BASE_FVP /* ARMv8-A base model */
Peter Hoyes16fff302021-11-11 09:26:01 +0000215
Andre Przywara019753a2022-03-04 16:30:14 +0000216#define BOOT_TARGET_DEVICES(func) \
217 func(SMH, smh, na) \
218 func(MEM, mem, na) \
219 FUNC_VIRTIO(func) \
220 func(PXE, pxe, na) \
221 func(DHCP, dhcp, na)
222
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000223#define VEXPRESS_KERNEL_ADDR 0x80080000
224#define VEXPRESS_PXEFILE_ADDR 0x8fa00000
225#define VEXPRESS_SCRIPT_ADDR 0x8fb00000
226#define VEXPRESS_FDT_ADDR 0x8fc00000
227#define VEXPRESS_BOOT_ADDR 0x8fd00000
228#define VEXPRESS_RAMDISK_ADDR 0x8fe00000
229
230#define EXTRA_ENV_NAMES \
231 "kernel_name=Image\0" \
232 "ramdisk_name=ramdisk.img\0" \
233 "fdtfile=devtree.dtb\0" \
234 "boot_name=boot.img\0" \
235 "boot_addr_r=" __stringify(VEXPRESS_BOOT_ADDR) "\0"
236
Peter Hoyes3ca0ea02022-03-04 16:30:18 +0000237#elif CONFIG_TARGET_VEXPRESS64_BASER_FVP /* ARMv8-R base model */
238
239#define BOOT_TARGET_DEVICES(func) \
240 func(MEM, mem, na) \
241 FUNC_VIRTIO(func) \
242 func(PXE, pxe, na) \
243 func(DHCP, dhcp, na)
244
245#define VEXPRESS_KERNEL_ADDR 0x00200000
246#define VEXPRESS_PXEFILE_ADDR 0x0fb00000
247#define VEXPRESS_FDT_ADDR 0x0fc00000
248#define VEXPRESS_SCRIPT_ADDR 0x0fd00000
249#define VEXPRESS_RAMDISK_ADDR 0x0fe00000
250
251#define EXTRA_ENV_NAMES \
252 "kernel_name=Image\0" \
253 "ramdisk_name=ramdisk.img\0" \
254 "fdtfile=board.dtb\0"
Darwin Rambod32d4112014-06-09 11:12:59 -0700255#endif
David Feng3b5458c2013-12-14 11:47:37 +0800256
Andre Przywara019753a2022-03-04 16:30:14 +0000257#include <config_distro_bootcmd.h>
258
Andre Przywaraec41c7f2022-03-04 16:30:12 +0000259/* Default load addresses and names for the different payloads. */
260#define CONFIG_EXTRA_ENV_SETTINGS \
261 "kernel_addr_r=" __stringify(VEXPRESS_KERNEL_ADDR) "\0" \
262 "ramdisk_addr_r=" __stringify(VEXPRESS_RAMDISK_ADDR) "\0" \
263 "pxefile_addr_r=" __stringify(VEXPRESS_PXEFILE_ADDR) "\0" \
264 "fdt_addr_r=" __stringify(VEXPRESS_FDT_ADDR) "\0" \
265 "scriptaddr=" __stringify(VEXPRESS_SCRIPT_ADDR) "\0" \
266 EXTRA_ENV_NAMES \
267 BOOTENV
268
David Feng3b5458c2013-12-14 11:47:37 +0800269/* Monitor Command Prompt */
270#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
David Feng3b5458c2013-12-14 11:47:37 +0800271#define CONFIG_SYS_MAXARGS 64 /* max command args */
272
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000273#ifdef CONFIG_TARGET_VEXPRESS64_JUNO
274#define CONFIG_SYS_FLASH_BASE 0x08000000
275/* 255 x 256KiB sectors + 4 x 64KiB sectors at the end = 259 */
276#define CONFIG_SYS_MAX_FLASH_SECT 259
277/* Store environment at top of flash in the same location as blank.img */
278/* in the Juno firmware. */
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100279#else
Peter Hoyes32860372021-11-11 09:26:00 +0000280#define CONFIG_SYS_FLASH_BASE (V2M_PA_BASE + 0x0C000000)
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000281/* 256 x 256KiB sectors */
282#define CONFIG_SYS_MAX_FLASH_SECT 256
283/* Store environment at top of flash */
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000284#endif
285
Ryan Harkinb1a4a672015-05-08 18:07:52 +0100286#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100287
Andre Przywarae3e81212020-04-27 19:18:03 +0100288#ifdef CONFIG_USB_EHCI_HCD
289#define CONFIG_USB_OHCI_NEW
290#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
291#endif
292
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100293#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
Ryan Harkinad5b2a22015-11-18 10:39:09 +0000294#define FLASH_MAX_SECTOR_SIZE 0x00040000
Linus Walleij6ba4b6a2015-02-19 17:19:37 +0100295
Peter Hoyes32860372021-11-11 09:26:00 +0000296#endif /* __VEXPRESS_AEMV8_H */