blob: a76a9fb2a395d88c030d2c06095ffdcaaa07c770 [file] [log] [blame]
Masahiro Yamada144a3e02015-04-21 20:38:20 +09001if ARCH_SOCFPGA
2
Simon Goldschmidt17d78522019-10-22 21:29:48 +02003config ERR_PTR_OFFSET
4 default 0xfffec000 if TARGET_SOCFPGA_GEN5 # Boot ROM range
5
Simon Goldschmidtb1c42692019-04-09 21:02:05 +02006config NR_DRAM_BANKS
7 default 1
8
Siew Chin Lim2492d592021-03-01 20:04:11 +08009config SOCFPGA_SECURE_VAB_AUTH
10 bool "Enable boot image authentication with Secure Device Manager"
Jit Loon Lim977071e2024-03-12 22:01:03 +080011 depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \
12 TARGET_SOCFPGA_AGILEX5
Siew Chin Lim2492d592021-03-01 20:04:11 +080013 select FIT_IMAGE_POST_PROCESS
14 select SHA384
Alexandru Gagniuc5df5d692021-09-02 19:54:18 -050015 select SHA512
Siew Chin Lim2492d592021-03-01 20:04:11 +080016 select SPL_FIT_IMAGE_POST_PROCESS
17 help
18 All images loaded from FIT will be authenticated by Secure Device
19 Manager.
20
21config SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE
22 bool "Allow non-FIT VAB signed images"
23 depends on SOCFPGA_SECURE_VAB_AUTH
24
Simon Goldschmidt20fd7de2019-06-13 21:50:28 +020025config SPL_SIZE_LIMIT
Simon Glassa8f0c942019-09-25 08:56:28 -060026 default 0x10000 if TARGET_SOCFPGA_GEN5
Simon Goldschmidt20fd7de2019-06-13 21:50:28 +020027
28config SPL_SIZE_LIMIT_PROVIDE_STACK
29 default 0x200 if TARGET_SOCFPGA_GEN5
30
Simon Goldschmidtb1c42692019-04-09 21:02:05 +020031config SPL_STACK_R_ADDR
32 default 0x00800000 if TARGET_SOCFPGA_GEN5
33
Simon Glassb59037b2023-09-26 08:14:25 -060034config SPL_SYS_MALLOC_F
35 default y if TARGET_SOCFPGA_GEN5
36
Simon Goldschmidt4f57b9a2019-04-09 21:02:06 +020037config SPL_SYS_MALLOC_F_LEN
38 default 0x800 if TARGET_SOCFPGA_GEN5
39
Dalon Westergreen8d770f42017-02-10 17:15:34 -080040config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
41 default 0xa2
42
Simon Goldschmidtb1c42692019-04-09 21:02:05 +020043config SYS_MALLOC_F_LEN
44 default 0x2000 if TARGET_SOCFPGA_ARRIA10
45 default 0x2000 if TARGET_SOCFPGA_GEN5
46
Simon Glass72cc5382022-10-20 18:22:39 -060047config TEXT_BASE
Simon Goldschmidtb1c42692019-04-09 21:02:05 +020048 default 0x01000040 if TARGET_SOCFPGA_ARRIA10
49 default 0x01000040 if TARGET_SOCFPGA_GEN5
50
Ley Foon Tan461d2982019-11-27 15:55:32 +080051config TARGET_SOCFPGA_AGILEX
52 bool
53 select ARMV8_MULTIENTRY
54 select ARMV8_SET_SMPEN
Siew Chin Limdbe60eb2020-12-24 18:21:12 +080055 select BINMAN if SPL_ATF
Ley Foon Tan461d2982019-11-27 15:55:32 +080056 select CLK
Chee Hong Ang89ac34d2020-08-07 11:50:05 +080057 select FPGA_INTEL_SDM_MAILBOX
Alif Zakuan Yuslaimia565f702025-02-18 16:34:52 +080058 select GICV2
Ley Foon Tan461d2982019-11-27 15:55:32 +080059 select NCORE_CACHE
60 select SPL_CLK if SPL
Siew Chin Lim8a714162021-03-01 20:04:10 +080061 select TARGET_SOCFPGA_SOC64
Ley Foon Tan461d2982019-11-27 15:55:32 +080062
Jit Loon Lim977071e2024-03-12 22:01:03 +080063config TARGET_SOCFPGA_AGILEX5
64 bool
65 select BINMAN if SPL_ATF
66 select CLK
67 select FPGA_INTEL_SDM_MAILBOX
Jit Loon Lim977071e2024-03-12 22:01:03 +080068 select SPL_CLK if SPL
69 select TARGET_SOCFPGA_SOC64
70
Marek Vasut822e7952015-08-02 21:57:57 +020071config TARGET_SOCFPGA_ARRIA5
72 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -060073 select TARGET_SOCFPGA_GEN5
Marek Vasut822e7952015-08-02 21:57:57 +020074
Ley Foon Tan5b7cea62017-04-26 02:44:48 +080075config TARGET_SOCFPGA_ARRIA10
76 bool
Alif Zakuan Yuslaimia565f702025-02-18 16:34:52 +080077 select GICV2
Ley Foon Tan17b9ba62019-05-06 09:55:59 +080078 select SPL_ALTERA_SDRAM
Michal Simek7e7ba3b2018-07-23 15:55:15 +020079 select SPL_BOARD_INIT if SPL
Ley Foon Tan1d07b3e2020-04-07 15:43:14 +080080 select SPL_CACHE if SPL
Marek Vasute1dcd622018-07-30 15:56:19 +020081 select CLK
82 select SPL_CLK if SPL
Marek Vasut69fbb882018-08-13 18:32:38 +020083 select DM_I2C
Marek Vasut700b2c62018-08-13 18:32:38 +020084 select DM_RESET
85 select SPL_DM_RESET if SPL
Marek Vasut04c8f4f2018-08-13 20:06:46 +020086 select REGMAP
87 select SPL_REGMAP if SPL
88 select SYSCON
89 select SPL_SYSCON if SPL
90 select ETH_DESIGNWARE_SOCFPGA
Simon Goldschmidtb1c42692019-04-09 21:02:05 +020091 imply FPGA_SOCFPGA
Simon Glass7611ac62019-09-25 08:56:27 -060092 imply SPL_USE_TINY_PRINTF
Ley Foon Tan5b7cea62017-04-26 02:44:48 +080093
Michał Barnaś8fdccae2024-03-19 18:18:13 +000094config SOCFPGA_ARRIA10_ALWAYS_REPROGRAM
95 bool "Always reprogram Arria 10 FPGA"
96 depends on TARGET_SOCFPGA_ARRIA10
97 help
98 Arria 10 FPGA is only programmed during the cold boot.
99 This option forces the FPGA to be reprogrammed every reboot,
100 allowing to change the bitstream and apply it with warm reboot.
101
Marek Vasut822e7952015-08-02 21:57:57 +0200102config TARGET_SOCFPGA_CYCLONE5
103 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600104 select TARGET_SOCFPGA_GEN5
105
106config TARGET_SOCFPGA_GEN5
107 bool
Ley Foon Tan17b9ba62019-05-06 09:55:59 +0800108 select SPL_ALTERA_SDRAM
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200109 imply FPGA_SOCFPGA
Simon Goldschmidt20fd7de2019-06-13 21:50:28 +0200110 imply SPL_SIZE_LIMIT_SUBTRACT_GD
111 imply SPL_SIZE_LIMIT_SUBTRACT_MALLOC
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200112 imply SPL_STACK_R
113 imply SPL_SYS_MALLOC_SIMPLE
Simon Glass7611ac62019-09-25 08:56:27 -0600114 imply SPL_USE_TINY_PRINTF
Marek Vasut822e7952015-08-02 21:57:57 +0200115
Siew Chin Lim988bfe42021-08-10 11:26:42 +0800116config TARGET_SOCFPGA_N5X
117 bool
118 select ARMV8_MULTIENTRY
119 select ARMV8_SET_SMPEN
120 select BINMAN if SPL_ATF
121 select CLK
Alif Zakuan Yuslaimia565f702025-02-18 16:34:52 +0800122 select GICV2
Siew Chin Lim988bfe42021-08-10 11:26:42 +0800123 select FPGA_INTEL_SDM_MAILBOX
124 select NCORE_CACHE
125 select SPL_ALTERA_SDRAM
126 select SPL_CLK if SPL
127 select TARGET_SOCFPGA_SOC64
128
129config TARGET_SOCFPGA_N5X_SOCDK
130 bool "Intel eASIC SoCDK (N5X)"
131 select TARGET_SOCFPGA_N5X
132
Siew Chin Lim8a714162021-03-01 20:04:10 +0800133config TARGET_SOCFPGA_SOC64
134 bool
135
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800136config TARGET_SOCFPGA_STRATIX10
137 bool
138 select ARMV8_MULTIENTRY
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800139 select ARMV8_SET_SMPEN
Siew Chin Limdbe60eb2020-12-24 18:21:12 +0800140 select BINMAN if SPL_ATF
Chee Hong Ang14192452020-08-07 11:50:03 +0800141 select FPGA_INTEL_SDM_MAILBOX
Alif Zakuan Yuslaimia565f702025-02-18 16:34:52 +0800142 select GICV2
Siew Chin Lim8a714162021-03-01 20:04:10 +0800143 select TARGET_SOCFPGA_SOC64
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800144
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900145choice
146 prompt "Altera SOCFPGA board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500147 optional
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900148
Ley Foon Tan461d2982019-11-27 15:55:32 +0800149config TARGET_SOCFPGA_AGILEX_SOCDK
150 bool "Intel SOCFPGA SoCDK (Agilex)"
151 select TARGET_SOCFPGA_AGILEX
152
Jit Loon Lim977071e2024-03-12 22:01:03 +0800153config TARGET_SOCFPGA_AGILEX5_SOCDK
154 bool "Intel SOCFPGA SoCDK (Agilex5)"
155 select TARGET_SOCFPGA_AGILEX5
156
Wolfgang Grandegger7789aab22019-05-12 19:25:18 +0200157config TARGET_SOCFPGA_ARIES_MCVEVK
158 bool "Aries MCVEVK (Cyclone V)"
159 select TARGET_SOCFPGA_CYCLONE5
160
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800161config TARGET_SOCFPGA_ARRIA10_SOCDK
162 bool "Altera SOCFPGA SoCDK (Arria 10)"
163 select TARGET_SOCFPGA_ARRIA10
164
Holger Brunckddef8892020-02-19 19:55:14 +0100165config TARGET_SOCFPGA_ARRIA5_SECU1
166 bool "ABB SECU1 (Arria V)"
167 select TARGET_SOCFPGA_ARRIA5
168 select VENDOR_KM
169
Marek Vasut822e7952015-08-02 21:57:57 +0200170config TARGET_SOCFPGA_ARRIA5_SOCDK
171 bool "Altera SOCFPGA SoCDK (Arria V)"
172 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900173
Paweł Anikiel5ee903d2022-06-17 12:47:20 +0200174config TARGET_SOCFPGA_CHAMELEONV3
175 bool "Google Chameleon v3 (Arria 10)"
176 select TARGET_SOCFPGA_ARRIA10
177
Marek Vasut822e7952015-08-02 21:57:57 +0200178config TARGET_SOCFPGA_CYCLONE5_SOCDK
179 bool "Altera SOCFPGA SoCDK (Cyclone V)"
180 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900181
Marek Vasutb06dad22018-02-24 23:34:00 +0100182config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
183 bool "Devboards DBM-SoC1 (Cyclone V)"
184 select TARGET_SOCFPGA_CYCLONE5
185
Marek Vasut567356a2015-11-23 17:06:27 +0100186config TARGET_SOCFPGA_EBV_SOCRATES
187 bool "EBV SoCrates (Cyclone V)"
188 select TARGET_SOCFPGA_CYCLONE5
189
Pavel Machek9802e872016-06-07 12:37:23 +0200190config TARGET_SOCFPGA_IS1
191 bool "IS1 (Cyclone V)"
192 select TARGET_SOCFPGA_CYCLONE5
193
Marek Vasut13da18c2019-06-27 00:19:31 +0200194config TARGET_SOCFPGA_SOFTING_VINING_FPGA
195 bool "Softing VIN|ING FPGA (Cyclone V)"
Tom Rini22d567e2017-01-22 19:43:11 -0500196 select BOARD_LATE_INIT
Marek Vasutba2ade92015-12-01 18:09:52 +0100197 select TARGET_SOCFPGA_CYCLONE5
198
Marek Vasut2e717ec2016-06-08 02:57:05 +0200199config TARGET_SOCFPGA_SR1500
200 bool "SR1500 (Cyclone V)"
201 select TARGET_SOCFPGA_CYCLONE5
202
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800203config TARGET_SOCFPGA_STRATIX10_SOCDK
204 bool "Intel SOCFPGA SoCDK (Stratix 10)"
205 select TARGET_SOCFPGA_STRATIX10
206
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500207config TARGET_SOCFPGA_TERASIC_DE0_NANO
208 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
209 select TARGET_SOCFPGA_CYCLONE5
210
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700211config TARGET_SOCFPGA_TERASIC_DE10_NANO
212 bool "Terasic DE10-Nano (Cyclone V)"
213 select TARGET_SOCFPGA_CYCLONE5
214
Humberto Navesa563e2e2022-05-22 21:54:57 -0400215config TARGET_SOCFPGA_TERASIC_DE10_STANDARD
216 bool "Terasic DE10-Standard (Cyclone V)"
217 select TARGET_SOCFPGA_CYCLONE5
218
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100219config TARGET_SOCFPGA_TERASIC_DE1_SOC
220 bool "Terasic DE1-SoC (Cyclone V)"
221 select TARGET_SOCFPGA_CYCLONE5
222
Marek Vasutb415bad2015-06-21 17:28:53 +0200223config TARGET_SOCFPGA_TERASIC_SOCKIT
224 bool "Terasic SoCkit (Cyclone V)"
225 select TARGET_SOCFPGA_CYCLONE5
226
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900227endchoice
228
229config SYS_BOARD
Jit Loon Lim977071e2024-03-12 22:01:03 +0800230 default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK
Ley Foon Tan461d2982019-11-27 15:55:32 +0800231 default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
Marek Vasut3f4c5612015-08-10 21:24:53 +0200232 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800233 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Paweł Anikiel5ee903d2022-06-17 12:47:20 +0200234 default "chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
Marek Vasut3f4c5612015-08-10 21:24:53 +0200235 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasutb06dad22018-02-24 23:34:00 +0100236 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500237 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100238 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700239 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Humberto Navesa563e2e2022-05-22 21:54:57 -0400240 default "de10-standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
Pavel Machek9802e872016-06-07 12:37:23 +0200241 default "is1" if TARGET_SOCFPGA_IS1
Wolfgang Grandegger7789aab22019-05-12 19:25:18 +0200242 default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Siew Chin Lim988bfe42021-08-10 11:26:42 +0800243 default "n5x-socdk" if TARGET_SOCFPGA_N5X_SOCDK
Holger Brunckddef8892020-02-19 19:55:14 +0100244 default "secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
Marek Vasutb415bad2015-06-21 17:28:53 +0200245 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100246 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100247 default "sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800248 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut13da18c2019-06-27 00:19:31 +0200249 default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900250
251config SYS_VENDOR
Jit Loon Lim977071e2024-03-12 22:01:03 +0800252 default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK
Ley Foon Tan461d2982019-11-27 15:55:32 +0800253 default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
Siew Chin Lim988bfe42021-08-10 11:26:42 +0800254 default "intel" if TARGET_SOCFPGA_N5X_SOCDK
Marek Vasut822e7952015-08-02 21:57:57 +0200255 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800256 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut822e7952015-08-02 21:57:57 +0200257 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800258 default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
Wolfgang Grandegger7789aab22019-05-12 19:25:18 +0200259 default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasutb06dad22018-02-24 23:34:00 +0100260 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Marek Vasut567356a2015-11-23 17:06:27 +0100261 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Paweł Anikiel5ee903d2022-06-17 12:47:20 +0200262 default "google" if TARGET_SOCFPGA_CHAMELEONV3
Holger Brunckddef8892020-02-19 19:55:14 +0100263 default "keymile" if TARGET_SOCFPGA_ARRIA5_SECU1
Marek Vasut13da18c2019-06-27 00:19:31 +0200264 default "softing" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500265 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100266 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700267 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Humberto Navesa563e2e2022-05-22 21:54:57 -0400268 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
Marek Vasutb415bad2015-06-21 17:28:53 +0200269 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900270
271config SYS_SOC
272 default "socfpga"
273
274config SYS_CONFIG_NAME
Jit Loon Lim977071e2024-03-12 22:01:03 +0800275 default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK
Ley Foon Tan461d2982019-11-27 15:55:32 +0800276 default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
Holger Brunckddef8892020-02-19 19:55:14 +0100277 default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500278 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800279 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Paweł Anikiel5ee903d2022-06-17 12:47:20 +0200280 default "socfpga_chameleonv3" if TARGET_SOCFPGA_CHAMELEONV3
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500281 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasutb06dad22018-02-24 23:34:00 +0100282 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500283 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100284 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700285 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Humberto Navesa563e2e2022-05-22 21:54:57 -0400286 default "socfpga_de10_standard" if TARGET_SOCFPGA_TERASIC_DE10_STANDARD
Pavel Machek9802e872016-06-07 12:37:23 +0200287 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Wolfgang Grandegger7789aab22019-05-12 19:25:18 +0200288 default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Siew Chin Lim988bfe42021-08-10 11:26:42 +0800289 default "socfpga_n5x_socdk" if TARGET_SOCFPGA_N5X_SOCDK
Marek Vasutb415bad2015-06-21 17:28:53 +0200290 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100291 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100292 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800293 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasut13da18c2019-06-27 00:19:31 +0200294 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900295
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900296endif