Blame - arch/arm/mach-socfpga/Kconfig - filogic/uboot

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Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	1	if ARCH_SOCFPGA
				2
Simon Glass	f2a8946	2016-09-12 23:18:41 -0600	[diff] [blame]	3	config SPL_LIBCOMMON_SUPPORT
				4	default y
				5
Simon Glass	f6de257	2016-09-12 23:18:42 -0600	[diff] [blame]	6	config SPL_LIBDISK_SUPPORT
				7	default y
				8
Simon Glass	b16c92c	2016-09-12 23:18:43 -0600	[diff] [blame]	9	config SPL_LIBGENERIC_SUPPORT
				10	default y
				11
Simon Glass	bd58f1d	2016-09-12 23:18:44 -0600	[diff] [blame]	12	config SPL_MMC_SUPPORT
				13	default y if DM_MMC
				14
Simon Glass	d5a307a	2016-09-12 23:18:48 -0600	[diff] [blame]	15	config SPL_NAND_SUPPORT
				16	default y if SPL_NAND_DENALI
				17
Simon Glass	e076d6f	2016-09-12 23:18:56 -0600	[diff] [blame]	18	config SPL_SERIAL_SUPPORT
				19	default y
				20
Simon Glass	219d612	2016-09-12 23:18:57 -0600	[diff] [blame]	21	config SPL_SPI_FLASH_SUPPORT
Simon Glass	b24fdca	2016-09-12 23:18:58 -0600	[diff] [blame]	22	default y if SPL_SPI_SUPPORT
				23
				24	config SPL_SPI_SUPPORT
Simon Glass	219d612	2016-09-12 23:18:57 -0600	[diff] [blame]	25	default y if DM_SPI
				26
Simon Glass	6662a9f	2016-09-12 23:19:02 -0600	[diff] [blame]	27	config SPL_WATCHDOG_SUPPORT
				28	default y
				29
Dalon Westergreen	8d770f4	2017-02-10 17:15:34 -0800	[diff] [blame]	30	config SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
				31	default y
				32
				33	config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
				34	default 0xa2
				35
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	36	config TARGET_SOCFPGA_ARRIA5
				37	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame]	38	select TARGET_SOCFPGA_GEN5
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	39
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	40	config TARGET_SOCFPGA_ARRIA10
				41	bool
Ley Foon Tan	48fcc4a	2017-05-03 17:13:32 +0800	[diff] [blame]	42	select SPL_BOARD_INIT if SPL
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	43
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	44	config TARGET_SOCFPGA_CYCLONE5
				45	bool
Dinh Nguyen	677a16f	2015-12-02 13:31:25 -0600	[diff] [blame]	46	select TARGET_SOCFPGA_GEN5
				47
				48	config TARGET_SOCFPGA_GEN5
				49	bool
Ley Foon Tan	016539e	2017-04-05 17:32:51 +0800	[diff] [blame]	50	select ALTERA_SDRAM
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	51
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	52	choice
				53	prompt "Altera SOCFPGA board select"
Joe Hershberger	f069960	2015-05-12 14:46:23 -0500	[diff] [blame]	54	optional
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	55
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	56	config TARGET_SOCFPGA_ARRIA10_SOCDK
				57	bool "Altera SOCFPGA SoCDK (Arria 10)"
				58	select TARGET_SOCFPGA_ARRIA10
				59
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	60	config TARGET_SOCFPGA_ARRIA5_SOCDK
				61	bool "Altera SOCFPGA SoCDK (Arria V)"
				62	select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	63
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	64	config TARGET_SOCFPGA_CYCLONE5_SOCDK
				65	bool "Altera SOCFPGA SoCDK (Cyclone V)"
				66	select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	67
Marek Vasut	9d6c56b	2017-04-05 13:17:03 +0200	[diff] [blame]	68	config TARGET_SOCFPGA_ARIES_MCVEVK
				69	bool "Aries MCVEVK (Cyclone V)"
Marek Vasut	8e8b62a	2015-08-03 01:37:28 +0200	[diff] [blame]	70	select TARGET_SOCFPGA_CYCLONE5
				71
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame^]	72	config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
				73	bool "Devboards DBM-SoC1 (Cyclone V)"
				74	select TARGET_SOCFPGA_CYCLONE5
				75
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	76	config TARGET_SOCFPGA_EBV_SOCRATES
				77	bool "EBV SoCrates (Cyclone V)"
				78	select TARGET_SOCFPGA_CYCLONE5
				79
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	80	config TARGET_SOCFPGA_IS1
				81	bool "IS1 (Cyclone V)"
				82	select TARGET_SOCFPGA_CYCLONE5
				83
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	84	config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
				85	bool "samtec VIN\|ING FPGA (Cyclone V)"
Tom Rini	22d567e	2017-01-22 19:43:11 -0500	[diff] [blame]	86	select BOARD_LATE_INIT
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	87	select TARGET_SOCFPGA_CYCLONE5
				88
Marek Vasut	2e717ec	2016-06-08 02:57:05 +0200	[diff] [blame]	89	config TARGET_SOCFPGA_SR1500
				90	bool "SR1500 (Cyclone V)"
				91	select TARGET_SOCFPGA_CYCLONE5
				92
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	93	config TARGET_SOCFPGA_TERASIC_DE0_NANO
				94	bool "Terasic DE0-Nano-Atlas (Cyclone V)"
				95	select TARGET_SOCFPGA_CYCLONE5
				96
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	97	config TARGET_SOCFPGA_TERASIC_DE10_NANO
				98	bool "Terasic DE10-Nano (Cyclone V)"
				99	select TARGET_SOCFPGA_CYCLONE5
				100
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	101	config TARGET_SOCFPGA_TERASIC_DE1_SOC
				102	bool "Terasic DE1-SoC (Cyclone V)"
				103	select TARGET_SOCFPGA_CYCLONE5
				104
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	105	config TARGET_SOCFPGA_TERASIC_SOCKIT
				106	bool "Terasic SoCkit (Cyclone V)"
				107	select TARGET_SOCFPGA_CYCLONE5
				108
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	109	endchoice
				110
				111	config SYS_BOARD
Marek Vasut	3f4c561	2015-08-10 21:24:53 +0200	[diff] [blame]	112	default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	113	default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	3f4c561	2015-08-10 21:24:53 +0200	[diff] [blame]	114	default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame^]	115	default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	116	default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	117	default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	118	default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	119	default "is1" if TARGET_SOCFPGA_IS1
Marek Vasut	9d6c56b	2017-04-05 13:17:03 +0200	[diff] [blame]	120	default "mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	121	default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	122	default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	123	default "sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	124	default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	125
				126	config SYS_VENDOR
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	127	default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	128	default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut	822e795	2015-08-02 21:57:57 +0200	[diff] [blame]	129	default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	9d6c56b	2017-04-05 13:17:03 +0200	[diff] [blame]	130	default "aries" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame^]	131	default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	132	default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	133	default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	134	default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	135	default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	136	default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	137	default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	138
				139	config SYS_SOC
				140	default "socfpga"
				141
				142	config SYS_CONFIG_NAME
Dinh Nguyen	16f6ffd	2015-09-22 17:01:32 -0500	[diff] [blame]	143	default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan	5b7cea6	2017-04-26 02:44:48 +0800	[diff] [blame]	144	default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Dinh Nguyen	16f6ffd	2015-09-22 17:01:32 -0500	[diff] [blame]	145	default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasut	b06dad2	2018-02-24 23:34:00 +0100	[diff] [blame^]	146	default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyen	c3364da	2015-09-01 17:41:52 -0500	[diff] [blame]	147	default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin	705bf37	2016-11-14 16:07:10 +0100	[diff] [blame]	148	default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen	7a0fe0d	2017-04-18 08:11:16 -0700	[diff] [blame]	149	default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek	9802e87	2016-06-07 12:37:23 +0200	[diff] [blame]	150	default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasut	9d6c56b	2017-04-05 13:17:03 +0200	[diff] [blame]	151	default "socfpga_mcvevk" if TARGET_SOCFPGA_ARIES_MCVEVK
Marek Vasut	b415bad	2015-06-21 17:28:53 +0200	[diff] [blame]	152	default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut	567356a	2015-11-23 17:06:27 +0100	[diff] [blame]	153	default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roese	bf5ed2e	2015-11-18 11:06:09 +0100	[diff] [blame]	154	default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Marek Vasut	ba2ade9	2015-12-01 18:09:52 +0100	[diff] [blame]	155	default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada	144a3e0	2015-04-21 20:38:20 +0900	[diff] [blame]	156
				157	endif