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git01.mediatek.com / filogic / uboot / b1c4269991839c571de04b2d0b11a581cdfa5705 / . / arch / arm / mach-socfpga / Kconfig
blob: 3c6c63067dc82d9afa1b6fd984e5b0dd10673853 [file] [log] [blame]
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]1if ARCH_SOCFPGA
2
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame^]3config NR_DRAM_BANKS
4 default 1
5
6config SPL_STACK_R_ADDR
7 default 0x00800000 if TARGET_SOCFPGA_GEN5
8
Dalon Westergreen8d770f42017-02-10 17:15:34 -0800[diff] [blame]9config SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION_TYPE
10 default 0xa2
11
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame^]12config SYS_MALLOC_F_LEN
13 default 0x2000 if TARGET_SOCFPGA_ARRIA10
14 default 0x2000 if TARGET_SOCFPGA_GEN5
15
16config SYS_TEXT_BASE
17 default 0x01000040 if TARGET_SOCFPGA_ARRIA10
18 default 0x01000040 if TARGET_SOCFPGA_GEN5
19
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]20config TARGET_SOCFPGA_ARRIA5
21 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]22 select TARGET_SOCFPGA_GEN5
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]23
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]24config TARGET_SOCFPGA_ARRIA10
25 bool
Tien Fong Chee4d447a52017-12-05 15:58:03 +0800[diff] [blame]26 select ALTERA_SDRAM
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]27 select SPL_BOARD_INIT if SPL
Marek Vasute1dcd622018-07-30 15:56:19 +0200[diff] [blame]28 select CLK
29 select SPL_CLK if SPL
Marek Vasut69fbb882018-08-13 18:32:38 +0200[diff] [blame]30 select DM_I2C
Marek Vasut700b2c62018-08-13 18:32:38 +0200[diff] [blame]31 select DM_RESET
32 select SPL_DM_RESET if SPL
Marek Vasut04c8f4f2018-08-13 20:06:46 +0200[diff] [blame]33 select REGMAP
34 select SPL_REGMAP if SPL
35 select SYSCON
36 select SPL_SYSCON if SPL
37 select ETH_DESIGNWARE_SOCFPGA
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame^]38 imply FPGA_SOCFPGA
39 imply USE_TINY_PRINTF
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]40
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]41config TARGET_SOCFPGA_CYCLONE5
42 bool
Dinh Nguyen677a16f2015-12-02 13:31:25 -0600[diff] [blame]43 select TARGET_SOCFPGA_GEN5
44
45config TARGET_SOCFPGA_GEN5
46 bool
Ley Foon Tan016539e2017-04-05 17:32:51 +0800[diff] [blame]47 select ALTERA_SDRAM
Simon Goldschmidtb1c42692019-04-09 21:02:05 +0200[diff] [blame^]48 imply FPGA_SOCFPGA
49 imply SPL_STACK_R
50 imply SPL_SYS_MALLOC_SIMPLE
51 imply USE_TINY_PRINTF
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]52
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]53config TARGET_SOCFPGA_STRATIX10
54 bool
55 select ARMV8_MULTIENTRY
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]56 select ARMV8_SET_SMPEN
Michal Simek7e7ba3b2018-07-23 15:55:15 +0200[diff] [blame]57 select ARMV8_SPIN_TABLE
Ang, Chee Hongda9640e2018-12-19 18:35:16 -0800[diff] [blame]58 select FPGA_STRATIX10
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]59
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]60choice
61 prompt "Altera SOCFPGA board select"
Joe Hershbergerf0699602015-05-12 14:46:23 -0500[diff] [blame]62 optional
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]63
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]64config TARGET_SOCFPGA_ARRIA10_SOCDK
65 bool "Altera SOCFPGA SoCDK (Arria 10)"
66 select TARGET_SOCFPGA_ARRIA10
67
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]68config TARGET_SOCFPGA_ARRIA5_SOCDK
69 bool "Altera SOCFPGA SoCDK (Arria V)"
70 select TARGET_SOCFPGA_ARRIA5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]71
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]72config TARGET_SOCFPGA_CYCLONE5_SOCDK
73 bool "Altera SOCFPGA SoCDK (Cyclone V)"
74 select TARGET_SOCFPGA_CYCLONE5
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]75
Marek Vasutb06dad22018-02-24 23:34:00 +0100[diff] [blame]76config TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
77 bool "Devboards DBM-SoC1 (Cyclone V)"
78 select TARGET_SOCFPGA_CYCLONE5
79
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]80config TARGET_SOCFPGA_EBV_SOCRATES
81 bool "EBV SoCrates (Cyclone V)"
82 select TARGET_SOCFPGA_CYCLONE5
83
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]84config TARGET_SOCFPGA_IS1
85 bool "IS1 (Cyclone V)"
86 select TARGET_SOCFPGA_CYCLONE5
87
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]88config TARGET_SOCFPGA_SAMTEC_VINING_FPGA
89 bool "samtec VIN|ING FPGA (Cyclone V)"
Tom Rini22d567e2017-01-22 19:43:11 -0500[diff] [blame]90 select BOARD_LATE_INIT
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]91 select TARGET_SOCFPGA_CYCLONE5
92
Marek Vasut2e717ec2016-06-08 02:57:05 +0200[diff] [blame]93config TARGET_SOCFPGA_SR1500
94 bool "SR1500 (Cyclone V)"
95 select TARGET_SOCFPGA_CYCLONE5
96
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]97config TARGET_SOCFPGA_STRATIX10_SOCDK
98 bool "Intel SOCFPGA SoCDK (Stratix 10)"
99 select TARGET_SOCFPGA_STRATIX10
100
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]101config TARGET_SOCFPGA_TERASIC_DE0_NANO
102 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
103 select TARGET_SOCFPGA_CYCLONE5
104
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700[diff] [blame]105config TARGET_SOCFPGA_TERASIC_DE10_NANO
106 bool "Terasic DE10-Nano (Cyclone V)"
107 select TARGET_SOCFPGA_CYCLONE5
108
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100[diff] [blame]109config TARGET_SOCFPGA_TERASIC_DE1_SOC
110 bool "Terasic DE1-SoC (Cyclone V)"
111 select TARGET_SOCFPGA_CYCLONE5
112
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]113config TARGET_SOCFPGA_TERASIC_SOCKIT
114 bool "Terasic SoCkit (Cyclone V)"
115 select TARGET_SOCFPGA_CYCLONE5
116
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]117endchoice
118
119config SYS_BOARD
Marek Vasut3f4c5612015-08-10 21:24:53 +0200[diff] [blame]120 default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]121 default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut3f4c5612015-08-10 21:24:53 +0200[diff] [blame]122 default "cyclone5-socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasutb06dad22018-02-24 23:34:00 +0100[diff] [blame]123 default "dbm-soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]124 default "de0-nano-soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100[diff] [blame]125 default "de1-soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700[diff] [blame]126 default "de10-nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]127 default "is1" if TARGET_SOCFPGA_IS1
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]128 default "sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]129 default "socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]130 default "sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]131 default "stratix10-socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]132 default "vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]133
134config SYS_VENDOR
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]135 default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]136 default "altera" if TARGET_SOCFPGA_ARRIA10_SOCDK
Marek Vasut822e7952015-08-02 21:57:57 +0200[diff] [blame]137 default "altera" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]138 default "altera" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasutb06dad22018-02-24 23:34:00 +0100[diff] [blame]139 default "devboards" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]140 default "ebv" if TARGET_SOCFPGA_EBV_SOCRATES
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]141 default "samtec" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]142 default "terasic" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100[diff] [blame]143 default "terasic" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700[diff] [blame]144 default "terasic" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]145 default "terasic" if TARGET_SOCFPGA_TERASIC_SOCKIT
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]146
147config SYS_SOC
148 default "socfpga"
149
150config SYS_CONFIG_NAME
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500[diff] [blame]151 default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
Ley Foon Tan5b7cea62017-04-26 02:44:48 +0800[diff] [blame]152 default "socfpga_arria10_socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
Dinh Nguyen16f6ffd2015-09-22 17:01:32 -0500[diff] [blame]153 default "socfpga_cyclone5_socdk" if TARGET_SOCFPGA_CYCLONE5_SOCDK
Marek Vasutb06dad22018-02-24 23:34:00 +0100[diff] [blame]154 default "socfpga_dbm_soc1" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1
Dinh Nguyenc3364da2015-09-01 17:41:52 -0500[diff] [blame]155 default "socfpga_de0_nano_soc" if TARGET_SOCFPGA_TERASIC_DE0_NANO
Anatolij Gustschin705bf372016-11-14 16:07:10 +0100[diff] [blame]156 default "socfpga_de1_soc" if TARGET_SOCFPGA_TERASIC_DE1_SOC
Dalon Westergreen7a0fe0d2017-04-18 08:11:16 -0700[diff] [blame]157 default "socfpga_de10_nano" if TARGET_SOCFPGA_TERASIC_DE10_NANO
Pavel Machek9802e872016-06-07 12:37:23 +0200[diff] [blame]158 default "socfpga_is1" if TARGET_SOCFPGA_IS1
Marek Vasutb415bad2015-06-21 17:28:53 +0200[diff] [blame]159 default "socfpga_sockit" if TARGET_SOCFPGA_TERASIC_SOCKIT
Marek Vasut567356a2015-11-23 17:06:27 +0100[diff] [blame]160 default "socfpga_socrates" if TARGET_SOCFPGA_EBV_SOCRATES
Stefan Roesebf5ed2e2015-11-18 11:06:09 +0100[diff] [blame]161 default "socfpga_sr1500" if TARGET_SOCFPGA_SR1500
Ley Foon Tan9c407b52018-05-24 00:17:32 +0800[diff] [blame]162 default "socfpga_stratix10_socdk" if TARGET_SOCFPGA_STRATIX10_SOCDK
Marek Vasutba2ade92015-12-01 18:09:52 +0100[diff] [blame]163 default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
Masahiro Yamada144a3e02015-04-21 20:38:20 +0900[diff] [blame]164
165endif