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Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# I2C subsystem configuration
3#
4
Simon Glass8e85e3c2021-07-10 21:14:35 -06005menuconfig I2C
6 bool "I2C support"
7 default y
8 help
9 Note:
10 This is a stand-in for an option to enable I2C support. In fact this
11 simply enables building of the I2C directory for U-Boot. The actual
12 I2C feature is enabled by DM_I2C (for driver model) and
13 the #define CONFIG_SYS_I2C_LEGACY (for the legacy I2C stack).
14
15 So at present there is no need to ever disable this option.
16
17 Eventually it will:
18
19 Enable support for the I2C (Inter-Integrated Circuit) bus in U-Boot.
20 I2C works with a clock and data line which can be driven by a
21 one or more masters or slaves. It is a fairly complex bus but is
22 widely used as it only needs two lines for communication. Speeds of
23 400kbps are typical but up to 3.4Mbps is supported by some
24 hardware. Enable this option to build the drivers in drivers/i2c as
25 part of a U-Boot build.
26
27if I2C
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +090028
Masahiro Yamadacd5cf8e2015-01-13 12:44:35 +090029config DM_I2C
30 bool "Enable Driver Model for I2C drivers"
31 depends on DM
32 help
Przemyslaw Marczake5fa1212015-03-31 18:57:17 +020033 Enable driver model for I2C. The I2C uclass interface: probe, read,
34 write and speed, is implemented with the bus drivers operations,
35 which provide methods for bus setting and data transfer. Each chip
Simon Glass71fa5b42020-12-03 16:55:18 -070036 device (bus child) info is kept as parent plat. The interface
Bartosz Golaszewski1e4450c2019-07-29 08:58:00 +020037 is defined in include/i2c.h.
Simon Glasse200ee22015-02-13 12:20:48 -070038
Igor Opaniuk964f2322021-02-09 13:52:43 +020039config SPL_DM_I2C
40 bool "Enable Driver Model for I2C drivers in SPL"
41 depends on SPL_DM && DM_I2C
42 default y
43 help
44 Enable driver model for I2C. The I2C uclass interface: probe, read,
45 write and speed, is implemented with the bus drivers operations,
46 which provide methods for bus setting and data transfer. Each chip
47 device (bus child) info is kept as parent platdata. The interface
48 is defined in include/i2c.h.
49
Tom Rini52b2e262021-08-18 23:12:24 -040050config SYS_I2C_LEGACY
51 bool "Enable legacy I2C subsystem and drivers"
52 depends on !DM_I2C
53 help
54 Enable the legacy I2C subsystem and drivers. While this is
55 deprecated in U-Boot itself, this can be useful in some situations
56 in SPL or TPL.
57
58config SPL_SYS_I2C_LEGACY
59 bool "Enable legacy I2C subsystem and drivers in SPL"
60 depends on SUPPORT_SPL && !SPL_DM_I2C
61 help
62 Enable the legacy I2C subsystem and drivers in SPL. This is useful
63 in some size constrained situations.
64
65config TPL_SYS_I2C_LEGACY
66 bool "Enable legacy I2C subsystem and drivers in TPL"
67 depends on SUPPORT_TPL && !SPL_DM_I2C
68 help
69 Enable the legacy I2C subsystem and drivers in TPL. This is useful
70 in some size constrained situations.
71
Tom Rini714482a2021-08-18 23:12:25 -040072config SYS_I2C_EARLY_INIT
73 bool "Enable legacy I2C subsystem early in boot"
74 depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC
75 help
76 Add the function prototype for i2c_early_init_f which is called in
77 board_early_init_f.
78
Simon Glass9ad07af2015-08-03 08:19:23 -060079config I2C_CROS_EC_TUNNEL
80 tristate "Chrome OS EC tunnel I2C bus"
81 depends on CROS_EC
82 help
83 This provides an I2C bus that will tunnel i2c commands through to
84 the other side of the Chrome OS EC to the I2C bus connected there.
85 This will work whatever the interface used to talk to the EC (SPI,
86 I2C or LPC). Some Chromebooks use this when the hardware design
87 does not allow direct access to the main PMIC from the AP.
88
Simon Glasseb2cc512015-08-03 08:19:24 -060089config I2C_CROS_EC_LDO
90 bool "Provide access to LDOs on the Chrome OS EC"
91 depends on CROS_EC
92 ---help---
93 On many Chromebooks the main PMIC is inaccessible to the AP. This is
94 often dealt with by using an I2C pass-through interface provided by
95 the EC. On some unfortunate models (e.g. Spring) the pass-through
96 is not available, and an LDO message is available instead. This
97 option enables a driver which provides very basic access to those
98 regulators, via the EC. We implement this as an I2C bus which
99 emulates just the TPS65090 messages we know about. This is done to
100 avoid duplicating the logic in the TPS65090 regulator driver for
101 enabling/disabling an LDO.
Simon Glass9ad07af2015-08-03 08:19:23 -0600102
Lukasz Majewski0a556272017-03-21 12:08:25 +0100103config I2C_SET_DEFAULT_BUS_NUM
104 bool "Set default I2C bus number"
105 depends on DM_I2C
106 help
107 Set default number of I2C bus to be accessed. This option provides
108 behaviour similar to old (i.e. pre DM) I2C bus driver.
109
110config I2C_DEFAULT_BUS_NUMBER
111 hex "I2C default bus number"
112 depends on I2C_SET_DEFAULT_BUS_NUM
113 default 0x0
114 help
115 Number of default I2C bus to use
116
Przemyslaw Marczakd3aa7e12015-03-31 18:57:18 +0200117config DM_I2C_GPIO
118 bool "Enable Driver Model for software emulated I2C bus driver"
119 depends on DM_I2C && DM_GPIO
120 help
121 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
122 configuration is given by the device tree. Kernel-style device tree
123 bindings are supported.
124 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
125
Igor Opaniuk964f2322021-02-09 13:52:43 +0200126config SPL_DM_I2C_GPIO
127 bool "Enable Driver Model for software emulated I2C bus driver in SPL"
Simon Glass035939e2021-07-10 21:14:30 -0600128 depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO
Igor Opaniuk964f2322021-02-09 13:52:43 +0200129 default y
130 help
131 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
132 configuration is given by the device tree. Kernel-style device tree
133 bindings are supported.
134 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
135
Songjun Wu26d88282016-06-20 13:22:38 +0800136config SYS_I2C_AT91
137 bool "Atmel I2C driver"
138 depends on DM_I2C && ARCH_AT91
139 help
140 Add support for the Atmel I2C driver. A serious problem is that there
141 is no documented way to issue repeated START conditions for more than
142 two messages, as needed to support combined I2C messages. Use the
143 i2c-gpio driver unless your system can cope with this limitation.
144 Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
145
Rayagonda Kokatanurd5dc36f2020-04-08 11:12:27 +0530146config SYS_I2C_IPROC
147 bool "Broadcom I2C driver"
148 depends on DM_I2C
149 help
150 Broadcom I2C driver.
151 Add support for Broadcom I2C driver.
152 Say yes here to to enable the Broadco I2C driver.
153
mario.six@gdsys.cc349686c2016-04-25 08:31:09 +0200154config SYS_I2C_FSL
155 bool "Freescale I2C bus driver"
mario.six@gdsys.cc349686c2016-04-25 08:31:09 +0200156 help
157 Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
158 MPC85xx processors.
159
Tom Rinibe94c762021-08-18 23:12:35 -0400160if SYS_I2C_FSL && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
161config SYS_FSL_I2C_OFFSET
162 hex "Offset from the IMMR of the address of the first I2C controller"
163
164config SYS_FSL_HAS_I2C2_OFFSET
165 bool "Support a second I2C controller"
166
167config SYS_FSL_I2C2_OFFSET
168 hex "Offset from the IMMR of the address of the second I2C controller"
169 depends on SYS_FSL_HAS_I2C2_OFFSET
170
171config SYS_FSL_HAS_I2C3_OFFSET
172 bool "Support a third I2C controller"
173
174config SYS_FSL_I2C3_OFFSET
175 hex "Offset from the IMMR of the address of the third I2C controller"
176 depends on SYS_FSL_HAS_I2C3_OFFSET
177
178config SYS_FSL_HAS_I2C4_OFFSET
179 bool "Support a fourth I2C controller"
180
181config SYS_FSL_I2C4_OFFSET
182 hex "Offset from the IMMR of the address of the fourth I2C controller"
183 depends on SYS_FSL_HAS_I2C4_OFFSET
184endif
185
Moritz Fischer0075dac2015-12-28 09:47:11 -0800186config SYS_I2C_CADENCE
187 tristate "Cadence I2C Controller"
Michal Simekc28665d2020-08-06 15:18:36 +0200188 depends on DM_I2C
Moritz Fischer0075dac2015-12-28 09:47:11 -0800189 help
190 Say yes here to select Cadence I2C Host Controller. This controller is
191 e.g. used by Xilinx Zynq.
192
Arthur Life661ba2020-06-01 12:56:31 -0700193config SYS_I2C_CA
194 tristate "Cortina-Access I2C Controller"
195 depends on DM_I2C && CORTINA_PLATFORM
196 default n
197 help
198 Add support for the Cortina Access I2C host controller.
199 Say yes here to select Cortina-Access I2C Host Controller.
200
Adam Forddecc8952018-08-10 05:05:22 -0500201config SYS_I2C_DAVINCI
202 bool "Davinci I2C Controller"
203 depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
204 help
205 Say yes here to add support for Davinci and Keystone I2C controller
206
Stefan Roeseb71955f2016-04-28 09:47:17 +0200207config SYS_I2C_DW
208 bool "Designware I2C Controller"
209 default n
210 help
211 Say yes here to select the Designware I2C Host Controller. This
212 controller is used in various SoCs, e.g. the ST SPEAr, Altera
213 SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
214
maxims@google.com7f613312017-04-17 12:00:30 -0700215config SYS_I2C_ASPEED
216 bool "Aspeed I2C Controller"
217 depends on DM_I2C && ARCH_ASPEED
218 help
219 Say yes here to select Aspeed I2C Host Controller. The driver
220 supports AST2500 and AST2400 controllers, but is very limited.
221 Only single master mode is supported and only byte-by-byte
222 synchronous reads and writes are supported, no Pool Buffers or DMA.
223
Simon Glass5e66fdc2016-01-17 16:11:44 -0700224config SYS_I2C_INTEL
225 bool "Intel I2C/SMBUS driver"
226 depends on DM_I2C
227 help
228 Add support for the Intel SMBUS driver. So far this driver is just
229 a stub which perhaps some basic init. There is no implementation of
230 the I2C API meaning that any I2C operations will immediately fail
231 for now.
232
Peng Fand684adb2017-02-24 09:54:18 +0800233config SYS_I2C_IMX_LPI2C
234 bool "NXP i.MX LPI2C driver"
Peng Fand684adb2017-02-24 09:54:18 +0800235 help
236 Add support for the NXP i.MX LPI2C driver.
237
Trevor Woerner5f37e502021-06-10 22:37:08 -0400238config SYS_I2C_LPC32XX
239 bool "LPC32XX I2C driver"
240 depends on ARCH_LPC32XX
241 help
242 Enable support for the LPC32xx I2C driver.
243
Beniamino Galvanid5b199c2017-10-29 10:09:00 +0100244config SYS_I2C_MESON
245 bool "Amlogic Meson I2C driver"
246 depends on DM_I2C && ARCH_MESON
247 help
Beniamino Galvani83b153d2017-11-26 17:40:54 +0100248 Add support for the I2C controller available in Amlogic Meson
249 SoCs. The controller supports programmable bus speed including
250 standard (100kbits/s) and fast (400kbit/s) speed and allows the
251 software to define a flexible format of the bit streams. It has an
252 internal buffer holding up to 8 bytes for transfers and supports
253 both 7-bit and 10-bit addresses.
Beniamino Galvanid5b199c2017-10-29 10:09:00 +0100254
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100255config SYS_I2C_MXC
Sriram Dash7122a0c2018-02-06 11:26:30 +0530256 bool "NXP MXC I2C driver"
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100257 help
Chris Packham94d0d3d2019-01-13 22:13:25 +1300258 Add support for the NXP I2C driver. This supports up to four bus
259 channels and operating on standard mode up to 100 kbits/s and fast
260 mode up to 400 kbits/s.
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100261
Tom Rini1a195882021-08-18 23:12:33 -0400262if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
Sriram Dash7122a0c2018-02-06 11:26:30 +0530263config SYS_I2C_MXC_I2C1
264 bool "NXP MXC I2C1"
265 help
266 Add support for NXP MXC I2C Controller 1.
267 Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
268
269config SYS_I2C_MXC_I2C2
270 bool "NXP MXC I2C2"
271 help
272 Add support for NXP MXC I2C Controller 2.
273 Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
274
275config SYS_I2C_MXC_I2C3
276 bool "NXP MXC I2C3"
277 help
278 Add support for NXP MXC I2C Controller 3.
279 Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
280
281config SYS_I2C_MXC_I2C4
282 bool "NXP MXC I2C4"
283 help
284 Add support for NXP MXC I2C Controller 4.
285 Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
Sriram Dasha64aa192018-02-06 11:26:31 +0530286
287config SYS_I2C_MXC_I2C5
288 bool "NXP MXC I2C5"
289 help
290 Add support for NXP MXC I2C Controller 5.
291 Required for SoCs which have I2C MXC controller 5 eg LX2160A
292
293config SYS_I2C_MXC_I2C6
294 bool "NXP MXC I2C6"
295 help
296 Add support for NXP MXC I2C Controller 6.
297 Required for SoCs which have I2C MXC controller 6 eg LX2160A
298
299config SYS_I2C_MXC_I2C7
300 bool "NXP MXC I2C7"
301 help
302 Add support for NXP MXC I2C Controller 7.
303 Required for SoCs which have I2C MXC controller 7 eg LX2160A
304
305config SYS_I2C_MXC_I2C8
306 bool "NXP MXC I2C8"
307 help
308 Add support for NXP MXC I2C Controller 8.
309 Required for SoCs which have I2C MXC controller 8 eg LX2160A
Sriram Dash7122a0c2018-02-06 11:26:30 +0530310endif
311
312if SYS_I2C_MXC_I2C1
313config SYS_MXC_I2C1_SPEED
314 int "I2C Channel 1 speed"
Tom Rini48425b12021-02-09 08:03:10 -0500315 default 40000000 if TARGET_LS2080A_EMU
Sriram Dash7122a0c2018-02-06 11:26:30 +0530316 default 100000
317 help
318 MXC I2C Channel 1 speed
319
320config SYS_MXC_I2C1_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400321 hex "I2C1 Slave"
Sriram Dash7122a0c2018-02-06 11:26:30 +0530322 default 0
323 help
324 MXC I2C1 Slave
325endif
326
327if SYS_I2C_MXC_I2C2
328config SYS_MXC_I2C2_SPEED
329 int "I2C Channel 2 speed"
Tom Rini48425b12021-02-09 08:03:10 -0500330 default 40000000 if TARGET_LS2080A_EMU
Sriram Dash7122a0c2018-02-06 11:26:30 +0530331 default 100000
332 help
333 MXC I2C Channel 2 speed
334
335config SYS_MXC_I2C2_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400336 hex "I2C2 Slave"
Sriram Dash7122a0c2018-02-06 11:26:30 +0530337 default 0
338 help
339 MXC I2C2 Slave
340endif
341
342if SYS_I2C_MXC_I2C3
343config SYS_MXC_I2C3_SPEED
344 int "I2C Channel 3 speed"
345 default 100000
346 help
347 MXC I2C Channel 3 speed
348
349config SYS_MXC_I2C3_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400350 hex "I2C3 Slave"
Sriram Dash7122a0c2018-02-06 11:26:30 +0530351 default 0
352 help
353 MXC I2C3 Slave
354endif
355
356if SYS_I2C_MXC_I2C4
357config SYS_MXC_I2C4_SPEED
358 int "I2C Channel 4 speed"
359 default 100000
360 help
361 MXC I2C Channel 4 speed
362
363config SYS_MXC_I2C4_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400364 hex "I2C4 Slave"
Sriram Dash7122a0c2018-02-06 11:26:30 +0530365 default 0
366 help
367 MXC I2C4 Slave
368endif
369
Sriram Dasha64aa192018-02-06 11:26:31 +0530370if SYS_I2C_MXC_I2C5
371config SYS_MXC_I2C5_SPEED
372 int "I2C Channel 5 speed"
373 default 100000
374 help
375 MXC I2C Channel 5 speed
376
377config SYS_MXC_I2C5_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400378 hex "I2C5 Slave"
Sriram Dasha64aa192018-02-06 11:26:31 +0530379 default 0
380 help
381 MXC I2C5 Slave
382endif
383
384if SYS_I2C_MXC_I2C6
385config SYS_MXC_I2C6_SPEED
386 int "I2C Channel 6 speed"
387 default 100000
388 help
389 MXC I2C Channel 6 speed
390
391config SYS_MXC_I2C6_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400392 hex "I2C6 Slave"
Sriram Dasha64aa192018-02-06 11:26:31 +0530393 default 0
394 help
395 MXC I2C6 Slave
396endif
397
398if SYS_I2C_MXC_I2C7
399config SYS_MXC_I2C7_SPEED
400 int "I2C Channel 7 speed"
401 default 100000
402 help
403 MXC I2C Channel 7 speed
404
405config SYS_MXC_I2C7_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400406 hex "I2C7 Slave"
Sriram Dasha64aa192018-02-06 11:26:31 +0530407 default 0
408 help
409 MXC I2C7 Slave
410endif
411
412if SYS_I2C_MXC_I2C8
413config SYS_MXC_I2C8_SPEED
414 int "I2C Channel 8 speed"
415 default 100000
416 help
417 MXC I2C Channel 8 speed
418
419config SYS_MXC_I2C8_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400420 hex "I2C8 Slave"
Sriram Dasha64aa192018-02-06 11:26:31 +0530421 default 0
422 help
423 MXC I2C8 Slave
424endif
425
Stefan Bosch9d85dfb2020-07-10 19:07:28 +0200426config SYS_I2C_NEXELL
427 bool "Nexell I2C driver"
428 depends on DM_I2C
429 help
430 Add support for the Nexell I2C driver. This is used with various
431 Nexell parts such as S5Pxx18 series SoCs. All chips
432 have several I2C ports and all are provided, controlled by the
433 device tree.
434
Pragnesh Patel1cfbd7a2020-11-14 14:42:34 +0530435config SYS_I2C_OCORES
436 bool "ocores I2C driver"
437 depends on DM_I2C
438 help
439 Add support for ocores I2C controller. For details see
440 https://opencores.org/projects/i2c
441
Adam Ford85901162017-08-07 13:11:34 -0500442config SYS_I2C_OMAP24XX
443 bool "TI OMAP2+ I2C driver"
Vignesh R64d4f552019-06-04 18:08:11 -0500444 depends on ARCH_OMAP2PLUS || ARCH_K3
Adam Ford85901162017-08-07 13:11:34 -0500445 help
446 Add support for the OMAP2+ I2C driver.
447
Marek Vasut27165962018-04-21 18:57:28 +0200448config SYS_I2C_RCAR_I2C
449 bool "Renesas RCar I2C driver"
450 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
451 help
452 Support for Renesas RCar I2C controller.
453
Marek Vasut125d8df2017-11-28 08:02:27 +0100454config SYS_I2C_RCAR_IIC
455 bool "Renesas RCar Gen3 IIC driver"
Marek Vasut4bc57a32018-02-17 02:17:40 +0100456 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
Marek Vasut125d8df2017-11-28 08:02:27 +0100457 help
458 Support for Renesas RCar Gen3 IIC controller.
459
Simon Glass3595f952015-08-30 16:55:39 -0600460config SYS_I2C_ROCKCHIP
461 bool "Rockchip I2C driver"
462 depends on DM_I2C
463 help
464 Add support for the Rockchip I2C driver. This is used with various
465 Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
Chris Packham94d0d3d2019-01-13 22:13:25 +1300466 have several I2C ports and all are provided, controlled by the
Simon Glass3595f952015-08-30 16:55:39 -0600467 device tree.
468
Simon Glass39bc3be2015-03-06 13:19:04 -0700469config SYS_I2C_SANDBOX
470 bool "Sandbox I2C driver"
471 depends on SANDBOX && DM_I2C
472 help
473 Enable I2C support for sandbox. This is an emulation of a real I2C
474 bus. Devices can be attached to the bus using the device tree
Masahiro Yamada8d8371d2017-02-11 12:39:55 +0900475 which specifies the driver to use. See sandbox.dts as an example.
Simon Glass39bc3be2015-03-06 13:19:04 -0700476
Tom Rinib9a254d2021-08-18 23:12:34 -0400477config SYS_I2C_SH
478 bool "Legacy SuperH I2C interface"
479 depends on ARCH_RMOBILE && SYS_I2C_LEGACY
480 help
481 Enable the legacy SuperH I2C interface.
482
483if SYS_I2C_SH
484config SYS_I2C_SH_NUM_CONTROLLERS
485 int
486 default 5
487
488config SYS_I2C_SH_BASE0
489 hex
490 default 0xE6820000
491
492config SYS_I2C_SH_BASE1
493 hex
494 default 0xE6822000
495
496config SYS_I2C_SH_BASE2
497 hex
498 default 0xE6824000
499
500config SYS_I2C_SH_BASE3
501 hex
502 default 0xE6826000
503
504config SYS_I2C_SH_BASE4
505 hex
506 default 0xE6828000
507
508config SH_I2C_8BIT
509 bool
510 default y
511
512config SH_I2C_DATA_HIGH
513 int
514 default 4
515
516config SH_I2C_DATA_LOW
517 int
518 default 5
519
520config SH_I2C_CLOCK
521 int
522 default 104000000
523endif
524
Tom Rini5817ff02021-08-17 17:59:46 -0400525config SYS_I2C_SOFT
526 bool "Legacy software I2C interface"
527 help
528 Enable the legacy software defined I2C interface
529
530config SYS_I2C_SOFT_SPEED
531 int "Software I2C bus speed"
532 depends on SYS_I2C_SOFT
533 default 100000
534 help
535 Speed of the software I2C bus
536
537config SYS_I2C_SOFT_SLAVE
538 hex "Software I2C slave address"
539 depends on SYS_I2C_SOFT
540 default 0xfe
541 help
542 Slave address of the software I2C bus
543
Suneel Garapatic6baea22020-05-26 14:13:07 +0200544config SYS_I2C_OCTEON
545 bool "Octeon II/III/TX/TX2 I2C driver"
546 depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
547 default y
548 help
549 Add support for the Marvell Octeon I2C driver. This is used with
550 various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
551 chips have several I2C ports and all are provided, controlled by
552 the device tree.
553
Jaehoon Chungf7e6a032017-01-09 14:47:52 +0900554config SYS_I2C_S3C24X0
555 bool "Samsung I2C driver"
Tom Rinifc917de2021-08-17 17:59:42 -0400556 depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C
Jaehoon Chungf7e6a032017-01-09 14:47:52 +0900557 help
558 Support for Samsung I2C controller as Samsung SoCs.
Simon Glass39bc3be2015-03-06 13:19:04 -0700559
Patrice Chotardebf442d2017-08-09 14:45:27 +0200560config SYS_I2C_STM32F7
561 bool "STMicroelectronics STM32F7 I2C support"
Patrick Delaunay85b53972018-03-12 10:46:10 +0100562 depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
Patrice Chotardebf442d2017-08-09 14:45:27 +0200563 help
564 Enable this option to add support for STM32 I2C controller
565 introduced with STM32F7/H7 SoCs. This I2C controller supports :
566 _ Slave and master modes
567 _ Multimaster capability
568 _ Standard-mode (up to 100 kHz)
569 _ Fast-mode (up to 400 kHz)
570 _ Fast-mode Plus (up to 1 MHz)
571 _ 7-bit and 10-bit addressing mode
572 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
573 _ All 7-bit addresses acknowledge mode
574 _ General call
575 _ Programmable setup and hold times
576 _ Easy to use event management
577 _ Optional clock stretching
578 _ Software reset
579
Jassi Brar23325cf2021-06-04 18:44:48 +0900580config SYS_I2C_SYNQUACER
581 bool "Socionext SynQuacer I2C controller"
582 depends on ARCH_SYNQUACER && DM_I2C
583 help
584 Support for Socionext Synquacer I2C controller. This I2C controller
585 will be used for RTC and LS-connector on DeveloperBox.
586
Peter Robinson12d37d82019-02-20 12:17:26 +0000587config SYS_I2C_TEGRA
588 bool "NVIDIA Tegra internal I2C controller"
Trevor Woerner513f6402020-05-06 08:02:41 -0400589 depends on ARCH_TEGRA
Peter Robinson12d37d82019-02-20 12:17:26 +0000590 help
591 Support for NVIDIA I2C controller available in Tegra SoCs.
592
Masahiro Yamada96a42ed2015-01-13 12:44:36 +0900593config SYS_I2C_UNIPHIER
594 bool "UniPhier I2C driver"
595 depends on ARCH_UNIPHIER && DM_I2C
596 default y
597 help
Masahiro Yamada563ee4c2015-05-29 17:30:01 +0900598 Support for UniPhier I2C controller driver. This I2C controller
599 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
Masahiro Yamada4e82e5e2015-01-13 12:44:37 +0900600
601config SYS_I2C_UNIPHIER_F
602 bool "UniPhier FIFO-builtin I2C driver"
603 depends on ARCH_UNIPHIER && DM_I2C
604 default y
605 help
Masahiro Yamada563ee4c2015-05-29 17:30:01 +0900606 Support for UniPhier FIFO-builtin I2C controller driver.
Masahiro Yamada4e82e5e2015-01-13 12:44:37 +0900607 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
Simon Glass2a80c402015-08-03 08:19:21 -0600608
Heiko Schochera37c1962018-10-11 07:26:33 +0200609config SYS_I2C_VERSATILE
610 bool "Arm Ltd Versatile I2C bus driver"
Tom Rini5af921e2021-02-20 20:05:47 -0500611 depends on DM_I2C && TARGET_VEXPRESS64_JUNO
Heiko Schochera37c1962018-10-11 07:26:33 +0200612 help
613 Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
614 controller is present in the development boards manufactured by Arm Ltd.
615
mario.six@gdsys.cc355a1272016-07-21 11:57:10 +0200616config SYS_I2C_MVTWSI
617 bool "Marvell I2C driver"
mario.six@gdsys.cc355a1272016-07-21 11:57:10 +0200618 help
619 Support for Marvell I2C controllers as used on the orion5x and
620 kirkwood SoC families.
621
Stephen Warren67a83482016-08-08 11:28:27 -0600622config TEGRA186_BPMP_I2C
623 bool "Enable Tegra186 BPMP-based I2C driver"
624 depends on TEGRA186_BPMP
625 help
626 Support for Tegra I2C controllers managed by the BPMP (Boot and
627 Power Management Processor). On Tegra186, some I2C controllers are
628 directly controlled by the main CPU, whereas others are controlled
629 by the BPMP, and can only be accessed by the main CPU via IPC
630 requests to the BPMP. This driver covers the latter case.
631
Tom Rinia6e29232021-08-18 23:12:32 -0400632config SYS_I2C_SLAVE
633 hex "I2C Slave address channel (all buses)"
634 depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
635 default 0xfe
636 help
637 I2C Slave address channel 0 for all buses in the legacy drivers.
638 Many boards/controllers/drivers don't support an I2C slave
639 interface so provide a default slave address for them for use in
640 common code. A real value for CONFIG_SYS_I2C_SLAVE should be
641 defined for any board which does support a slave interface and
642 this default used otherwise.
643
644config SYS_I2C_SPEED
645 int "I2C Slave channel 0 speed (all buses)"
646 depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
647 default 100000
648 help
649 I2C Slave speed channel 0 for all buses in the legacy drivers.
650
Adam Fordfa1dd3d2017-08-11 06:39:34 -0500651config SYS_I2C_BUS_MAX
652 int "Max I2C busses"
653 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
654 default 2 if TI816X
655 default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
656 default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
657 default 5 if OMAP54XX
658 help
659 Define the maximum number of available I2C buses.
660
Marek Vasut9de0e2a2018-12-19 12:26:27 +0100661config SYS_I2C_XILINX_XIIC
662 bool "Xilinx AXI I2C driver"
663 depends on DM_I2C
664 help
665 Support for Xilinx AXI I2C controller.
666
Mario Six3bb409c2018-01-15 11:08:11 +0100667config SYS_I2C_IHS
668 bool "gdsys IHS I2C driver"
669 depends on DM_I2C
670 help
671 Support for gdsys IHS I2C driver on FPGA bus.
672
Simon Glass2a80c402015-08-03 08:19:21 -0600673source "drivers/i2c/muxes/Kconfig"
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900674
Simon Glass8e85e3c2021-07-10 21:14:35 -0600675endif