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Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# I2C subsystem configuration
3#
4
5menu "I2C support"
6
Masahiro Yamadacd5cf8e2015-01-13 12:44:35 +09007config DM_I2C
8 bool "Enable Driver Model for I2C drivers"
9 depends on DM
10 help
Przemyslaw Marczake5fa1212015-03-31 18:57:17 +020011 Enable driver model for I2C. The I2C uclass interface: probe, read,
12 write and speed, is implemented with the bus drivers operations,
13 which provide methods for bus setting and data transfer. Each chip
14 device (bus child) info is kept as parent platdata. The interface
15 is defined in include/i2c.h. When i2c bus driver supports the i2c
16 uclass, but the device drivers not, then DM_I2C_COMPAT config can
17 be used as compatibility layer.
Masahiro Yamada96a42ed2015-01-13 12:44:36 +090018
Simon Glasse200ee22015-02-13 12:20:48 -070019config DM_I2C_COMPAT
20 bool "Enable I2C compatibility layer"
21 depends on DM
22 help
23 Enable old-style I2C functions for compatibility with existing code.
24 This option can be enabled as a temporary measure to avoid needing
25 to convert all code for a board in a single commit. It should not
26 be enabled for any board in an official release.
27
Simon Glass9ad07af2015-08-03 08:19:23 -060028config I2C_CROS_EC_TUNNEL
29 tristate "Chrome OS EC tunnel I2C bus"
30 depends on CROS_EC
31 help
32 This provides an I2C bus that will tunnel i2c commands through to
33 the other side of the Chrome OS EC to the I2C bus connected there.
34 This will work whatever the interface used to talk to the EC (SPI,
35 I2C or LPC). Some Chromebooks use this when the hardware design
36 does not allow direct access to the main PMIC from the AP.
37
Simon Glasseb2cc512015-08-03 08:19:24 -060038config I2C_CROS_EC_LDO
39 bool "Provide access to LDOs on the Chrome OS EC"
40 depends on CROS_EC
41 ---help---
42 On many Chromebooks the main PMIC is inaccessible to the AP. This is
43 often dealt with by using an I2C pass-through interface provided by
44 the EC. On some unfortunate models (e.g. Spring) the pass-through
45 is not available, and an LDO message is available instead. This
46 option enables a driver which provides very basic access to those
47 regulators, via the EC. We implement this as an I2C bus which
48 emulates just the TPS65090 messages we know about. This is done to
49 avoid duplicating the logic in the TPS65090 regulator driver for
50 enabling/disabling an LDO.
Simon Glass9ad07af2015-08-03 08:19:23 -060051
Lukasz Majewski0a556272017-03-21 12:08:25 +010052config I2C_SET_DEFAULT_BUS_NUM
53 bool "Set default I2C bus number"
54 depends on DM_I2C
55 help
56 Set default number of I2C bus to be accessed. This option provides
57 behaviour similar to old (i.e. pre DM) I2C bus driver.
58
59config I2C_DEFAULT_BUS_NUMBER
60 hex "I2C default bus number"
61 depends on I2C_SET_DEFAULT_BUS_NUM
62 default 0x0
63 help
64 Number of default I2C bus to use
65
Przemyslaw Marczakd3aa7e12015-03-31 18:57:18 +020066config DM_I2C_GPIO
67 bool "Enable Driver Model for software emulated I2C bus driver"
68 depends on DM_I2C && DM_GPIO
69 help
70 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
71 configuration is given by the device tree. Kernel-style device tree
72 bindings are supported.
73 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
74
Songjun Wu26d88282016-06-20 13:22:38 +080075config SYS_I2C_AT91
76 bool "Atmel I2C driver"
77 depends on DM_I2C && ARCH_AT91
78 help
79 Add support for the Atmel I2C driver. A serious problem is that there
80 is no documented way to issue repeated START conditions for more than
81 two messages, as needed to support combined I2C messages. Use the
82 i2c-gpio driver unless your system can cope with this limitation.
83 Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
84
mario.six@gdsys.cc349686c2016-04-25 08:31:09 +020085config SYS_I2C_FSL
86 bool "Freescale I2C bus driver"
87 depends on DM_I2C
88 help
89 Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
90 MPC85xx processors.
91
Moritz Fischer0075dac2015-12-28 09:47:11 -080092config SYS_I2C_CADENCE
93 tristate "Cadence I2C Controller"
94 depends on DM_I2C && (ARCH_ZYNQ || ARM64)
95 help
96 Say yes here to select Cadence I2C Host Controller. This controller is
97 e.g. used by Xilinx Zynq.
98
Stefan Roeseb71955f2016-04-28 09:47:17 +020099config SYS_I2C_DW
100 bool "Designware I2C Controller"
101 default n
102 help
103 Say yes here to select the Designware I2C Host Controller. This
104 controller is used in various SoCs, e.g. the ST SPEAr, Altera
105 SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
106
Stefan Roese38fe7dc2016-04-28 09:47:19 +0200107config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED
108 bool "DW I2C Enable Status Register not supported"
109 depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \
110 TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600)
111 default y
112 help
113 Some versions of the Designware I2C controller do not support the
114 enable status register. This config option can be enabled in such
115 cases.
116
maxims@google.com7f613312017-04-17 12:00:30 -0700117config SYS_I2C_ASPEED
118 bool "Aspeed I2C Controller"
119 depends on DM_I2C && ARCH_ASPEED
120 help
121 Say yes here to select Aspeed I2C Host Controller. The driver
122 supports AST2500 and AST2400 controllers, but is very limited.
123 Only single master mode is supported and only byte-by-byte
124 synchronous reads and writes are supported, no Pool Buffers or DMA.
125
Simon Glass5e66fdc2016-01-17 16:11:44 -0700126config SYS_I2C_INTEL
127 bool "Intel I2C/SMBUS driver"
128 depends on DM_I2C
129 help
130 Add support for the Intel SMBUS driver. So far this driver is just
131 a stub which perhaps some basic init. There is no implementation of
132 the I2C API meaning that any I2C operations will immediately fail
133 for now.
134
Peng Fand684adb2017-02-24 09:54:18 +0800135config SYS_I2C_IMX_LPI2C
136 bool "NXP i.MX LPI2C driver"
Peng Fand684adb2017-02-24 09:54:18 +0800137 help
138 Add support for the NXP i.MX LPI2C driver.
139
Beniamino Galvanid5b199c2017-10-29 10:09:00 +0100140config SYS_I2C_MESON
141 bool "Amlogic Meson I2C driver"
142 depends on DM_I2C && ARCH_MESON
143 help
144 Add support for the Amlogic Meson I2C driver.
145
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100146config SYS_I2C_MXC
147 bool "NXP i.MX I2C driver"
148 depends on MX6
149 help
150 Add support for the NXP i.MX I2C driver. This supports upto for bus
151 channels and operating on standard mode upto 100 kbits/s and fast
152 mode upto 400 kbits/s.
153
Adam Ford85901162017-08-07 13:11:34 -0500154config SYS_I2C_OMAP24XX
155 bool "TI OMAP2+ I2C driver"
156 depends on ARCH_OMAP2PLUS
157 help
158 Add support for the OMAP2+ I2C driver.
159
Marek Vasut125d8df2017-11-28 08:02:27 +0100160config SYS_I2C_RCAR_IIC
161 bool "Renesas RCar Gen3 IIC driver"
162 depends on RCAR_GEN3 && DM_I2C
163 help
164 Support for Renesas RCar Gen3 IIC controller.
165
Simon Glass3595f952015-08-30 16:55:39 -0600166config SYS_I2C_ROCKCHIP
167 bool "Rockchip I2C driver"
168 depends on DM_I2C
169 help
170 Add support for the Rockchip I2C driver. This is used with various
171 Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
172 have several I2C ports and all are provided, controled by the
173 device tree.
174
Simon Glass39bc3be2015-03-06 13:19:04 -0700175config SYS_I2C_SANDBOX
176 bool "Sandbox I2C driver"
177 depends on SANDBOX && DM_I2C
178 help
179 Enable I2C support for sandbox. This is an emulation of a real I2C
180 bus. Devices can be attached to the bus using the device tree
Masahiro Yamada8d8371d2017-02-11 12:39:55 +0900181 which specifies the driver to use. See sandbox.dts as an example.
Simon Glass39bc3be2015-03-06 13:19:04 -0700182
Jaehoon Chungf7e6a032017-01-09 14:47:52 +0900183config SYS_I2C_S3C24X0
184 bool "Samsung I2C driver"
185 depends on ARCH_EXYNOS4 && DM_I2C
186 help
187 Support for Samsung I2C controller as Samsung SoCs.
Simon Glass39bc3be2015-03-06 13:19:04 -0700188
Patrice Chotardebf442d2017-08-09 14:45:27 +0200189config SYS_I2C_STM32F7
190 bool "STMicroelectronics STM32F7 I2C support"
191 depends on (STM32F7 || STM32H7) && DM_I2C
192 help
193 Enable this option to add support for STM32 I2C controller
194 introduced with STM32F7/H7 SoCs. This I2C controller supports :
195 _ Slave and master modes
196 _ Multimaster capability
197 _ Standard-mode (up to 100 kHz)
198 _ Fast-mode (up to 400 kHz)
199 _ Fast-mode Plus (up to 1 MHz)
200 _ 7-bit and 10-bit addressing mode
201 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
202 _ All 7-bit addresses acknowledge mode
203 _ General call
204 _ Programmable setup and hold times
205 _ Easy to use event management
206 _ Optional clock stretching
207 _ Software reset
208
Masahiro Yamada96a42ed2015-01-13 12:44:36 +0900209config SYS_I2C_UNIPHIER
210 bool "UniPhier I2C driver"
211 depends on ARCH_UNIPHIER && DM_I2C
212 default y
213 help
Masahiro Yamada563ee4c2015-05-29 17:30:01 +0900214 Support for UniPhier I2C controller driver. This I2C controller
215 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
Masahiro Yamada4e82e5e2015-01-13 12:44:37 +0900216
217config SYS_I2C_UNIPHIER_F
218 bool "UniPhier FIFO-builtin I2C driver"
219 depends on ARCH_UNIPHIER && DM_I2C
220 default y
221 help
Masahiro Yamada563ee4c2015-05-29 17:30:01 +0900222 Support for UniPhier FIFO-builtin I2C controller driver.
Masahiro Yamada4e82e5e2015-01-13 12:44:37 +0900223 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
Simon Glass2a80c402015-08-03 08:19:21 -0600224
mario.six@gdsys.cc355a1272016-07-21 11:57:10 +0200225config SYS_I2C_MVTWSI
226 bool "Marvell I2C driver"
227 depends on DM_I2C
228 help
229 Support for Marvell I2C controllers as used on the orion5x and
230 kirkwood SoC families.
231
Stephen Warren67a83482016-08-08 11:28:27 -0600232config TEGRA186_BPMP_I2C
233 bool "Enable Tegra186 BPMP-based I2C driver"
234 depends on TEGRA186_BPMP
235 help
236 Support for Tegra I2C controllers managed by the BPMP (Boot and
237 Power Management Processor). On Tegra186, some I2C controllers are
238 directly controlled by the main CPU, whereas others are controlled
239 by the BPMP, and can only be accessed by the main CPU via IPC
240 requests to the BPMP. This driver covers the latter case.
241
Adam Fordfa1dd3d2017-08-11 06:39:34 -0500242config SYS_I2C_BUS_MAX
243 int "Max I2C busses"
244 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
245 default 2 if TI816X
246 default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
247 default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
248 default 5 if OMAP54XX
249 help
250 Define the maximum number of available I2C buses.
251
Simon Glass2a80c402015-08-03 08:19:21 -0600252source "drivers/i2c/muxes/Kconfig"
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900253
254endmenu