Masahiro Yamada | cc85b7b | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 1 | # |
| 2 | # I2C subsystem configuration |
| 3 | # |
| 4 | |
| 5 | menu "I2C support" |
| 6 | |
Masahiro Yamada | cd5cf8e | 2015-01-13 12:44:35 +0900 | [diff] [blame] | 7 | config DM_I2C |
| 8 | bool "Enable Driver Model for I2C drivers" |
| 9 | depends on DM |
| 10 | help |
Przemyslaw Marczak | e5fa121 | 2015-03-31 18:57:17 +0200 | [diff] [blame] | 11 | Enable driver model for I2C. The I2C uclass interface: probe, read, |
| 12 | write and speed, is implemented with the bus drivers operations, |
| 13 | which provide methods for bus setting and data transfer. Each chip |
| 14 | device (bus child) info is kept as parent platdata. The interface |
| 15 | is defined in include/i2c.h. When i2c bus driver supports the i2c |
| 16 | uclass, but the device drivers not, then DM_I2C_COMPAT config can |
| 17 | be used as compatibility layer. |
Masahiro Yamada | 96a42ed | 2015-01-13 12:44:36 +0900 | [diff] [blame] | 18 | |
Simon Glass | e200ee2 | 2015-02-13 12:20:48 -0700 | [diff] [blame] | 19 | config DM_I2C_COMPAT |
| 20 | bool "Enable I2C compatibility layer" |
| 21 | depends on DM |
| 22 | help |
| 23 | Enable old-style I2C functions for compatibility with existing code. |
| 24 | This option can be enabled as a temporary measure to avoid needing |
| 25 | to convert all code for a board in a single commit. It should not |
| 26 | be enabled for any board in an official release. |
| 27 | |
Simon Glass | 9ad07af | 2015-08-03 08:19:23 -0600 | [diff] [blame] | 28 | config I2C_CROS_EC_TUNNEL |
| 29 | tristate "Chrome OS EC tunnel I2C bus" |
| 30 | depends on CROS_EC |
| 31 | help |
| 32 | This provides an I2C bus that will tunnel i2c commands through to |
| 33 | the other side of the Chrome OS EC to the I2C bus connected there. |
| 34 | This will work whatever the interface used to talk to the EC (SPI, |
| 35 | I2C or LPC). Some Chromebooks use this when the hardware design |
| 36 | does not allow direct access to the main PMIC from the AP. |
| 37 | |
Simon Glass | eb2cc51 | 2015-08-03 08:19:24 -0600 | [diff] [blame] | 38 | config I2C_CROS_EC_LDO |
| 39 | bool "Provide access to LDOs on the Chrome OS EC" |
| 40 | depends on CROS_EC |
| 41 | ---help--- |
| 42 | On many Chromebooks the main PMIC is inaccessible to the AP. This is |
| 43 | often dealt with by using an I2C pass-through interface provided by |
| 44 | the EC. On some unfortunate models (e.g. Spring) the pass-through |
| 45 | is not available, and an LDO message is available instead. This |
| 46 | option enables a driver which provides very basic access to those |
| 47 | regulators, via the EC. We implement this as an I2C bus which |
| 48 | emulates just the TPS65090 messages we know about. This is done to |
| 49 | avoid duplicating the logic in the TPS65090 regulator driver for |
| 50 | enabling/disabling an LDO. |
Simon Glass | 9ad07af | 2015-08-03 08:19:23 -0600 | [diff] [blame] | 51 | |
Przemyslaw Marczak | d3aa7e1 | 2015-03-31 18:57:18 +0200 | [diff] [blame] | 52 | config DM_I2C_GPIO |
| 53 | bool "Enable Driver Model for software emulated I2C bus driver" |
| 54 | depends on DM_I2C && DM_GPIO |
| 55 | help |
| 56 | Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO |
| 57 | configuration is given by the device tree. Kernel-style device tree |
| 58 | bindings are supported. |
| 59 | Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt |
| 60 | |
mario.six@gdsys.cc | 349686c | 2016-04-25 08:31:09 +0200 | [diff] [blame] | 61 | config SYS_I2C_FSL |
| 62 | bool "Freescale I2C bus driver" |
| 63 | depends on DM_I2C |
| 64 | help |
| 65 | Add support for Freescale I2C busses as used on MPC8240, MPC8245, and |
| 66 | MPC85xx processors. |
| 67 | |
Moritz Fischer | 0075dac | 2015-12-28 09:47:11 -0800 | [diff] [blame] | 68 | config SYS_I2C_CADENCE |
| 69 | tristate "Cadence I2C Controller" |
| 70 | depends on DM_I2C && (ARCH_ZYNQ || ARM64) |
| 71 | help |
| 72 | Say yes here to select Cadence I2C Host Controller. This controller is |
| 73 | e.g. used by Xilinx Zynq. |
| 74 | |
Stefan Roese | b71955f | 2016-04-28 09:47:17 +0200 | [diff] [blame] | 75 | config SYS_I2C_DW |
| 76 | bool "Designware I2C Controller" |
| 77 | default n |
| 78 | help |
| 79 | Say yes here to select the Designware I2C Host Controller. This |
| 80 | controller is used in various SoCs, e.g. the ST SPEAr, Altera |
| 81 | SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs. |
| 82 | |
Stefan Roese | 38fe7dc | 2016-04-28 09:47:19 +0200 | [diff] [blame^] | 83 | config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED |
| 84 | bool "DW I2C Enable Status Register not supported" |
| 85 | depends on SYS_I2C_DW && (TARGET_SPEAR300 || TARGET_SPEAR310 || \ |
| 86 | TARGET_SPEAR320 || TARGET_SPEAR600 || TARGET_X600) |
| 87 | default y |
| 88 | help |
| 89 | Some versions of the Designware I2C controller do not support the |
| 90 | enable status register. This config option can be enabled in such |
| 91 | cases. |
| 92 | |
Simon Glass | 5e66fdc | 2016-01-17 16:11:44 -0700 | [diff] [blame] | 93 | config SYS_I2C_INTEL |
| 94 | bool "Intel I2C/SMBUS driver" |
| 95 | depends on DM_I2C |
| 96 | help |
| 97 | Add support for the Intel SMBUS driver. So far this driver is just |
| 98 | a stub which perhaps some basic init. There is no implementation of |
| 99 | the I2C API meaning that any I2C operations will immediately fail |
| 100 | for now. |
| 101 | |
Simon Glass | 3595f95 | 2015-08-30 16:55:39 -0600 | [diff] [blame] | 102 | config SYS_I2C_ROCKCHIP |
| 103 | bool "Rockchip I2C driver" |
| 104 | depends on DM_I2C |
| 105 | help |
| 106 | Add support for the Rockchip I2C driver. This is used with various |
| 107 | Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips |
| 108 | have several I2C ports and all are provided, controled by the |
| 109 | device tree. |
| 110 | |
Simon Glass | 39bc3be | 2015-03-06 13:19:04 -0700 | [diff] [blame] | 111 | config SYS_I2C_SANDBOX |
| 112 | bool "Sandbox I2C driver" |
| 113 | depends on SANDBOX && DM_I2C |
| 114 | help |
| 115 | Enable I2C support for sandbox. This is an emulation of a real I2C |
| 116 | bus. Devices can be attached to the bus using the device tree |
| 117 | which specifies the driver to use. As an example, see this device |
| 118 | tree fragment from sandbox.dts. It shows that the I2C bus has a |
| 119 | single EEPROM at address 0x2c (7-bit address) which is emulated by |
| 120 | the driver for "sandbox,i2c-eeprom", which is in |
| 121 | drivers/misc/i2c_eeprom_emul.c. |
| 122 | |
| 123 | i2c@0 { |
| 124 | #address-cells = <1>; |
| 125 | #size-cells = <0>; |
| 126 | reg = <0>; |
| 127 | compatible = "sandbox,i2c"; |
| 128 | clock-frequency = <400000>; |
| 129 | eeprom@2c { |
| 130 | reg = <0x2c>; |
| 131 | compatible = "i2c-eeprom"; |
| 132 | emul { |
| 133 | compatible = "sandbox,i2c-eeprom"; |
| 134 | sandbox,filename = "i2c.bin"; |
| 135 | sandbox,size = <128>; |
| 136 | }; |
| 137 | }; |
| 138 | }; |
| 139 | |
| 140 | |
Masahiro Yamada | 96a42ed | 2015-01-13 12:44:36 +0900 | [diff] [blame] | 141 | config SYS_I2C_UNIPHIER |
| 142 | bool "UniPhier I2C driver" |
| 143 | depends on ARCH_UNIPHIER && DM_I2C |
| 144 | default y |
| 145 | help |
Masahiro Yamada | 563ee4c | 2015-05-29 17:30:01 +0900 | [diff] [blame] | 146 | Support for UniPhier I2C controller driver. This I2C controller |
| 147 | is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs. |
Masahiro Yamada | 4e82e5e | 2015-01-13 12:44:37 +0900 | [diff] [blame] | 148 | |
| 149 | config SYS_I2C_UNIPHIER_F |
| 150 | bool "UniPhier FIFO-builtin I2C driver" |
| 151 | depends on ARCH_UNIPHIER && DM_I2C |
| 152 | default y |
| 153 | help |
Masahiro Yamada | 563ee4c | 2015-05-29 17:30:01 +0900 | [diff] [blame] | 154 | Support for UniPhier FIFO-builtin I2C controller driver. |
Masahiro Yamada | 4e82e5e | 2015-01-13 12:44:37 +0900 | [diff] [blame] | 155 | This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs. |
Simon Glass | 2a80c40 | 2015-08-03 08:19:21 -0600 | [diff] [blame] | 156 | |
| 157 | source "drivers/i2c/muxes/Kconfig" |
Masahiro Yamada | cc85b7b | 2015-07-26 02:46:26 +0900 | [diff] [blame] | 158 | |
| 159 | endmenu |