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Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# I2C subsystem configuration
3#
4
5menu "I2C support"
6
Masahiro Yamadacd5cf8e2015-01-13 12:44:35 +09007config DM_I2C
8 bool "Enable Driver Model for I2C drivers"
9 depends on DM
10 help
Przemyslaw Marczake5fa1212015-03-31 18:57:17 +020011 Enable driver model for I2C. The I2C uclass interface: probe, read,
12 write and speed, is implemented with the bus drivers operations,
13 which provide methods for bus setting and data transfer. Each chip
14 device (bus child) info is kept as parent platdata. The interface
15 is defined in include/i2c.h. When i2c bus driver supports the i2c
16 uclass, but the device drivers not, then DM_I2C_COMPAT config can
17 be used as compatibility layer.
Masahiro Yamada96a42ed2015-01-13 12:44:36 +090018
Simon Glasse200ee22015-02-13 12:20:48 -070019config DM_I2C_COMPAT
20 bool "Enable I2C compatibility layer"
21 depends on DM
22 help
23 Enable old-style I2C functions for compatibility with existing code.
24 This option can be enabled as a temporary measure to avoid needing
25 to convert all code for a board in a single commit. It should not
26 be enabled for any board in an official release.
27
Simon Glass9ad07af2015-08-03 08:19:23 -060028config I2C_CROS_EC_TUNNEL
29 tristate "Chrome OS EC tunnel I2C bus"
30 depends on CROS_EC
31 help
32 This provides an I2C bus that will tunnel i2c commands through to
33 the other side of the Chrome OS EC to the I2C bus connected there.
34 This will work whatever the interface used to talk to the EC (SPI,
35 I2C or LPC). Some Chromebooks use this when the hardware design
36 does not allow direct access to the main PMIC from the AP.
37
Simon Glasseb2cc512015-08-03 08:19:24 -060038config I2C_CROS_EC_LDO
39 bool "Provide access to LDOs on the Chrome OS EC"
40 depends on CROS_EC
41 ---help---
42 On many Chromebooks the main PMIC is inaccessible to the AP. This is
43 often dealt with by using an I2C pass-through interface provided by
44 the EC. On some unfortunate models (e.g. Spring) the pass-through
45 is not available, and an LDO message is available instead. This
46 option enables a driver which provides very basic access to those
47 regulators, via the EC. We implement this as an I2C bus which
48 emulates just the TPS65090 messages we know about. This is done to
49 avoid duplicating the logic in the TPS65090 regulator driver for
50 enabling/disabling an LDO.
Simon Glass9ad07af2015-08-03 08:19:23 -060051
Przemyslaw Marczakd3aa7e12015-03-31 18:57:18 +020052config DM_I2C_GPIO
53 bool "Enable Driver Model for software emulated I2C bus driver"
54 depends on DM_I2C && DM_GPIO
55 help
56 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
57 configuration is given by the device tree. Kernel-style device tree
58 bindings are supported.
59 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
60
Moritz Fischer0075dac2015-12-28 09:47:11 -080061config SYS_I2C_CADENCE
62 tristate "Cadence I2C Controller"
63 depends on DM_I2C && (ARCH_ZYNQ || ARM64)
64 help
65 Say yes here to select Cadence I2C Host Controller. This controller is
66 e.g. used by Xilinx Zynq.
67
Simon Glass5e66fdc2016-01-17 16:11:44 -070068config SYS_I2C_INTEL
69 bool "Intel I2C/SMBUS driver"
70 depends on DM_I2C
71 help
72 Add support for the Intel SMBUS driver. So far this driver is just
73 a stub which perhaps some basic init. There is no implementation of
74 the I2C API meaning that any I2C operations will immediately fail
75 for now.
76
Simon Glass3595f952015-08-30 16:55:39 -060077config SYS_I2C_ROCKCHIP
78 bool "Rockchip I2C driver"
79 depends on DM_I2C
80 help
81 Add support for the Rockchip I2C driver. This is used with various
82 Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
83 have several I2C ports and all are provided, controled by the
84 device tree.
85
Simon Glass39bc3be2015-03-06 13:19:04 -070086config SYS_I2C_SANDBOX
87 bool "Sandbox I2C driver"
88 depends on SANDBOX && DM_I2C
89 help
90 Enable I2C support for sandbox. This is an emulation of a real I2C
91 bus. Devices can be attached to the bus using the device tree
92 which specifies the driver to use. As an example, see this device
93 tree fragment from sandbox.dts. It shows that the I2C bus has a
94 single EEPROM at address 0x2c (7-bit address) which is emulated by
95 the driver for "sandbox,i2c-eeprom", which is in
96 drivers/misc/i2c_eeprom_emul.c.
97
98 i2c@0 {
99 #address-cells = <1>;
100 #size-cells = <0>;
101 reg = <0>;
102 compatible = "sandbox,i2c";
103 clock-frequency = <400000>;
104 eeprom@2c {
105 reg = <0x2c>;
106 compatible = "i2c-eeprom";
107 emul {
108 compatible = "sandbox,i2c-eeprom";
109 sandbox,filename = "i2c.bin";
110 sandbox,size = <128>;
111 };
112 };
113 };
114
115
Masahiro Yamada96a42ed2015-01-13 12:44:36 +0900116config SYS_I2C_UNIPHIER
117 bool "UniPhier I2C driver"
118 depends on ARCH_UNIPHIER && DM_I2C
119 default y
120 help
Masahiro Yamada563ee4c2015-05-29 17:30:01 +0900121 Support for UniPhier I2C controller driver. This I2C controller
122 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
Masahiro Yamada4e82e5e2015-01-13 12:44:37 +0900123
124config SYS_I2C_UNIPHIER_F
125 bool "UniPhier FIFO-builtin I2C driver"
126 depends on ARCH_UNIPHIER && DM_I2C
127 default y
128 help
Masahiro Yamada563ee4c2015-05-29 17:30:01 +0900129 Support for UniPhier FIFO-builtin I2C controller driver.
Masahiro Yamada4e82e5e2015-01-13 12:44:37 +0900130 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
Simon Glass2a80c402015-08-03 08:19:21 -0600131
132source "drivers/i2c/muxes/Kconfig"
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900133
134endmenu