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Masahiro Yamadacc85b7b2015-07-26 02:46:26 +09001#
2# I2C subsystem configuration
3#
4
Simon Glass8e85e3c2021-07-10 21:14:35 -06005menuconfig I2C
6 bool "I2C support"
7 default y
8 help
9 Note:
10 This is a stand-in for an option to enable I2C support. In fact this
11 simply enables building of the I2C directory for U-Boot. The actual
12 I2C feature is enabled by DM_I2C (for driver model) and
13 the #define CONFIG_SYS_I2C_LEGACY (for the legacy I2C stack).
14
15 So at present there is no need to ever disable this option.
16
17 Eventually it will:
18
19 Enable support for the I2C (Inter-Integrated Circuit) bus in U-Boot.
20 I2C works with a clock and data line which can be driven by a
21 one or more masters or slaves. It is a fairly complex bus but is
22 widely used as it only needs two lines for communication. Speeds of
23 400kbps are typical but up to 3.4Mbps is supported by some
24 hardware. Enable this option to build the drivers in drivers/i2c as
25 part of a U-Boot build.
26
27if I2C
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +090028
Masahiro Yamadacd5cf8e2015-01-13 12:44:35 +090029config DM_I2C
30 bool "Enable Driver Model for I2C drivers"
31 depends on DM
32 help
Przemyslaw Marczake5fa1212015-03-31 18:57:17 +020033 Enable driver model for I2C. The I2C uclass interface: probe, read,
34 write and speed, is implemented with the bus drivers operations,
35 which provide methods for bus setting and data transfer. Each chip
Simon Glass71fa5b42020-12-03 16:55:18 -070036 device (bus child) info is kept as parent plat. The interface
Bartosz Golaszewski1e4450c2019-07-29 08:58:00 +020037 is defined in include/i2c.h.
Simon Glasse200ee22015-02-13 12:20:48 -070038
Igor Opaniuk964f2322021-02-09 13:52:43 +020039config SPL_DM_I2C
40 bool "Enable Driver Model for I2C drivers in SPL"
41 depends on SPL_DM && DM_I2C
42 default y
43 help
44 Enable driver model for I2C. The I2C uclass interface: probe, read,
45 write and speed, is implemented with the bus drivers operations,
46 which provide methods for bus setting and data transfer. Each chip
47 device (bus child) info is kept as parent platdata. The interface
48 is defined in include/i2c.h.
49
Tom Rini52b2e262021-08-18 23:12:24 -040050config SYS_I2C_LEGACY
51 bool "Enable legacy I2C subsystem and drivers"
52 depends on !DM_I2C
53 help
54 Enable the legacy I2C subsystem and drivers. While this is
55 deprecated in U-Boot itself, this can be useful in some situations
56 in SPL or TPL.
57
58config SPL_SYS_I2C_LEGACY
59 bool "Enable legacy I2C subsystem and drivers in SPL"
60 depends on SUPPORT_SPL && !SPL_DM_I2C
61 help
62 Enable the legacy I2C subsystem and drivers in SPL. This is useful
63 in some size constrained situations.
64
65config TPL_SYS_I2C_LEGACY
66 bool "Enable legacy I2C subsystem and drivers in TPL"
67 depends on SUPPORT_TPL && !SPL_DM_I2C
68 help
69 Enable the legacy I2C subsystem and drivers in TPL. This is useful
70 in some size constrained situations.
71
Tom Rini714482a2021-08-18 23:12:25 -040072config SYS_I2C_EARLY_INIT
73 bool "Enable legacy I2C subsystem early in boot"
74 depends on BOARD_EARLY_INIT_F && SPL_SYS_I2C_LEGACY && SYS_I2C_MXC
75 help
76 Add the function prototype for i2c_early_init_f which is called in
77 board_early_init_f.
78
Simon Glass9ad07af2015-08-03 08:19:23 -060079config I2C_CROS_EC_TUNNEL
80 tristate "Chrome OS EC tunnel I2C bus"
81 depends on CROS_EC
82 help
83 This provides an I2C bus that will tunnel i2c commands through to
84 the other side of the Chrome OS EC to the I2C bus connected there.
85 This will work whatever the interface used to talk to the EC (SPI,
86 I2C or LPC). Some Chromebooks use this when the hardware design
87 does not allow direct access to the main PMIC from the AP.
88
Simon Glasseb2cc512015-08-03 08:19:24 -060089config I2C_CROS_EC_LDO
90 bool "Provide access to LDOs on the Chrome OS EC"
91 depends on CROS_EC
92 ---help---
93 On many Chromebooks the main PMIC is inaccessible to the AP. This is
94 often dealt with by using an I2C pass-through interface provided by
95 the EC. On some unfortunate models (e.g. Spring) the pass-through
96 is not available, and an LDO message is available instead. This
97 option enables a driver which provides very basic access to those
98 regulators, via the EC. We implement this as an I2C bus which
99 emulates just the TPS65090 messages we know about. This is done to
100 avoid duplicating the logic in the TPS65090 regulator driver for
101 enabling/disabling an LDO.
Simon Glass9ad07af2015-08-03 08:19:23 -0600102
Lukasz Majewski0a556272017-03-21 12:08:25 +0100103config I2C_SET_DEFAULT_BUS_NUM
104 bool "Set default I2C bus number"
105 depends on DM_I2C
106 help
107 Set default number of I2C bus to be accessed. This option provides
108 behaviour similar to old (i.e. pre DM) I2C bus driver.
109
110config I2C_DEFAULT_BUS_NUMBER
111 hex "I2C default bus number"
112 depends on I2C_SET_DEFAULT_BUS_NUM
113 default 0x0
114 help
115 Number of default I2C bus to use
116
Przemyslaw Marczakd3aa7e12015-03-31 18:57:18 +0200117config DM_I2C_GPIO
118 bool "Enable Driver Model for software emulated I2C bus driver"
119 depends on DM_I2C && DM_GPIO
120 help
121 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
122 configuration is given by the device tree. Kernel-style device tree
123 bindings are supported.
124 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
125
Igor Opaniuk964f2322021-02-09 13:52:43 +0200126config SPL_DM_I2C_GPIO
127 bool "Enable Driver Model for software emulated I2C bus driver in SPL"
Simon Glass035939e2021-07-10 21:14:30 -0600128 depends on SPL_DM && DM_I2C_GPIO && SPL_DM_GPIO && SPL_GPIO
Igor Opaniuk964f2322021-02-09 13:52:43 +0200129 default y
130 help
131 Enable the i2c bus driver emulation by using the GPIOs. The bus GPIO
132 configuration is given by the device tree. Kernel-style device tree
133 bindings are supported.
134 Binding info: doc/device-tree-bindings/i2c/i2c-gpio.txt
135
Songjun Wu26d88282016-06-20 13:22:38 +0800136config SYS_I2C_AT91
137 bool "Atmel I2C driver"
138 depends on DM_I2C && ARCH_AT91
139 help
140 Add support for the Atmel I2C driver. A serious problem is that there
141 is no documented way to issue repeated START conditions for more than
142 two messages, as needed to support combined I2C messages. Use the
143 i2c-gpio driver unless your system can cope with this limitation.
144 Binding info: doc/device-tree-bindings/i2c/i2c-at91.txt
145
Rayagonda Kokatanurd5dc36f2020-04-08 11:12:27 +0530146config SYS_I2C_IPROC
147 bool "Broadcom I2C driver"
148 depends on DM_I2C
149 help
150 Broadcom I2C driver.
151 Add support for Broadcom I2C driver.
152 Say yes here to to enable the Broadco I2C driver.
153
mario.six@gdsys.cc349686c2016-04-25 08:31:09 +0200154config SYS_I2C_FSL
155 bool "Freescale I2C bus driver"
156 depends on DM_I2C
157 help
158 Add support for Freescale I2C busses as used on MPC8240, MPC8245, and
159 MPC85xx processors.
160
Moritz Fischer0075dac2015-12-28 09:47:11 -0800161config SYS_I2C_CADENCE
162 tristate "Cadence I2C Controller"
Michal Simekc28665d2020-08-06 15:18:36 +0200163 depends on DM_I2C
Moritz Fischer0075dac2015-12-28 09:47:11 -0800164 help
165 Say yes here to select Cadence I2C Host Controller. This controller is
166 e.g. used by Xilinx Zynq.
167
Arthur Life661ba2020-06-01 12:56:31 -0700168config SYS_I2C_CA
169 tristate "Cortina-Access I2C Controller"
170 depends on DM_I2C && CORTINA_PLATFORM
171 default n
172 help
173 Add support for the Cortina Access I2C host controller.
174 Say yes here to select Cortina-Access I2C Host Controller.
175
Adam Forddecc8952018-08-10 05:05:22 -0500176config SYS_I2C_DAVINCI
177 bool "Davinci I2C Controller"
178 depends on (ARCH_KEYSTONE || ARCH_DAVINCI)
179 help
180 Say yes here to add support for Davinci and Keystone I2C controller
181
Stefan Roeseb71955f2016-04-28 09:47:17 +0200182config SYS_I2C_DW
183 bool "Designware I2C Controller"
184 default n
185 help
186 Say yes here to select the Designware I2C Host Controller. This
187 controller is used in various SoCs, e.g. the ST SPEAr, Altera
188 SoCFPGA, Synopsys ARC700 and some Intel x86 SoCs.
189
maxims@google.com7f613312017-04-17 12:00:30 -0700190config SYS_I2C_ASPEED
191 bool "Aspeed I2C Controller"
192 depends on DM_I2C && ARCH_ASPEED
193 help
194 Say yes here to select Aspeed I2C Host Controller. The driver
195 supports AST2500 and AST2400 controllers, but is very limited.
196 Only single master mode is supported and only byte-by-byte
197 synchronous reads and writes are supported, no Pool Buffers or DMA.
198
Simon Glass5e66fdc2016-01-17 16:11:44 -0700199config SYS_I2C_INTEL
200 bool "Intel I2C/SMBUS driver"
201 depends on DM_I2C
202 help
203 Add support for the Intel SMBUS driver. So far this driver is just
204 a stub which perhaps some basic init. There is no implementation of
205 the I2C API meaning that any I2C operations will immediately fail
206 for now.
207
Peng Fand684adb2017-02-24 09:54:18 +0800208config SYS_I2C_IMX_LPI2C
209 bool "NXP i.MX LPI2C driver"
Peng Fand684adb2017-02-24 09:54:18 +0800210 help
211 Add support for the NXP i.MX LPI2C driver.
212
Trevor Woerner5f37e502021-06-10 22:37:08 -0400213config SYS_I2C_LPC32XX
214 bool "LPC32XX I2C driver"
215 depends on ARCH_LPC32XX
216 help
217 Enable support for the LPC32xx I2C driver.
218
Beniamino Galvanid5b199c2017-10-29 10:09:00 +0100219config SYS_I2C_MESON
220 bool "Amlogic Meson I2C driver"
221 depends on DM_I2C && ARCH_MESON
222 help
Beniamino Galvani83b153d2017-11-26 17:40:54 +0100223 Add support for the I2C controller available in Amlogic Meson
224 SoCs. The controller supports programmable bus speed including
225 standard (100kbits/s) and fast (400kbit/s) speed and allows the
226 software to define a flexible format of the bit streams. It has an
227 internal buffer holding up to 8 bytes for transfers and supports
228 both 7-bit and 10-bit addresses.
Beniamino Galvanid5b199c2017-10-29 10:09:00 +0100229
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100230config SYS_I2C_MXC
Sriram Dash7122a0c2018-02-06 11:26:30 +0530231 bool "NXP MXC I2C driver"
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100232 help
Chris Packham94d0d3d2019-01-13 22:13:25 +1300233 Add support for the NXP I2C driver. This supports up to four bus
234 channels and operating on standard mode up to 100 kbits/s and fast
235 mode up to 400 kbits/s.
Jagan Teki0aedd7f2016-12-06 00:00:57 +0100236
Tom Rini1a195882021-08-18 23:12:33 -0400237if SYS_I2C_MXC && (SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY)
Sriram Dash7122a0c2018-02-06 11:26:30 +0530238config SYS_I2C_MXC_I2C1
239 bool "NXP MXC I2C1"
240 help
241 Add support for NXP MXC I2C Controller 1.
242 Required for SoCs which have I2C MXC controller 1 eg LS1088A, LS2080A
243
244config SYS_I2C_MXC_I2C2
245 bool "NXP MXC I2C2"
246 help
247 Add support for NXP MXC I2C Controller 2.
248 Required for SoCs which have I2C MXC controller 2 eg LS1088A, LS2080A
249
250config SYS_I2C_MXC_I2C3
251 bool "NXP MXC I2C3"
252 help
253 Add support for NXP MXC I2C Controller 3.
254 Required for SoCs which have I2C MXC controller 3 eg LS1088A, LS2080A
255
256config SYS_I2C_MXC_I2C4
257 bool "NXP MXC I2C4"
258 help
259 Add support for NXP MXC I2C Controller 4.
260 Required for SoCs which have I2C MXC controller 4 eg LS1088A, LS2080A
Sriram Dasha64aa192018-02-06 11:26:31 +0530261
262config SYS_I2C_MXC_I2C5
263 bool "NXP MXC I2C5"
264 help
265 Add support for NXP MXC I2C Controller 5.
266 Required for SoCs which have I2C MXC controller 5 eg LX2160A
267
268config SYS_I2C_MXC_I2C6
269 bool "NXP MXC I2C6"
270 help
271 Add support for NXP MXC I2C Controller 6.
272 Required for SoCs which have I2C MXC controller 6 eg LX2160A
273
274config SYS_I2C_MXC_I2C7
275 bool "NXP MXC I2C7"
276 help
277 Add support for NXP MXC I2C Controller 7.
278 Required for SoCs which have I2C MXC controller 7 eg LX2160A
279
280config SYS_I2C_MXC_I2C8
281 bool "NXP MXC I2C8"
282 help
283 Add support for NXP MXC I2C Controller 8.
284 Required for SoCs which have I2C MXC controller 8 eg LX2160A
Sriram Dash7122a0c2018-02-06 11:26:30 +0530285endif
286
287if SYS_I2C_MXC_I2C1
288config SYS_MXC_I2C1_SPEED
289 int "I2C Channel 1 speed"
Tom Rini48425b12021-02-09 08:03:10 -0500290 default 40000000 if TARGET_LS2080A_EMU
Sriram Dash7122a0c2018-02-06 11:26:30 +0530291 default 100000
292 help
293 MXC I2C Channel 1 speed
294
295config SYS_MXC_I2C1_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400296 hex "I2C1 Slave"
Sriram Dash7122a0c2018-02-06 11:26:30 +0530297 default 0
298 help
299 MXC I2C1 Slave
300endif
301
302if SYS_I2C_MXC_I2C2
303config SYS_MXC_I2C2_SPEED
304 int "I2C Channel 2 speed"
Tom Rini48425b12021-02-09 08:03:10 -0500305 default 40000000 if TARGET_LS2080A_EMU
Sriram Dash7122a0c2018-02-06 11:26:30 +0530306 default 100000
307 help
308 MXC I2C Channel 2 speed
309
310config SYS_MXC_I2C2_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400311 hex "I2C2 Slave"
Sriram Dash7122a0c2018-02-06 11:26:30 +0530312 default 0
313 help
314 MXC I2C2 Slave
315endif
316
317if SYS_I2C_MXC_I2C3
318config SYS_MXC_I2C3_SPEED
319 int "I2C Channel 3 speed"
320 default 100000
321 help
322 MXC I2C Channel 3 speed
323
324config SYS_MXC_I2C3_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400325 hex "I2C3 Slave"
Sriram Dash7122a0c2018-02-06 11:26:30 +0530326 default 0
327 help
328 MXC I2C3 Slave
329endif
330
331if SYS_I2C_MXC_I2C4
332config SYS_MXC_I2C4_SPEED
333 int "I2C Channel 4 speed"
334 default 100000
335 help
336 MXC I2C Channel 4 speed
337
338config SYS_MXC_I2C4_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400339 hex "I2C4 Slave"
Sriram Dash7122a0c2018-02-06 11:26:30 +0530340 default 0
341 help
342 MXC I2C4 Slave
343endif
344
Sriram Dasha64aa192018-02-06 11:26:31 +0530345if SYS_I2C_MXC_I2C5
346config SYS_MXC_I2C5_SPEED
347 int "I2C Channel 5 speed"
348 default 100000
349 help
350 MXC I2C Channel 5 speed
351
352config SYS_MXC_I2C5_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400353 hex "I2C5 Slave"
Sriram Dasha64aa192018-02-06 11:26:31 +0530354 default 0
355 help
356 MXC I2C5 Slave
357endif
358
359if SYS_I2C_MXC_I2C6
360config SYS_MXC_I2C6_SPEED
361 int "I2C Channel 6 speed"
362 default 100000
363 help
364 MXC I2C Channel 6 speed
365
366config SYS_MXC_I2C6_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400367 hex "I2C6 Slave"
Sriram Dasha64aa192018-02-06 11:26:31 +0530368 default 0
369 help
370 MXC I2C6 Slave
371endif
372
373if SYS_I2C_MXC_I2C7
374config SYS_MXC_I2C7_SPEED
375 int "I2C Channel 7 speed"
376 default 100000
377 help
378 MXC I2C Channel 7 speed
379
380config SYS_MXC_I2C7_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400381 hex "I2C7 Slave"
Sriram Dasha64aa192018-02-06 11:26:31 +0530382 default 0
383 help
384 MXC I2C7 Slave
385endif
386
387if SYS_I2C_MXC_I2C8
388config SYS_MXC_I2C8_SPEED
389 int "I2C Channel 8 speed"
390 default 100000
391 help
392 MXC I2C Channel 8 speed
393
394config SYS_MXC_I2C8_SLAVE
Tom Rini1a195882021-08-18 23:12:33 -0400395 hex "I2C8 Slave"
Sriram Dasha64aa192018-02-06 11:26:31 +0530396 default 0
397 help
398 MXC I2C8 Slave
399endif
400
Stefan Bosch9d85dfb2020-07-10 19:07:28 +0200401config SYS_I2C_NEXELL
402 bool "Nexell I2C driver"
403 depends on DM_I2C
404 help
405 Add support for the Nexell I2C driver. This is used with various
406 Nexell parts such as S5Pxx18 series SoCs. All chips
407 have several I2C ports and all are provided, controlled by the
408 device tree.
409
Pragnesh Patel1cfbd7a2020-11-14 14:42:34 +0530410config SYS_I2C_OCORES
411 bool "ocores I2C driver"
412 depends on DM_I2C
413 help
414 Add support for ocores I2C controller. For details see
415 https://opencores.org/projects/i2c
416
Adam Ford85901162017-08-07 13:11:34 -0500417config SYS_I2C_OMAP24XX
418 bool "TI OMAP2+ I2C driver"
Vignesh R64d4f552019-06-04 18:08:11 -0500419 depends on ARCH_OMAP2PLUS || ARCH_K3
Adam Ford85901162017-08-07 13:11:34 -0500420 help
421 Add support for the OMAP2+ I2C driver.
422
Marek Vasut27165962018-04-21 18:57:28 +0200423config SYS_I2C_RCAR_I2C
424 bool "Renesas RCar I2C driver"
425 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
426 help
427 Support for Renesas RCar I2C controller.
428
Marek Vasut125d8df2017-11-28 08:02:27 +0100429config SYS_I2C_RCAR_IIC
430 bool "Renesas RCar Gen3 IIC driver"
Marek Vasut4bc57a32018-02-17 02:17:40 +0100431 depends on (RCAR_GEN3 || RCAR_GEN2) && DM_I2C
Marek Vasut125d8df2017-11-28 08:02:27 +0100432 help
433 Support for Renesas RCar Gen3 IIC controller.
434
Simon Glass3595f952015-08-30 16:55:39 -0600435config SYS_I2C_ROCKCHIP
436 bool "Rockchip I2C driver"
437 depends on DM_I2C
438 help
439 Add support for the Rockchip I2C driver. This is used with various
440 Rockchip parts such as RK3126, RK3128, RK3036 and RK3288. All chips
Chris Packham94d0d3d2019-01-13 22:13:25 +1300441 have several I2C ports and all are provided, controlled by the
Simon Glass3595f952015-08-30 16:55:39 -0600442 device tree.
443
Simon Glass39bc3be2015-03-06 13:19:04 -0700444config SYS_I2C_SANDBOX
445 bool "Sandbox I2C driver"
446 depends on SANDBOX && DM_I2C
447 help
448 Enable I2C support for sandbox. This is an emulation of a real I2C
449 bus. Devices can be attached to the bus using the device tree
Masahiro Yamada8d8371d2017-02-11 12:39:55 +0900450 which specifies the driver to use. See sandbox.dts as an example.
Simon Glass39bc3be2015-03-06 13:19:04 -0700451
Tom Rinib9a254d2021-08-18 23:12:34 -0400452config SYS_I2C_SH
453 bool "Legacy SuperH I2C interface"
454 depends on ARCH_RMOBILE && SYS_I2C_LEGACY
455 help
456 Enable the legacy SuperH I2C interface.
457
458if SYS_I2C_SH
459config SYS_I2C_SH_NUM_CONTROLLERS
460 int
461 default 5
462
463config SYS_I2C_SH_BASE0
464 hex
465 default 0xE6820000
466
467config SYS_I2C_SH_BASE1
468 hex
469 default 0xE6822000
470
471config SYS_I2C_SH_BASE2
472 hex
473 default 0xE6824000
474
475config SYS_I2C_SH_BASE3
476 hex
477 default 0xE6826000
478
479config SYS_I2C_SH_BASE4
480 hex
481 default 0xE6828000
482
483config SH_I2C_8BIT
484 bool
485 default y
486
487config SH_I2C_DATA_HIGH
488 int
489 default 4
490
491config SH_I2C_DATA_LOW
492 int
493 default 5
494
495config SH_I2C_CLOCK
496 int
497 default 104000000
498endif
499
Tom Rini5817ff02021-08-17 17:59:46 -0400500config SYS_I2C_SOFT
501 bool "Legacy software I2C interface"
502 help
503 Enable the legacy software defined I2C interface
504
505config SYS_I2C_SOFT_SPEED
506 int "Software I2C bus speed"
507 depends on SYS_I2C_SOFT
508 default 100000
509 help
510 Speed of the software I2C bus
511
512config SYS_I2C_SOFT_SLAVE
513 hex "Software I2C slave address"
514 depends on SYS_I2C_SOFT
515 default 0xfe
516 help
517 Slave address of the software I2C bus
518
Suneel Garapatic6baea22020-05-26 14:13:07 +0200519config SYS_I2C_OCTEON
520 bool "Octeon II/III/TX/TX2 I2C driver"
521 depends on (ARCH_OCTEON || ARCH_OCTEONTX || ARCH_OCTEONTX2) && DM_I2C
522 default y
523 help
524 Add support for the Marvell Octeon I2C driver. This is used with
525 various Octeon parts such as Octeon II/III and OcteonTX/TX2. All
526 chips have several I2C ports and all are provided, controlled by
527 the device tree.
528
Jaehoon Chungf7e6a032017-01-09 14:47:52 +0900529config SYS_I2C_S3C24X0
530 bool "Samsung I2C driver"
Tom Rinifc917de2021-08-17 17:59:42 -0400531 depends on (ARCH_EXYNOS4 || ARCH_EXYNOS5) && DM_I2C
Jaehoon Chungf7e6a032017-01-09 14:47:52 +0900532 help
533 Support for Samsung I2C controller as Samsung SoCs.
Simon Glass39bc3be2015-03-06 13:19:04 -0700534
Patrice Chotardebf442d2017-08-09 14:45:27 +0200535config SYS_I2C_STM32F7
536 bool "STMicroelectronics STM32F7 I2C support"
Patrick Delaunay85b53972018-03-12 10:46:10 +0100537 depends on (STM32F7 || STM32H7 || ARCH_STM32MP) && DM_I2C
Patrice Chotardebf442d2017-08-09 14:45:27 +0200538 help
539 Enable this option to add support for STM32 I2C controller
540 introduced with STM32F7/H7 SoCs. This I2C controller supports :
541 _ Slave and master modes
542 _ Multimaster capability
543 _ Standard-mode (up to 100 kHz)
544 _ Fast-mode (up to 400 kHz)
545 _ Fast-mode Plus (up to 1 MHz)
546 _ 7-bit and 10-bit addressing mode
547 _ Multiple 7-bit slave addresses (2 addresses, 1 with configurable mask)
548 _ All 7-bit addresses acknowledge mode
549 _ General call
550 _ Programmable setup and hold times
551 _ Easy to use event management
552 _ Optional clock stretching
553 _ Software reset
554
Jassi Brar23325cf2021-06-04 18:44:48 +0900555config SYS_I2C_SYNQUACER
556 bool "Socionext SynQuacer I2C controller"
557 depends on ARCH_SYNQUACER && DM_I2C
558 help
559 Support for Socionext Synquacer I2C controller. This I2C controller
560 will be used for RTC and LS-connector on DeveloperBox.
561
Peter Robinson12d37d82019-02-20 12:17:26 +0000562config SYS_I2C_TEGRA
563 bool "NVIDIA Tegra internal I2C controller"
Trevor Woerner513f6402020-05-06 08:02:41 -0400564 depends on ARCH_TEGRA
Peter Robinson12d37d82019-02-20 12:17:26 +0000565 help
566 Support for NVIDIA I2C controller available in Tegra SoCs.
567
Masahiro Yamada96a42ed2015-01-13 12:44:36 +0900568config SYS_I2C_UNIPHIER
569 bool "UniPhier I2C driver"
570 depends on ARCH_UNIPHIER && DM_I2C
571 default y
572 help
Masahiro Yamada563ee4c2015-05-29 17:30:01 +0900573 Support for UniPhier I2C controller driver. This I2C controller
574 is used on PH1-LD4, PH1-sLD8 or older UniPhier SoCs.
Masahiro Yamada4e82e5e2015-01-13 12:44:37 +0900575
576config SYS_I2C_UNIPHIER_F
577 bool "UniPhier FIFO-builtin I2C driver"
578 depends on ARCH_UNIPHIER && DM_I2C
579 default y
580 help
Masahiro Yamada563ee4c2015-05-29 17:30:01 +0900581 Support for UniPhier FIFO-builtin I2C controller driver.
Masahiro Yamada4e82e5e2015-01-13 12:44:37 +0900582 This I2C controller is used on PH1-Pro4 or newer UniPhier SoCs.
Simon Glass2a80c402015-08-03 08:19:21 -0600583
Heiko Schochera37c1962018-10-11 07:26:33 +0200584config SYS_I2C_VERSATILE
585 bool "Arm Ltd Versatile I2C bus driver"
Tom Rini5af921e2021-02-20 20:05:47 -0500586 depends on DM_I2C && TARGET_VEXPRESS64_JUNO
Heiko Schochera37c1962018-10-11 07:26:33 +0200587 help
588 Add support for the Arm Ltd Versatile Express I2C driver. The I2C host
589 controller is present in the development boards manufactured by Arm Ltd.
590
mario.six@gdsys.cc355a1272016-07-21 11:57:10 +0200591config SYS_I2C_MVTWSI
592 bool "Marvell I2C driver"
mario.six@gdsys.cc355a1272016-07-21 11:57:10 +0200593 help
594 Support for Marvell I2C controllers as used on the orion5x and
595 kirkwood SoC families.
596
Stephen Warren67a83482016-08-08 11:28:27 -0600597config TEGRA186_BPMP_I2C
598 bool "Enable Tegra186 BPMP-based I2C driver"
599 depends on TEGRA186_BPMP
600 help
601 Support for Tegra I2C controllers managed by the BPMP (Boot and
602 Power Management Processor). On Tegra186, some I2C controllers are
603 directly controlled by the main CPU, whereas others are controlled
604 by the BPMP, and can only be accessed by the main CPU via IPC
605 requests to the BPMP. This driver covers the latter case.
606
Tom Rinia6e29232021-08-18 23:12:32 -0400607config SYS_I2C_SLAVE
608 hex "I2C Slave address channel (all buses)"
609 depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
610 default 0xfe
611 help
612 I2C Slave address channel 0 for all buses in the legacy drivers.
613 Many boards/controllers/drivers don't support an I2C slave
614 interface so provide a default slave address for them for use in
615 common code. A real value for CONFIG_SYS_I2C_SLAVE should be
616 defined for any board which does support a slave interface and
617 this default used otherwise.
618
619config SYS_I2C_SPEED
620 int "I2C Slave channel 0 speed (all buses)"
621 depends on SYS_I2C_LEGACY || SPL_SYS_I2C_LEGACY || TPL_SYS_I2C_LEGACY
622 default 100000
623 help
624 I2C Slave speed channel 0 for all buses in the legacy drivers.
625
Adam Fordfa1dd3d2017-08-11 06:39:34 -0500626config SYS_I2C_BUS_MAX
627 int "Max I2C busses"
628 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_SOCFPGA
629 default 2 if TI816X
630 default 3 if OMAP34XX || AM33XX || AM43XX || ARCH_KEYSTONE
631 default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
632 default 5 if OMAP54XX
633 help
634 Define the maximum number of available I2C buses.
635
Marek Vasut9de0e2a2018-12-19 12:26:27 +0100636config SYS_I2C_XILINX_XIIC
637 bool "Xilinx AXI I2C driver"
638 depends on DM_I2C
639 help
640 Support for Xilinx AXI I2C controller.
641
Mario Six3bb409c2018-01-15 11:08:11 +0100642config SYS_I2C_IHS
643 bool "gdsys IHS I2C driver"
644 depends on DM_I2C
645 help
646 Support for gdsys IHS I2C driver on FPGA bus.
647
Simon Glass2a80c402015-08-03 08:19:21 -0600648source "drivers/i2c/muxes/Kconfig"
Masahiro Yamadacc85b7b2015-07-26 02:46:26 +0900649
Simon Glass8e85e3c2021-07-10 21:14:35 -0600650endif