blob: 93f14098ccb627db190f4b80c80d33057cd38507 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
wdenk4a9cbbe2002-08-27 09:48:53 +00002/*
3 * (C) Copyright 2000, 2001
4 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
wdenk4a9cbbe2002-08-27 09:48:53 +00005 */
6
7/*
8 * FPGA support
9 */
wdenk4a9cbbe2002-08-27 09:48:53 +000010#include <command.h>
Simon Glass0af6e2d2019-08-01 09:46:52 -060011#include <env.h>
wdenk57b2d802003-06-27 21:31:46 +000012#include <fpga.h>
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +053013#include <fs.h>
Simon Glass1a974af2019-08-01 09:46:36 -060014#include <gzip.h>
Simon Glass2dc9c342020-05-10 11:40:01 -060015#include <image.h>
Simon Glass0f2af882020-05-10 11:40:05 -060016#include <log.h>
wdenk525d7b62005-01-22 18:13:04 +000017#include <malloc.h>
wdenk4a9cbbe2002-08-27 09:48:53 +000018
Michal Simek02d95c02018-06-04 14:57:34 +020019static long do_fpga_get_device(char *arg)
20{
21 long dev = FPGA_INVALID_DEVICE;
22 char *devstr = env_get("fpga");
23
24 if (devstr)
25 /* Should be strtol to handle -1 cases */
26 dev = simple_strtol(devstr, NULL, 16);
27
Michal Simek19942472018-07-26 15:33:51 +020028 if (dev == FPGA_INVALID_DEVICE && arg)
Michal Simek02d95c02018-06-04 14:57:34 +020029 dev = simple_strtol(arg, NULL, 16);
30
31 debug("%s: device = %ld\n", __func__, dev);
32
33 return dev;
34}
35
Michal Simek6f6be6f2018-06-04 15:51:23 +020036static int do_fpga_check_params(long *dev, long *fpga_data, size_t *data_size,
Simon Glassed38aef2020-05-10 11:40:03 -060037 struct cmd_tbl *cmdtp, int argc,
38 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +020039{
40 size_t local_data_size;
41 long local_fpga_data;
42
43 debug("%s %d, %d\n", __func__, argc, cmdtp->maxargs);
44
45 if (argc != cmdtp->maxargs) {
46 debug("fpga: incorrect parameters passed\n");
47 return CMD_RET_USAGE;
48 }
49
50 *dev = do_fpga_get_device(argv[0]);
51
52 local_fpga_data = simple_strtol(argv[1], NULL, 16);
53 if (!local_fpga_data) {
54 debug("fpga: zero fpga_data address\n");
55 return CMD_RET_USAGE;
56 }
57 *fpga_data = local_fpga_data;
58
Simon Glass3ff49ec2021-07-24 09:03:29 -060059 local_data_size = hextoul(argv[2], NULL);
Michal Simek6f6be6f2018-06-04 15:51:23 +020060 if (!local_data_size) {
61 debug("fpga: zero size\n");
62 return CMD_RET_USAGE;
63 }
64 *data_size = local_data_size;
65
66 return 0;
67}
68
Michal Simeka2555972018-05-30 10:00:40 +020069#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Simon Glassed38aef2020-05-10 11:40:03 -060070int do_fpga_loads(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +000071{
wdenk1ebf41e2004-01-02 14:00:00 +000072 size_t data_size = 0;
Michal Simekc1fd3122018-06-05 15:14:39 +020073 long fpga_data, dev;
74 int ret;
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +053075 struct fpga_secure_info fpga_sec_info;
76
77 memset(&fpga_sec_info, 0, sizeof(fpga_sec_info));
wdenk4a9cbbe2002-08-27 09:48:53 +000078
Michal Simekc1fd3122018-06-05 15:14:39 +020079 if (argc < 5) {
80 debug("fpga: incorrect parameters passed\n");
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +053081 return CMD_RET_USAGE;
82 }
83
Michal Simekc1fd3122018-06-05 15:14:39 +020084 if (argc == 6)
85 fpga_sec_info.userkey_addr = (u8 *)(uintptr_t)
86 simple_strtoull(argv[5],
87 NULL, 16);
88 else
89 /*
90 * If 6th parameter is not passed then do_fpga_check_params
91 * will get 5 instead of expected 6 which means that function
92 * return CMD_RET_USAGE. Increase number of params +1 to pass
93 * this.
94 */
95 argc++;
Michal Simek2af67462018-05-30 11:18:38 +020096
Simon Glass3ff49ec2021-07-24 09:03:29 -060097 fpga_sec_info.encflag = (u8)hextoul(argv[4], NULL);
98 fpga_sec_info.authflag = (u8)hextoul(argv[3], NULL);
Siva Durga Prasad Paladugu8f039b12018-05-31 15:10:21 +053099
Michal Simekc1fd3122018-06-05 15:14:39 +0200100 if (fpga_sec_info.authflag >= FPGA_NO_ENC_OR_NO_AUTH &&
101 fpga_sec_info.encflag >= FPGA_NO_ENC_OR_NO_AUTH) {
102 debug("fpga: Use <fpga load> for NonSecure bitstream\n");
103 return CMD_RET_USAGE;
wdenk1ebf41e2004-01-02 14:00:00 +0000104 }
wdenk4a9cbbe2002-08-27 09:48:53 +0000105
Michal Simekc1fd3122018-06-05 15:14:39 +0200106 if (fpga_sec_info.encflag == FPGA_ENC_USR_KEY &&
107 !fpga_sec_info.userkey_addr) {
108 debug("fpga: User key not provided\n");
Michal Simekf4337f32018-05-30 10:04:34 +0200109 return CMD_RET_USAGE;
Stefano Babic67d7f562010-10-19 09:22:52 +0200110 }
111
Michal Simekc1fd3122018-06-05 15:14:39 +0200112 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
113 cmdtp, argc, argv);
114 if (ret)
115 return ret;
Stefan Roese5f1cf2d2006-08-15 14:15:51 +0200116
Michal Simekc1fd3122018-06-05 15:14:39 +0200117 return fpga_loads(dev, (void *)fpga_data, data_size, &fpga_sec_info);
wdenk4a9cbbe2002-08-27 09:48:53 +0000118}
Michal Simekc1fd3122018-06-05 15:14:39 +0200119#endif
Michal Simeke2846782018-06-04 15:51:16 +0200120
121#if defined(CONFIG_CMD_FPGA_LOADFS)
Simon Glassed38aef2020-05-10 11:40:03 -0600122static int do_fpga_loadfs(struct cmd_tbl *cmdtp, int flag, int argc,
Michal Simeke2846782018-06-04 15:51:16 +0200123 char *const argv[])
124{
125 size_t data_size = 0;
126 long fpga_data, dev;
127 int ret;
128 fpga_fs_info fpga_fsinfo;
129
130 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
131 cmdtp, argc, argv);
132 if (ret)
133 return ret;
134
135 fpga_fsinfo.fstype = FS_TYPE_ANY;
Simon Glass3ff49ec2021-07-24 09:03:29 -0600136 fpga_fsinfo.blocksize = (unsigned int)hextoul(argv[3], NULL);
Michal Simeke2846782018-06-04 15:51:16 +0200137 fpga_fsinfo.interface = argv[4];
138 fpga_fsinfo.dev_part = argv[5];
139 fpga_fsinfo.filename = argv[6];
140
141 return fpga_fsload(dev, (void *)fpga_data, data_size, &fpga_fsinfo);
142}
143#endif
wdenk4a9cbbe2002-08-27 09:48:53 +0000144
Simon Glassed38aef2020-05-10 11:40:03 -0600145static int do_fpga_info(struct cmd_tbl *cmdtp, int flag, int argc,
146 char *const argv[])
Michal Simek02d95c02018-06-04 14:57:34 +0200147{
148 long dev = do_fpga_get_device(argv[0]);
149
150 return fpga_info(dev);
151}
152
Simon Glassed38aef2020-05-10 11:40:03 -0600153static int do_fpga_dump(struct cmd_tbl *cmdtp, int flag, int argc,
154 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200155{
156 size_t data_size = 0;
157 long fpga_data, dev;
158 int ret;
159
160 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
161 cmdtp, argc, argv);
162 if (ret)
163 return ret;
164
165 return fpga_dump(dev, (void *)fpga_data, data_size);
166}
167
Simon Glassed38aef2020-05-10 11:40:03 -0600168static int do_fpga_load(struct cmd_tbl *cmdtp, int flag, int argc,
169 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200170{
171 size_t data_size = 0;
172 long fpga_data, dev;
173 int ret;
174
175 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
176 cmdtp, argc, argv);
177 if (ret)
178 return ret;
179
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +0300180 return fpga_load(dev, (void *)fpga_data, data_size, BIT_FULL, 0);
Michal Simek6f6be6f2018-06-04 15:51:23 +0200181}
182
Simon Glassed38aef2020-05-10 11:40:03 -0600183static int do_fpga_loadb(struct cmd_tbl *cmdtp, int flag, int argc,
184 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200185{
186 size_t data_size = 0;
187 long fpga_data, dev;
188 int ret;
189
190 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
191 cmdtp, argc, argv);
192 if (ret)
193 return ret;
194
195 return fpga_loadbitstream(dev, (void *)fpga_data, data_size, BIT_FULL);
196}
197
198#if defined(CONFIG_CMD_FPGA_LOADP)
Simon Glassed38aef2020-05-10 11:40:03 -0600199static int do_fpga_loadp(struct cmd_tbl *cmdtp, int flag, int argc,
200 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200201{
202 size_t data_size = 0;
203 long fpga_data, dev;
204 int ret;
205
206 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
207 cmdtp, argc, argv);
208 if (ret)
209 return ret;
210
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +0300211 return fpga_load(dev, (void *)fpga_data, data_size, BIT_PARTIAL, 0);
Michal Simek6f6be6f2018-06-04 15:51:23 +0200212}
213#endif
214
215#if defined(CONFIG_CMD_FPGA_LOADBP)
Simon Glassed38aef2020-05-10 11:40:03 -0600216static int do_fpga_loadbp(struct cmd_tbl *cmdtp, int flag, int argc,
217 char *const argv[])
Michal Simek6f6be6f2018-06-04 15:51:23 +0200218{
219 size_t data_size = 0;
220 long fpga_data, dev;
221 int ret;
222
223 ret = do_fpga_check_params(&dev, &fpga_data, &data_size,
224 cmdtp, argc, argv);
225 if (ret)
226 return ret;
227
228 return fpga_loadbitstream(dev, (void *)fpga_data, data_size,
229 BIT_PARTIAL);
230}
231#endif
232
Michal Simek4aeae102018-06-04 16:15:58 +0200233#if defined(CONFIG_CMD_FPGA_LOADMK)
Simon Glassed38aef2020-05-10 11:40:03 -0600234static int do_fpga_loadmk(struct cmd_tbl *cmdtp, int flag, int argc,
235 char *const argv[])
Michal Simek4aeae102018-06-04 16:15:58 +0200236{
237 size_t data_size = 0;
238 void *fpga_data = NULL;
239#if defined(CONFIG_FIT)
240 const char *fit_uname = NULL;
241 ulong fit_addr;
242#endif
243 ulong dev = do_fpga_get_device(argv[0]);
244 char *datastr = env_get("fpgadata");
245
Michal Simek19942472018-07-26 15:33:51 +0200246 debug("fpga: argc %x, dev %lx, datastr %s\n", argc, dev, datastr);
247
248 if (dev == FPGA_INVALID_DEVICE) {
249 debug("fpga: Invalid fpga device\n");
250 return CMD_RET_USAGE;
251 }
252
253 if (argc == 0 && !datastr) {
254 debug("fpga: No datastr passed\n");
255 return CMD_RET_USAGE;
256 }
Michal Simek4aeae102018-06-04 16:15:58 +0200257
258 if (argc == 2) {
Michal Simek19942472018-07-26 15:33:51 +0200259 datastr = argv[1];
260 debug("fpga: Full command with two args\n");
261 } else if (argc == 1 && !datastr) {
262 debug("fpga: Dev is setup - fpgadata passed\n");
263 datastr = argv[0];
264 }
265
Michal Simek4aeae102018-06-04 16:15:58 +0200266#if defined(CONFIG_FIT)
Michal Simek19942472018-07-26 15:33:51 +0200267 if (fit_parse_subimage(datastr, (ulong)fpga_data,
268 &fit_addr, &fit_uname)) {
269 fpga_data = (void *)fit_addr;
270 debug("* fpga: subimage '%s' from FIT image ",
271 fit_uname);
272 debug("at 0x%08lx\n", fit_addr);
273 } else
Michal Simek4aeae102018-06-04 16:15:58 +0200274#endif
Michal Simek19942472018-07-26 15:33:51 +0200275 {
Simon Glass3ff49ec2021-07-24 09:03:29 -0600276 fpga_data = (void *)hextoul(datastr, NULL);
Michal Simek19942472018-07-26 15:33:51 +0200277 debug("* fpga: cmdline image address = 0x%08lx\n",
278 (ulong)fpga_data);
279 }
280 debug("%s: fpga_data = 0x%lx\n", __func__, (ulong)fpga_data);
281 if (!fpga_data) {
282 puts("Zero fpga_data address\n");
283 return CMD_RET_USAGE;
Michal Simek4aeae102018-06-04 16:15:58 +0200284 }
285
286 switch (genimg_get_format(fpga_data)) {
Tom Rinic220bd92019-05-23 07:14:07 -0400287#if defined(CONFIG_LEGACY_IMAGE_FORMAT)
Michal Simek4aeae102018-06-04 16:15:58 +0200288 case IMAGE_FORMAT_LEGACY:
289 {
Simon Glassbb7d3bb2022-09-06 20:26:52 -0600290 struct legacy_img_hdr *hdr = (struct legacy_img_hdr *)fpga_data;
Michal Simek4aeae102018-06-04 16:15:58 +0200291 ulong data;
292 u8 comp;
293
294 comp = image_get_comp(hdr);
295 if (comp == IH_COMP_GZIP) {
296#if defined(CONFIG_GZIP)
297 ulong image_buf = image_get_data(hdr);
298 ulong image_size = ~0UL;
299
300 data = image_get_load(hdr);
301
302 if (gunzip((void *)data, ~0UL, (void *)image_buf,
303 &image_size) != 0) {
304 puts("GUNZIP: error\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200305 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200306 }
307 data_size = image_size;
308#else
309 puts("Gunzip image is not supported\n");
310 return 1;
311#endif
312 } else {
313 data = (ulong)image_get_data(hdr);
314 data_size = image_get_data_size(hdr);
315 }
316 return fpga_load(dev, (void *)data, data_size,
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +0300317 BIT_FULL, 0);
Michal Simek4aeae102018-06-04 16:15:58 +0200318 }
319#endif
320#if defined(CONFIG_FIT)
321 case IMAGE_FORMAT_FIT:
322 {
323 const void *fit_hdr = (const void *)fpga_data;
Sean Andersonb89d61a2022-08-16 11:16:05 -0400324 int err;
Michal Simek4aeae102018-06-04 16:15:58 +0200325 const void *fit_data;
326
327 if (!fit_uname) {
328 puts("No FIT subimage unit name\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200329 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200330 }
331
Simon Glassd563c252021-02-15 17:08:09 -0700332 if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
Michal Simek4aeae102018-06-04 16:15:58 +0200333 puts("Bad FIT image format\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200334 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200335 }
336
Sean Andersonb89d61a2022-08-16 11:16:05 -0400337 err = fit_get_data_node(fit_hdr, fit_uname, &fit_data,
338 &data_size);
339 if (err) {
340 printf("Could not load '%s' subimage (err %d)\n",
341 fit_uname, err);
Michal Simekec2e3dc2018-06-05 16:43:38 +0200342 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200343 }
344
Oleksandr Suvorov4ff163d2022-07-22 17:16:07 +0300345 return fpga_load(dev, fit_data, data_size, BIT_FULL, 0);
Michal Simek4aeae102018-06-04 16:15:58 +0200346 }
347#endif
348 default:
349 puts("** Unknown image type\n");
Michal Simekec2e3dc2018-06-05 16:43:38 +0200350 return CMD_RET_FAILURE;
Michal Simek4aeae102018-06-04 16:15:58 +0200351 }
352}
353#endif
354
Simon Glassed38aef2020-05-10 11:40:03 -0600355static struct cmd_tbl fpga_commands[] = {
Michal Simek02d95c02018-06-04 14:57:34 +0200356 U_BOOT_CMD_MKENT(info, 1, 1, do_fpga_info, "", ""),
Michal Simek6f6be6f2018-06-04 15:51:23 +0200357 U_BOOT_CMD_MKENT(dump, 3, 1, do_fpga_dump, "", ""),
358 U_BOOT_CMD_MKENT(load, 3, 1, do_fpga_load, "", ""),
359 U_BOOT_CMD_MKENT(loadb, 3, 1, do_fpga_loadb, "", ""),
360#if defined(CONFIG_CMD_FPGA_LOADP)
361 U_BOOT_CMD_MKENT(loadp, 3, 1, do_fpga_loadp, "", ""),
362#endif
363#if defined(CONFIG_CMD_FPGA_LOADBP)
364 U_BOOT_CMD_MKENT(loadbp, 3, 1, do_fpga_loadbp, "", ""),
365#endif
Michal Simeke2846782018-06-04 15:51:16 +0200366#if defined(CONFIG_CMD_FPGA_LOADFS)
367 U_BOOT_CMD_MKENT(loadfs, 7, 1, do_fpga_loadfs, "", ""),
368#endif
Michal Simek4aeae102018-06-04 16:15:58 +0200369#if defined(CONFIG_CMD_FPGA_LOADMK)
370 U_BOOT_CMD_MKENT(loadmk, 2, 1, do_fpga_loadmk, "", ""),
371#endif
Michal Simekc1fd3122018-06-05 15:14:39 +0200372#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
373 U_BOOT_CMD_MKENT(loads, 6, 1, do_fpga_loads, "", ""),
374#endif
Michal Simek9933c362018-06-04 14:55:20 +0200375};
376
Simon Glassed38aef2020-05-10 11:40:03 -0600377static int do_fpga_wrapper(struct cmd_tbl *cmdtp, int flag, int argc,
Michal Simek9933c362018-06-04 14:55:20 +0200378 char *const argv[])
379{
Simon Glassed38aef2020-05-10 11:40:03 -0600380 struct cmd_tbl *fpga_cmd;
Michal Simek9933c362018-06-04 14:55:20 +0200381 int ret;
382
383 if (argc < 2)
384 return CMD_RET_USAGE;
385
386 fpga_cmd = find_cmd_tbl(argv[1], fpga_commands,
387 ARRAY_SIZE(fpga_commands));
Michal Simek9933c362018-06-04 14:55:20 +0200388 if (!fpga_cmd) {
389 debug("fpga: non existing command\n");
390 return CMD_RET_USAGE;
391 }
392
393 argc -= 2;
394 argv += 2;
395
396 if (argc > fpga_cmd->maxargs) {
397 debug("fpga: more parameters passed\n");
398 return CMD_RET_USAGE;
399 }
400
401 ret = fpga_cmd->cmd(fpga_cmd, flag, argc, argv);
402
403 return cmd_process_error(fpga_cmd, ret);
404}
405
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530406#if defined(CONFIG_CMD_FPGA_LOADFS) || defined(CONFIG_CMD_FPGA_LOAD_SECURE)
Michal Simek9933c362018-06-04 14:55:20 +0200407U_BOOT_CMD(fpga, 9, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530408#else
Michal Simek9933c362018-06-04 14:55:20 +0200409U_BOOT_CMD(fpga, 6, 1, do_fpga_wrapper,
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530410#endif
Michal Simeka888af72013-04-26 13:10:07 +0200411 "loadable FPGA image support",
412 "[operation type] [device number] [image address] [image size]\n"
413 "fpga operations:\n"
Michal Simek70da5922015-01-26 08:52:27 +0100414 " dump\t[dev] [address] [size]\tLoad device to memory buffer\n"
Michal Simeka888af72013-04-26 13:10:07 +0200415 " info\t[dev]\t\t\tlist known device information\n"
416 " load\t[dev] [address] [size]\tLoad device from memory buffer\n"
Michal Simek64c70982014-05-02 13:43:39 +0200417#if defined(CONFIG_CMD_FPGA_LOADP)
418 " loadp\t[dev] [address] [size]\t"
419 "Load device from memory buffer with partial bitstream\n"
420#endif
Michal Simeka888af72013-04-26 13:10:07 +0200421 " loadb\t[dev] [address] [size]\t"
422 "Load device from bitstream buffer (Xilinx only)\n"
Michal Simek64c70982014-05-02 13:43:39 +0200423#if defined(CONFIG_CMD_FPGA_LOADBP)
424 " loadbp\t[dev] [address] [size]\t"
425 "Load device from bitstream buffer with partial bitstream"
426 "(Xilinx only)\n"
427#endif
Siva Durga Prasad Paladugu9112b4c2014-03-14 16:35:37 +0530428#if defined(CONFIG_CMD_FPGA_LOADFS)
429 "Load device from filesystem (FAT by default) (Xilinx only)\n"
430 " loadfs [dev] [address] [image size] [blocksize] <interface>\n"
431 " [<dev[:part]>] <filename>\n"
432#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530433#if defined(CONFIG_CMD_FPGA_LOADMK)
Michal Simeka888af72013-04-26 13:10:07 +0200434 " loadmk [dev] [address]\tLoad device generated with mkimage"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100435#if defined(CONFIG_FIT)
Michal Simeka888af72013-04-26 13:10:07 +0200436 "\n"
437 "\tFor loadmk operating on FIT format uImage address must include\n"
438 "\tsubimage unit name in the form of addr:<subimg_uname>"
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100439#endif
Siva Durga Prasad Paladuguadc11de2014-03-14 16:35:38 +0530440#endif
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530441#if defined(CONFIG_CMD_FPGA_LOAD_SECURE)
442 "Load encrypted bitstream (Xilinx only)\n"
443 " loads [dev] [address] [size] [auth-OCM-0/DDR-1/noauth-2]\n"
444 " [enc-devkey(0)/userkey(1)/nenc(2) [Userkey address]\n"
445 "Loads the secure bistreams(authenticated/encrypted/both\n"
446 "authenticated and encrypted) of [size] from [address].\n"
447 "The auth-OCM/DDR flag specifies to perform authentication\n"
448 "in OCM or in DDR. 0 for OCM, 1 for DDR, 2 for no authentication.\n"
449 "The enc flag specifies which key to be used for decryption\n"
450 "0-device key, 1-user key, 2-no encryption.\n"
451 "The optional Userkey address specifies from which address key\n"
452 "has to be used for decryption if user key is selected.\n"
Robert P. J. Dayda625142019-05-28 11:33:27 -0400453 "NOTE: the secure bitstream has to be created using Xilinx\n"
Siva Durga Prasad Paladugucce0cb02018-05-31 15:10:22 +0530454 "bootgen tool only.\n"
455#endif
Marian Balakowiczd79162d2008-03-12 10:33:01 +0100456);