blob: 88d4d3cb9834e5decc43abe64a9d4948c27ee438 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Simon Glassf1eba352022-10-20 18:23:20 -060040 mmc2 = "/mmc2";
41 mmc3 = "/mmc3";
Bin Meng408e5902018-08-03 01:14:41 -070042 pci0 = &pci0;
43 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070044 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020045 remoteproc0 = &rproc_1;
46 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060047 rtc0 = &rtc_0;
48 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060049 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020050 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070051 testbus3 = "/some-bus";
52 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070053 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070054 testfdt3 = "/b-test";
55 testfdt5 = "/some-bus/c-test@5";
56 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070057 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020058 fdt-dummy0 = "/translation-test@8000/dev@0,0";
59 fdt-dummy1 = "/translation-test@8000/dev@1,100";
60 fdt-dummy2 = "/translation-test@8000/dev@2,200";
61 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060062 usb0 = &usb_0;
63 usb1 = &usb_1;
64 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020065 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020066 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060067 };
68
Simon Glass5e135d32022-10-20 18:23:15 -060069 binman: binman {
Philippe Reynes462d1632022-03-28 22:56:53 +020070 };
71
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020072 config {
Simon Glass0034d962021-08-07 07:24:01 -060073 testing-bool;
74 testing-int = <123>;
75 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020076 environment {
77 from_fdt = "yes";
78 fdt_env_path = "";
79 };
80 };
81
Simon Glassb255efc2022-04-24 23:31:24 -060082 bootstd {
Simon Glassa9289612022-10-20 18:23:14 -060083 u-boot,dm-vpl;
Simon Glassb255efc2022-04-24 23:31:24 -060084 compatible = "u-boot,boot-std";
85
86 filename-prefixes = "/", "/boot/";
87 bootdev-order = "mmc2", "mmc1";
88
89 syslinux {
90 compatible = "u-boot,distro-syslinux";
91 };
92
93 efi {
94 compatible = "u-boot,distro-efi";
95 };
Simon Glassa9289612022-10-20 18:23:14 -060096
Simon Glassd2bc33ed2023-01-06 08:52:41 -060097 theme {
98 font-size = <30>;
99 };
100
Simon Glassf1eba352022-10-20 18:23:20 -0600101 /*
102 * This is used for the VBE OS-request tests. A FAT filesystem
103 * created in a partition with the VBE information appearing
104 * before the parititon starts
105 */
Simon Glassa9289612022-10-20 18:23:14 -0600106 firmware0 {
107 u-boot,dm-vpl;
108 compatible = "fwupd,vbe-simple";
109 storage = "mmc1";
110 skip-offset = <0x200>;
111 area-start = <0x400>;
112 area-size = <0x1000>;
113 state-offset = <0x400>;
114 state-size = <0x40>;
115 version-offset = <0x800>;
116 version-size = <0x100>;
117 };
Simon Glassf1eba352022-10-20 18:23:20 -0600118
119 /*
120 * This is used for the VBE VPL tests. The MMC device holds the
121 * binman image.bin file. The test progresses through each phase
122 * of U-Boot, loading each in turn from MMC.
123 *
124 * Note that the test enables this node (and mmc3) before
125 * running U-Boot
126 */
127 firmware1 {
128 u-boot,dm-vpl;
129 status = "disabled";
130 compatible = "fwupd,vbe-simple";
131 storage = "mmc3";
132 skip-offset = <0x400000>;
133 area-start = <0>;
134 area-size = <0xe00000>;
135 state-offset = <0xdffc00>;
136 state-size = <0x40>;
137 version-offset = <0xdffe00>;
138 version-size = <0x100>;
139 };
Simon Glassb255efc2022-04-24 23:31:24 -0600140 };
141
Andrew Scull451b8b12022-05-30 10:00:12 +0000142 fuzzing-engine {
143 compatible = "sandbox,fuzzing-engine";
144 };
145
Nandor Han6521e5d2021-06-10 16:56:44 +0300146 reboot-mode0 {
147 compatible = "reboot-mode-gpio";
148 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
149 u-boot,env-variable = "bootstatus";
150 mode-test = <0x01>;
151 mode-download = <0x03>;
152 };
153
Nandor Han7e4067a2021-06-10 16:56:45 +0300154 reboot_mode1: reboot-mode@14 {
155 compatible = "reboot-mode-rtc";
156 rtc = <&rtc_0>;
157 reg = <0x30 4>;
158 u-boot,env-variable = "bootstatus";
159 big-endian;
160 mode-test = <0x21969147>;
161 mode-download = <0x51939147>;
162 };
163
Simon Glassed96cde2018-12-10 10:37:33 -0700164 audio: audio-codec {
165 compatible = "sandbox,audio-codec";
166 #sound-dai-cells = <1>;
167 };
168
Philippe Reynes1ee26482020-07-24 18:19:51 +0200169 buttons {
170 compatible = "gpio-keys";
171
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200172 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200173 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200174 label = "button1";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300175 linux,code = <BTN_1>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200176 };
177
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200178 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200179 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200180 label = "button2";
Dzmitry Sankouski157f2c52023-01-22 18:21:24 +0300181 linux,code = <BTN_2>;
Philippe Reynes1ee26482020-07-24 18:19:51 +0200182 };
183 };
184
Marek Szyprowskiad398592021-02-18 11:33:18 +0100185 buttons2 {
186 compatible = "adc-keys";
187 io-channels = <&adc 3>;
188 keyup-threshold-microvolt = <3000000>;
189
190 button-up {
191 label = "button3";
192 linux,code = <KEY_F3>;
193 press-threshold-microvolt = <1500000>;
194 };
195
196 button-down {
197 label = "button4";
198 linux,code = <KEY_F4>;
199 press-threshold-microvolt = <1000000>;
200 };
201
202 button-enter {
203 label = "button5";
204 linux,code = <KEY_F5>;
205 press-threshold-microvolt = <500000>;
206 };
207 };
208
Simon Glassc953aaf2018-12-10 10:37:34 -0700209 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600210 reg = <0 0>;
211 compatible = "google,cros-ec-sandbox";
212
213 /*
214 * This describes the flash memory within the EC. Note
215 * that the STM32L flash erases to 0, not 0xff.
216 */
217 flash {
218 image-pos = <0x08000000>;
219 size = <0x20000>;
220 erase-value = <0>;
221
222 /* Information for sandbox */
223 ro {
224 image-pos = <0>;
225 size = <0xf000>;
226 };
227 wp-ro {
228 image-pos = <0xf000>;
229 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700230 used = <0x884>;
231 compress = "lz4";
232 uncomp-size = <0xcf8>;
233 hash {
234 algo = "sha256";
235 value = [00 01 02 03 04 05 06 07
236 08 09 0a 0b 0c 0d 0e 0f
237 10 11 12 13 14 15 16 17
238 18 19 1a 1b 1c 1d 1e 1f];
239 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600240 };
241 rw {
242 image-pos = <0x10000>;
243 size = <0x10000>;
244 };
245 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300246
247 cros_ec_pwm: cros-ec-pwm {
248 compatible = "google,cros-ec-pwm";
249 #pwm-cells = <1>;
250 };
251
Simon Glass699c9ca2018-10-01 12:22:08 -0600252 };
253
Yannick Fertré9712c822019-10-07 15:29:05 +0200254 dsi_host: dsi_host {
255 compatible = "sandbox,dsi-host";
256 };
257
Simon Glassb2c1cac2014-02-26 15:59:21 -0700258 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600259 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700260 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600261 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700262 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600263 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100264 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
265 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700266 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100267 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
268 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
269 <&gpio_b 7 GPIO_IN 3 2 1>,
270 <&gpio_b 8 GPIO_OUT 3 2 1>,
271 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100272 test3-gpios =
273 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
274 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
275 <&gpio_c 2 GPIO_OUT>,
276 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
277 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200278 <&gpio_c 5 GPIO_IN>,
279 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
280 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530281 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
282 test5-gpios = <&gpio_a 19>;
283
Simon Glass73025392021-10-23 17:26:04 -0600284 bool-value;
Stefan Herbrechtsmeier1b090e62022-06-14 15:21:30 +0200285 int8-value = /bits/ 8 <0x12>;
286 int16-value = /bits/ 16 <0x1234>;
Simon Glass6df01f92018-12-10 10:37:37 -0700287 int-value = <1234>;
288 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200289 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200290 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600291 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700292 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600293 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200294 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530295
296 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
297 <&muxcontroller0 2>, <&muxcontroller0 3>,
298 <&muxcontroller1>;
299 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
300 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100301 display-timings {
302 timing0: 240x320 {
303 clock-frequency = <6500000>;
304 hactive = <240>;
305 vactive = <320>;
306 hfront-porch = <6>;
307 hback-porch = <7>;
308 hsync-len = <1>;
309 vback-porch = <5>;
310 vfront-porch = <8>;
311 vsync-len = <2>;
312 hsync-active = <1>;
313 vsync-active = <0>;
314 de-active = <1>;
315 pixelclk-active = <1>;
316 interlaced;
317 doublescan;
318 doubleclk;
319 };
320 timing1: 480x800 {
321 clock-frequency = <9000000>;
322 hactive = <480>;
323 vactive = <800>;
324 hfront-porch = <10>;
325 hback-porch = <59>;
326 hsync-len = <12>;
327 vback-porch = <15>;
328 vfront-porch = <17>;
329 vsync-len = <16>;
330 hsync-active = <0>;
331 vsync-active = <1>;
332 de-active = <0>;
333 pixelclk-active = <0>;
334 };
335 timing2: 800x480 {
336 clock-frequency = <33500000>;
337 hactive = <800>;
338 vactive = <480>;
339 hback-porch = <89>;
340 hfront-porch = <164>;
341 vback-porch = <23>;
342 vfront-porch = <10>;
343 hsync-len = <11>;
344 vsync-len = <13>;
345 };
346 };
Nikhil M Jainbb9d1312023-01-31 15:35:15 +0530347 panel-timings {
348 clock-frequency = <6500000>;
349 hactive = <240>;
350 vactive = <320>;
351 hfront-porch = <6>;
352 hback-porch = <7>;
353 hsync-len = <1>;
354 vback-porch = <5>;
355 vfront-porch = <8>;
356 vsync-len = <2>;
357 hsync-active = <1>;
358 vsync-active = <0>;
359 de-active = <1>;
360 pixelclk-active = <1>;
361 interlaced;
362 doublescan;
363 doubleclk;
364 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700365 };
366
367 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600368 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700369 compatible = "not,compatible";
370 };
371
372 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600373 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700374 };
375
Simon Glass5620cf82018-10-01 12:22:40 -0600376 backlight: backlight {
377 compatible = "pwm-backlight";
378 enable-gpios = <&gpio_a 1>;
379 power-supply = <&ldo_1>;
380 pwms = <&pwm 0 1000>;
381 default-brightness-level = <5>;
382 brightness-levels = <0 16 32 64 128 170 202 234 255>;
383 };
384
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200385 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200386 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200387 bind-test-child1 {
388 compatible = "sandbox,phy";
389 #phy-cells = <1>;
390 };
391
392 bind-test-child2 {
393 compatible = "simple-bus";
394 };
395 };
396
Simon Glassb2c1cac2014-02-26 15:59:21 -0700397 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600398 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700399 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600400 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700401 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530402
403 mux-controls = <&muxcontroller0 0>;
404 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700405 };
406
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200407 phy_provider0: gen_phy@0 {
408 compatible = "sandbox,phy";
409 #phy-cells = <1>;
410 };
411
412 phy_provider1: gen_phy@1 {
413 compatible = "sandbox,phy";
414 #phy-cells = <0>;
415 broken;
416 };
417
developer71092972020-05-02 11:35:12 +0200418 phy_provider2: gen_phy@2 {
419 compatible = "sandbox,phy";
420 #phy-cells = <0>;
421 };
422
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200423 gen_phy_user: gen_phy_user {
424 compatible = "simple-bus";
425 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
426 phy-names = "phy1", "phy2", "phy3";
427 };
428
developer71092972020-05-02 11:35:12 +0200429 gen_phy_user1: gen_phy_user1 {
430 compatible = "simple-bus";
431 phys = <&phy_provider0 0>, <&phy_provider2>;
432 phy-names = "phy1", "phy2";
433 };
434
Simon Glassb2c1cac2014-02-26 15:59:21 -0700435 some-bus {
436 #address-cells = <1>;
437 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600438 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600439 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600440 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700441 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600442 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700443 compatible = "denx,u-boot-fdt-test";
444 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600445 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700446 ping-add = <5>;
447 };
Simon Glass40717422014-07-23 06:55:18 -0600448 c-test@0 {
449 compatible = "denx,u-boot-fdt-test";
450 reg = <0>;
451 ping-expect = <6>;
452 ping-add = <6>;
453 };
454 c-test@1 {
455 compatible = "denx,u-boot-fdt-test";
456 reg = <1>;
457 ping-expect = <7>;
458 ping-add = <7>;
459 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700460 };
461
462 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600463 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600464 ping-expect = <6>;
465 ping-add = <6>;
466 compatible = "google,another-fdt-test";
467 };
468
469 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600470 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600471 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700472 ping-add = <6>;
473 compatible = "google,another-fdt-test";
474 };
475
Simon Glass0ccb0972015-01-25 08:27:05 -0700476 f-test {
477 compatible = "denx,u-boot-fdt-test";
478 };
479
480 g-test {
481 compatible = "denx,u-boot-fdt-test";
482 };
483
Bin Mengd9d24782018-10-10 22:07:01 -0700484 h-test {
485 compatible = "denx,u-boot-fdt-test1";
486 };
487
developercf8bc132020-05-02 11:35:10 +0200488 i-test {
489 compatible = "mediatek,u-boot-fdt-test";
490 #address-cells = <1>;
491 #size-cells = <0>;
492
493 subnode@0 {
494 reg = <0>;
495 };
496
497 subnode@1 {
498 reg = <1>;
499 };
500
501 subnode@2 {
502 reg = <2>;
503 };
504 };
505
Simon Glass204675c2019-12-29 21:19:25 -0700506 devres-test {
507 compatible = "denx,u-boot-devres-test";
508 };
509
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530510 another-test {
511 reg = <0 2>;
512 compatible = "denx,u-boot-fdt-test";
513 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
514 test5-gpios = <&gpio_a 19>;
515 };
516
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100517 mmio-bus@0 {
518 #address-cells = <1>;
519 #size-cells = <1>;
520 compatible = "denx,u-boot-test-bus";
521 dma-ranges = <0x10000000 0x00000000 0x00040000>;
522
523 subnode@0 {
524 compatible = "denx,u-boot-fdt-test";
525 };
526 };
527
528 mmio-bus@1 {
529 #address-cells = <1>;
530 #size-cells = <1>;
531 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100532
533 subnode@0 {
534 compatible = "denx,u-boot-fdt-test";
535 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100536 };
537
Simon Glass3c601b12020-07-07 13:12:06 -0600538 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600539 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600540 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600541 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600542 child {
543 compatible = "denx,u-boot-acpi-test";
544 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600545 };
546
Simon Glass3c601b12020-07-07 13:12:06 -0600547 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600548 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600549 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600550 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600551 };
552
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200553 clocks {
554 clk_fixed: clk-fixed {
555 compatible = "fixed-clock";
556 #clock-cells = <0>;
557 clock-frequency = <1234>;
558 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000559
560 clk_fixed_factor: clk-fixed-factor {
561 compatible = "fixed-factor-clock";
562 #clock-cells = <0>;
563 clock-div = <3>;
564 clock-mult = <2>;
565 clocks = <&clk_fixed>;
566 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200567
568 osc {
569 compatible = "fixed-clock";
570 #clock-cells = <0>;
571 clock-frequency = <20000000>;
572 };
Stephen Warrena9622432016-06-17 09:44:00 -0600573 };
574
575 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600576 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600577 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200578 assigned-clocks = <&clk_sandbox 3>;
579 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600580 };
581
582 clk-test {
583 compatible = "sandbox,clk-test";
584 clocks = <&clk_fixed>,
585 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200586 <&clk_sandbox 0>,
587 <&clk_sandbox 3>,
588 <&clk_sandbox 2>;
589 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600590 };
591
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200592 ccf: clk-ccf {
593 compatible = "sandbox,clk-ccf";
594 };
595
Simon Glass507ab962021-12-04 08:56:31 -0700596 efi-media {
597 compatible = "sandbox,efi-media";
598 };
599
Simon Glass5b968632015-05-22 15:42:15 -0600600 eth@10002000 {
601 compatible = "sandbox,eth";
602 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600603 };
604
605 eth_5: eth@10003000 {
606 compatible = "sandbox,eth";
607 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400608 nvmem-cells = <&eth5_addr>;
609 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600610 };
611
Bin Meng04a11cb2015-08-27 22:25:53 -0700612 eth_3: sbe5 {
613 compatible = "sandbox,eth";
614 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400615 nvmem-cells = <&eth3_addr>;
616 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700617 };
618
Simon Glass5b968632015-05-22 15:42:15 -0600619 eth@10004000 {
620 compatible = "sandbox,eth";
621 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600622 };
623
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200624 phy_eth0: phy-test-eth {
625 compatible = "sandbox,eth";
626 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400627 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200628 phy-handle = <&ethphy1>;
Marek BehĂșnbc194772022-04-07 00:33:01 +0200629 phy-mode = "2500base-x";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200630 };
631
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800632 dsa_eth0: dsa-test-eth {
633 compatible = "sandbox,eth";
634 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400635 nvmem-cells = <&eth4_addr>;
636 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800637 };
638
639 dsa-test {
640 compatible = "sandbox,dsa";
641
642 ports {
643 #address-cells = <1>;
644 #size-cells = <0>;
645 swp_0: port@0 {
646 reg = <0>;
647 label = "lan0";
648 phy-mode = "rgmii-rxid";
649
650 fixed-link {
651 speed = <100>;
652 full-duplex;
653 };
654 };
655
656 swp_1: port@1 {
657 reg = <1>;
658 label = "lan1";
659 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800660 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800661 };
662
663 port@2 {
664 reg = <2>;
665 ethernet = <&dsa_eth0>;
666
667 fixed-link {
668 speed = <1000>;
669 full-duplex;
670 };
671 };
672 };
673 };
674
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700675 firmware {
676 sandbox_firmware: sandbox-firmware {
677 compatible = "sandbox,firmware";
678 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200679
Etienne Carriere09665cb2022-02-21 09:22:39 +0100680 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200681 compatible = "sandbox,scmi-agent";
682 #address-cells = <1>;
683 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200684
Etienne Carriere09665cb2022-02-21 09:22:39 +0100685 protocol@10 {
686 reg = <0x10>;
687 };
688
689 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200690 reg = <0x14>;
691 #clock-cells = <1>;
692 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200693
Etienne Carriere09665cb2022-02-21 09:22:39 +0100694 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200695 reg = <0x16>;
696 #reset-cells = <1>;
697 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100698
699 protocol@17 {
700 reg = <0x17>;
701
702 regulators {
703 #address-cells = <1>;
704 #size-cells = <0>;
705
Etienne Carriere09665cb2022-02-21 09:22:39 +0100706 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100707 reg = <0>;
708 regulator-name = "sandbox-voltd0";
709 regulator-min-microvolt = <1100000>;
710 regulator-max-microvolt = <3300000>;
711 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100712 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100713 reg = <0x1>;
714 regulator-name = "sandbox-voltd1";
715 regulator-min-microvolt = <1800000>;
716 };
717 };
718 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200719 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700720 };
721
Alexander Dahl6ac319d2022-09-30 14:04:30 +0200722 fpga {
723 compatible = "sandbox,fpga";
724 };
725
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100726 pinctrl-gpio {
727 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700728
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100729 gpio_a: base-gpios {
730 compatible = "sandbox,gpio";
731 gpio-controller;
732 #gpio-cells = <1>;
733 gpio-bank-name = "a";
734 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200735 hog_input_active_low {
736 gpio-hog;
737 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200738 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200739 };
740 hog_input_active_high {
741 gpio-hog;
742 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200743 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200744 };
745 hog_output_low {
746 gpio-hog;
747 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200748 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200749 };
750 hog_output_high {
751 gpio-hog;
752 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200753 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200754 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100755 };
756
757 gpio_b: extra-gpios {
758 compatible = "sandbox,gpio";
759 gpio-controller;
760 #gpio-cells = <5>;
761 gpio-bank-name = "b";
762 sandbox,gpio-count = <10>;
763 };
Simon Glass25348a42014-10-13 23:42:11 -0600764
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100765 gpio_c: pinmux-gpios {
766 compatible = "sandbox,gpio";
767 gpio-controller;
768 #gpio-cells = <2>;
769 gpio-bank-name = "c";
770 sandbox,gpio-count = <10>;
771 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100772 };
773
Simon Glass7df766e2014-12-10 08:55:55 -0700774 i2c@0 {
775 #address-cells = <1>;
776 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600777 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700778 compatible = "sandbox,i2c";
779 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200780 pinctrl-names = "default";
781 pinctrl-0 = <&pinmux_i2c0_pins>;
782
Simon Glass7df766e2014-12-10 08:55:55 -0700783 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400784 #address-cells = <1>;
785 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700786 reg = <0x2c>;
787 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700788 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200789 partitions {
790 compatible = "fixed-partitions";
791 #address-cells = <1>;
792 #size-cells = <1>;
793 bootcount_i2c: bootcount@10 {
794 reg = <10 2>;
795 };
796 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400797
798 eth3_addr: mac-address@24 {
799 reg = <24 6>;
800 };
Simon Glass7df766e2014-12-10 08:55:55 -0700801 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200802
Simon Glass336b2952015-05-22 15:42:17 -0600803 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400804 #address-cells = <1>;
805 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600806 reg = <0x43>;
807 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700808 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400809
810 eth4_addr: mac-address@40 {
811 reg = <0x40 6>;
812 };
Simon Glass336b2952015-05-22 15:42:17 -0600813 };
814
815 rtc_1: rtc@61 {
816 reg = <0x61>;
817 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700818 sandbox,emul = <&emul1>;
819 };
820
821 i2c_emul: emul {
822 reg = <0xff>;
823 compatible = "sandbox,i2c-emul-parent";
824 emul_eeprom: emul-eeprom {
825 compatible = "sandbox,i2c-eeprom";
826 sandbox,filename = "i2c.bin";
827 sandbox,size = <256>;
828 };
829 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700830 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700831 };
832 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700833 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600834 };
835 };
836
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200837 sandbox_pmic: sandbox_pmic {
838 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700839 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200840 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200841
842 mc34708: pmic@41 {
843 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700844 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200845 };
Simon Glass7df766e2014-12-10 08:55:55 -0700846 };
847
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100848 bootcount@0 {
849 compatible = "u-boot,bootcount-rtc";
850 rtc = <&rtc_1>;
851 offset = <0x13>;
852 };
853
Michal Simek4f18f922020-05-28 11:48:55 +0200854 bootcount {
855 compatible = "u-boot,bootcount-i2c-eeprom";
856 i2c-eeprom = <&bootcount_i2c>;
857 };
858
Nandor Han88895812021-06-10 15:40:38 +0300859 bootcount_4@0 {
860 compatible = "u-boot,bootcount-syscon";
861 syscon = <&syscon0>;
862 reg = <0x0 0x04>, <0x0 0x04>;
863 reg-names = "syscon_reg", "offset";
864 };
865
866 bootcount_2@0 {
867 compatible = "u-boot,bootcount-syscon";
868 syscon = <&syscon0>;
869 reg = <0x0 0x04>, <0x0 0x02> ;
870 reg-names = "syscon_reg", "offset";
871 };
872
Marek Szyprowskiad398592021-02-18 11:33:18 +0100873 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100874 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100875 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100876 vdd-supply = <&buck2>;
877 vss-microvolts = <0>;
878 };
879
Mark Kettenis67748ee2021-10-23 16:58:02 +0200880 iommu: iommu@0 {
881 compatible = "sandbox,iommu";
882 #iommu-cells = <0>;
883 };
884
Simon Glass515dcff2020-02-06 09:55:00 -0700885 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700886 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700887 interrupt-controller;
888 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700889 };
890
Simon Glass90b6fef2016-01-18 19:52:26 -0700891 lcd {
892 u-boot,dm-pre-reloc;
893 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200894 pinctrl-names = "default";
895 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700896 xres = <1366>;
897 yres = <768>;
898 };
899
Simon Glassd783eb32015-07-06 12:54:34 -0600900 leds {
901 compatible = "gpio-leds";
902
903 iracibble {
904 gpios = <&gpio_a 1 0>;
905 label = "sandbox:red";
906 };
907
908 martinet {
909 gpios = <&gpio_a 2 0>;
910 label = "sandbox:green";
911 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200912
913 default_on {
914 gpios = <&gpio_a 5 0>;
915 label = "sandbox:default_on";
916 default-state = "on";
917 };
918
919 default_off {
920 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400921 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200922 default-state = "off";
923 };
Simon Glassd783eb32015-07-06 12:54:34 -0600924 };
925
Paul Doelle709f0372022-07-04 09:00:25 +0000926 wdt-gpio-toggle {
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200927 gpios = <&gpio_a 7 0>;
928 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200929 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +0000930 hw_algo = "toggle";
931 always-running;
932 };
933
934 wdt-gpio-level {
935 gpios = <&gpio_a 7 0>;
936 compatible = "linux,wdt-gpio";
937 hw_margin_ms = <100>;
938 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200939 always-running;
940 };
941
Stephen Warren62f2c902016-05-16 17:41:37 -0600942 mbox: mbox {
943 compatible = "sandbox,mbox";
944 #mbox-cells = <1>;
945 };
946
947 mbox-test {
948 compatible = "sandbox,mbox-test";
949 mboxes = <&mbox 100>, <&mbox 1>;
950 mbox-names = "other", "test";
951 };
952
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900953 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200954 #address-cells = <1>;
955 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400956 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200957 cpu1: cpu@1 {
958 device_type = "cpu";
959 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400960 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900961 compatible = "sandbox,cpu_sandbox";
962 u-boot,dm-pre-reloc;
963 };
Mario Sixdea5df72018-08-06 10:23:44 +0200964
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200965 cpu2: cpu@2 {
966 device_type = "cpu";
967 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900968 compatible = "sandbox,cpu_sandbox";
969 u-boot,dm-pre-reloc;
970 };
Mario Sixdea5df72018-08-06 10:23:44 +0200971
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200972 cpu3: cpu@3 {
973 device_type = "cpu";
974 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900975 compatible = "sandbox,cpu_sandbox";
976 u-boot,dm-pre-reloc;
977 };
Mario Sixdea5df72018-08-06 10:23:44 +0200978 };
979
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500980 chipid: chipid {
981 compatible = "sandbox,soc";
982 };
983
Simon Glassc953aaf2018-12-10 10:37:34 -0700984 i2s: i2s {
985 compatible = "sandbox,i2s";
986 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700987 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700988 };
989
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200990 nop-test_0 {
991 compatible = "sandbox,nop_sandbox1";
992 nop-test_1 {
993 compatible = "sandbox,nop_sandbox2";
994 bind = "True";
995 };
996 nop-test_2 {
997 compatible = "sandbox,nop_sandbox2";
998 bind = "False";
999 };
1000 };
1001
Roger Quadrosb0679a72022-10-20 16:30:46 +03001002 memory-controller {
1003 compatible = "sandbox,memory";
1004 };
1005
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001006 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -04001007 #address-cells = <1>;
1008 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001009 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -04001010
1011 eth5_addr: mac-address@10 {
1012 reg = <0x10 6>;
1013 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +02001014 };
1015
Simon Glasse4fef742017-04-23 20:02:07 -06001016 mmc2 {
1017 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -06001018 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -06001019 };
1020
Simon Glassb255efc2022-04-24 23:31:24 -06001021 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -06001022 mmc1 {
1023 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -06001024 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -06001025 };
1026
Simon Glassb255efc2022-04-24 23:31:24 -06001027 /* This is used for the fastboot tests */
Sughosh Ganu77079e72022-10-21 18:16:05 +05301028 mmc0: mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -06001029 compatible = "sandbox,mmc";
1030 };
1031
Simon Glassf1eba352022-10-20 18:23:20 -06001032 /* This is used for VBE VPL tests */
1033 mmc3 {
1034 status = "disabled";
1035 compatible = "sandbox,mmc";
1036 filename = "image.bin";
1037 non-removable;
1038 };
1039
Simon Glassd2bc33ed2023-01-06 08:52:41 -06001040 /* This is used for bootstd bootmenu tests */
1041 mmc4 {
1042 status = "disabled";
1043 compatible = "sandbox,mmc";
1044 filename = "mmc4.img";
1045 };
1046
Simon Glass53a68b32019-02-16 20:24:50 -07001047 pch {
1048 compatible = "sandbox,pch";
1049 };
1050
Tom Rini4a3ca482020-02-11 12:41:23 -05001051 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -07001052 compatible = "sandbox,pci";
1053 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001054 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001055 #address-cells = <3>;
1056 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -06001057 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -07001058 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Mark Kettenis5dfd4ec2023-01-21 20:27:57 +01001059 iommu-map = <0x0010 &iommu 0 1>;
1060 iommu-map-mask = <0xfffffff8>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001061 pci@0,0 {
1062 compatible = "pci-generic";
1063 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001064 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -07001065 };
Alex Margineanf1274432019-06-07 11:24:24 +03001066 pci@1,0 {
1067 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001068 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
1069 reg = <0x02000814 0 0 0 0
1070 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001071 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +03001072 };
Simon Glass937bb472019-12-06 21:41:57 -07001073 p2sb-pci@2,0 {
1074 compatible = "sandbox,p2sb";
1075 reg = <0x02001010 0 0 0 0>;
1076 sandbox,emul = <&p2sb_emul>;
1077
1078 adder {
1079 intel,p2sb-port-id = <3>;
1080 compatible = "sandbox,adder";
1081 };
1082 };
Simon Glass8c501022019-12-06 21:41:54 -07001083 pci@1e,0 {
1084 compatible = "sandbox,pmc";
1085 reg = <0xf000 0 0 0 0>;
1086 sandbox,emul = <&pmc_emul1e>;
1087 acpi-base = <0x400>;
1088 gpe0-dwx-mask = <0xf>;
1089 gpe0-dwx-shift-base = <4>;
1090 gpe0-dw = <6 7 9>;
1091 gpe0-sts = <0x20>;
1092 gpe0-en = <0x30>;
1093 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001094 pci@1f,0 {
1095 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001096 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1097 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001098 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001099 };
1100 };
1101
Simon Glassb98ba4c2019-09-25 08:56:10 -06001102 pci-emul0 {
1103 compatible = "sandbox,pci-emul-parent";
1104 swap_case_emul0_0: emul0@0,0 {
1105 compatible = "sandbox,swap-case";
1106 };
1107 swap_case_emul0_1: emul0@1,0 {
1108 compatible = "sandbox,swap-case";
1109 use-ea;
1110 };
1111 swap_case_emul0_1f: emul0@1f,0 {
1112 compatible = "sandbox,swap-case";
1113 };
Simon Glass937bb472019-12-06 21:41:57 -07001114 p2sb_emul: emul@2,0 {
1115 compatible = "sandbox,p2sb-emul";
1116 };
Simon Glass8c501022019-12-06 21:41:54 -07001117 pmc_emul1e: emul@1e,0 {
1118 compatible = "sandbox,pmc-emul";
1119 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001120 };
1121
Tom Rini4a3ca482020-02-11 12:41:23 -05001122 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001123 compatible = "sandbox,pci";
1124 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001125 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001126 #address-cells = <3>;
1127 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001128 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001129 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001130 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001131 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001132 0x0c 0x00 0x1234 0x5678
1133 0x10 0x00 0x1234 0x5678>;
1134 pci@10,0 {
1135 reg = <0x8000 0 0 0 0>;
1136 };
Bin Meng408e5902018-08-03 01:14:41 -07001137 };
1138
Tom Rini4a3ca482020-02-11 12:41:23 -05001139 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001140 compatible = "sandbox,pci";
1141 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001142 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001143 #address-cells = <3>;
1144 #size-cells = <2>;
1145 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1146 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1147 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1148 pci@1f,0 {
1149 compatible = "pci-generic";
1150 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001151 sandbox,emul = <&swap_case_emul2_1f>;
1152 };
1153 };
1154
1155 pci-emul2 {
1156 compatible = "sandbox,pci-emul-parent";
1157 swap_case_emul2_1f: emul2@1f,0 {
1158 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001159 };
1160 };
1161
Ramon Friedc64f19b2019-04-27 11:15:23 +03001162 pci_ep: pci_ep {
1163 compatible = "sandbox,pci_ep";
1164 };
1165
Simon Glass9c433fe2017-04-23 20:10:44 -06001166 probing {
1167 compatible = "simple-bus";
1168 test1 {
1169 compatible = "denx,u-boot-probe-test";
1170 };
1171
1172 test2 {
1173 compatible = "denx,u-boot-probe-test";
1174 };
1175
1176 test3 {
1177 compatible = "denx,u-boot-probe-test";
1178 };
1179
1180 test4 {
1181 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001182 first-syscon = <&syscon0>;
1183 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001184 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001185 };
1186 };
1187
Stephen Warren92c67fa2016-07-13 13:45:31 -06001188 pwrdom: power-domain {
1189 compatible = "sandbox,power-domain";
1190 #power-domain-cells = <1>;
1191 };
1192
1193 power-domain-test {
1194 compatible = "sandbox,power-domain-test";
1195 power-domains = <&pwrdom 2>;
1196 };
1197
Simon Glass5620cf82018-10-01 12:22:40 -06001198 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001199 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001200 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001201 pinctrl-names = "default";
1202 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001203 };
1204
1205 pwm2 {
1206 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001207 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001208 };
1209
Simon Glass3d355e62015-07-06 12:54:31 -06001210 ram {
1211 compatible = "sandbox,ram";
1212 };
1213
Simon Glassd860f222015-07-06 12:54:29 -06001214 reset@0 {
1215 compatible = "sandbox,warm-reset";
Michal Suchanek76874302022-10-10 20:29:39 +02001216 u-boot,dm-pre-proper;
Simon Glassd860f222015-07-06 12:54:29 -06001217 };
1218
1219 reset@1 {
1220 compatible = "sandbox,reset";
Michal Suchanek76874302022-10-10 20:29:39 +02001221 u-boot,dm-pre-proper;
Simon Glassd860f222015-07-06 12:54:29 -06001222 };
1223
Stephen Warren6488e642016-06-17 09:43:59 -06001224 resetc: reset-ctl {
1225 compatible = "sandbox,reset-ctl";
1226 #reset-cells = <1>;
1227 };
1228
1229 reset-ctl-test {
1230 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001231 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1232 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001233 };
1234
Sughosh Ganu23e37512019-12-28 23:58:31 +05301235 rng {
1236 compatible = "sandbox,sandbox-rng";
1237 };
1238
Nishanth Menonedf85812015-09-17 15:42:41 -05001239 rproc_1: rproc@1 {
1240 compatible = "sandbox,test-processor";
1241 remoteproc-name = "remoteproc-test-dev1";
1242 };
1243
1244 rproc_2: rproc@2 {
1245 compatible = "sandbox,test-processor";
1246 internal-memory-mapped;
1247 remoteproc-name = "remoteproc-test-dev2";
1248 };
1249
Simon Glass5620cf82018-10-01 12:22:40 -06001250 panel {
1251 compatible = "simple-panel";
1252 backlight = <&backlight 0 100>;
1253 };
1254
Simon Glass509f32e2022-09-21 16:21:47 +02001255 scsi {
1256 compatible = "sandbox,scsi";
1257 sandbox,filepath = "scsi.img";
1258 };
1259
Ramon Fried26ed32e2018-07-02 02:57:59 +03001260 smem@0 {
1261 compatible = "sandbox,smem";
1262 };
1263
Simon Glass76072ac2018-12-10 10:37:36 -07001264 sound {
1265 compatible = "sandbox,sound";
1266 cpu {
1267 sound-dai = <&i2s 0>;
1268 };
1269
1270 codec {
1271 sound-dai = <&audio 0>;
1272 };
1273 };
1274
Simon Glass25348a42014-10-13 23:42:11 -06001275 spi@0 {
1276 #address-cells = <1>;
1277 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001278 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001279 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001280 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001281 pinctrl-names = "default";
1282 pinctrl-0 = <&pinmux_spi0_pins>;
1283
Simon Glass25348a42014-10-13 23:42:11 -06001284 spi.bin@0 {
1285 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001286 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001287 spi-max-frequency = <40000000>;
1288 sandbox,filename = "spi.bin";
1289 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001290 spi.bin@1 {
1291 reg = <1>;
1292 compatible = "spansion,m25p16", "jedec,spi-nor";
1293 spi-max-frequency = <50000000>;
1294 sandbox,filename = "spi.bin";
1295 spi-cpol;
1296 spi-cpha;
1297 };
Simon Glass25348a42014-10-13 23:42:11 -06001298 };
1299
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001300 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001301 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001302 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001303 };
1304
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001305 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001306 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001307 reg = <0x20 5
1308 0x28 6
1309 0x30 7
1310 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001311 };
1312
Patrick Delaunayee010432019-03-07 09:57:13 +01001313 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001314 compatible = "simple-mfd", "syscon";
1315 reg = <0x40 5
1316 0x48 6
1317 0x50 7
1318 0x58 8>;
1319 };
1320
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301321 syscon3: syscon@3 {
1322 compatible = "simple-mfd", "syscon";
1323 reg = <0x000100 0x10>;
1324
1325 muxcontroller0: a-mux-controller {
1326 compatible = "mmio-mux";
1327 #mux-control-cells = <1>;
1328
1329 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1330 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1331 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1332 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1333 u-boot,mux-autoprobe;
1334 };
1335 };
1336
1337 muxcontroller1: emul-mux-controller {
1338 compatible = "mux-emul";
1339 #mux-control-cells = <0>;
1340 u-boot,mux-autoprobe;
1341 idle-state = <0xabcd>;
1342 };
1343
Simon Glass791a17f2020-12-16 21:20:27 -07001344 testfdtm0 {
1345 compatible = "denx,u-boot-fdtm-test";
1346 };
1347
1348 testfdtm1: testfdtm1 {
1349 compatible = "denx,u-boot-fdtm-test";
1350 };
1351
1352 testfdtm2 {
1353 compatible = "denx,u-boot-fdtm-test";
1354 };
1355
Sean Anderson79d3bba2020-09-28 10:52:23 -04001356 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001357 compatible = "sandbox,timer";
1358 clock-frequency = <1000000>;
1359 };
1360
Sean Anderson79d3bba2020-09-28 10:52:23 -04001361 timer@1 {
1362 compatible = "sandbox,timer";
1363 sandbox,timebase-frequency-fallback;
1364 };
1365
Miquel Raynal80938c12018-05-15 11:57:27 +02001366 tpm2 {
1367 compatible = "sandbox,tpm2";
1368 };
1369
Simon Glass5b968632015-05-22 15:42:15 -06001370 uart0: serial {
1371 compatible = "sandbox,serial";
1372 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001373 pinctrl-names = "default";
1374 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001375 };
1376
Simon Glass31680482015-03-25 12:23:05 -06001377 usb_0: usb@0 {
1378 compatible = "sandbox,usb";
1379 status = "disabled";
1380 hub {
1381 compatible = "sandbox,usb-hub";
1382 #address-cells = <1>;
1383 #size-cells = <0>;
1384 flash-stick {
1385 reg = <0>;
1386 compatible = "sandbox,usb-flash";
1387 };
1388 };
1389 };
1390
1391 usb_1: usb@1 {
1392 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001393 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001394 hub {
1395 compatible = "usb-hub";
1396 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001397 #address-cells = <1>;
1398 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001399 hub-emul {
1400 compatible = "sandbox,usb-hub";
1401 #address-cells = <1>;
1402 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001403 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001404 reg = <0>;
1405 compatible = "sandbox,usb-flash";
1406 sandbox,filepath = "testflash.bin";
1407 };
1408
Simon Glass4700fe52015-11-08 23:48:01 -07001409 flash-stick@1 {
1410 reg = <1>;
1411 compatible = "sandbox,usb-flash";
1412 sandbox,filepath = "testflash1.bin";
1413 };
1414
1415 flash-stick@2 {
1416 reg = <2>;
1417 compatible = "sandbox,usb-flash";
1418 sandbox,filepath = "testflash2.bin";
1419 };
1420
Simon Glassc0ccc722015-11-08 23:48:08 -07001421 keyb@3 {
1422 reg = <3>;
1423 compatible = "sandbox,usb-keyb";
1424 };
1425
Simon Glass31680482015-03-25 12:23:05 -06001426 };
Michael Walle7c961322020-06-02 01:47:07 +02001427
1428 usbstor@1 {
1429 reg = <1>;
1430 };
1431 usbstor@3 {
1432 reg = <3>;
1433 };
Simon Glass31680482015-03-25 12:23:05 -06001434 };
1435 };
1436
1437 usb_2: usb@2 {
1438 compatible = "sandbox,usb";
1439 status = "disabled";
1440 };
1441
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001442 spmi: spmi@0 {
1443 compatible = "sandbox,spmi";
1444 #address-cells = <0x1>;
1445 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001446 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001447 pm8916@0 {
1448 compatible = "qcom,spmi-pmic";
1449 reg = <0x0 0x1>;
1450 #address-cells = <0x1>;
1451 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001452 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001453
1454 spmi_gpios: gpios@c000 {
1455 compatible = "qcom,pm8916-gpio";
1456 reg = <0xc000 0x400>;
1457 gpio-controller;
1458 gpio-count = <4>;
1459 #gpio-cells = <2>;
1460 gpio-bank-name="spmi";
1461 };
1462 };
1463 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001464
1465 wdt0: wdt@0 {
1466 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001467 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001468 };
Rob Clarka471b672018-01-10 11:33:30 +01001469
Mario Six95922152018-08-09 14:51:19 +02001470 axi: axi@0 {
1471 compatible = "sandbox,axi";
1472 #address-cells = <0x1>;
1473 #size-cells = <0x1>;
1474 store@0 {
1475 compatible = "sandbox,sandbox_store";
1476 reg = <0x0 0x400>;
1477 };
1478 };
1479
Rob Clarka471b672018-01-10 11:33:30 +01001480 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001481 #address-cells = <1>;
1482 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001483 setting = "sunrise ohoka";
1484 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001485 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001486 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001487 chosen-test {
1488 compatible = "denx,u-boot-fdt-test";
1489 reg = <9 1>;
1490 };
1491 };
Mario Six35616ef2018-03-12 14:53:33 +01001492
1493 translation-test@8000 {
1494 compatible = "simple-bus";
1495 reg = <0x8000 0x4000>;
1496
1497 #address-cells = <0x2>;
1498 #size-cells = <0x1>;
1499
1500 ranges = <0 0x0 0x8000 0x1000
1501 1 0x100 0x9000 0x1000
1502 2 0x200 0xA000 0x1000
1503 3 0x300 0xB000 0x1000
1504 >;
1505
Fabien Dessenne22236e02019-05-31 15:11:30 +02001506 dma-ranges = <0 0x000 0x10000000 0x1000
1507 1 0x100 0x20000000 0x1000
1508 >;
1509
Mario Six35616ef2018-03-12 14:53:33 +01001510 dev@0,0 {
1511 compatible = "denx,u-boot-fdt-dummy";
1512 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojasa3181152018-12-03 19:37:09 +01001513 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001514 };
1515
1516 dev@1,100 {
1517 compatible = "denx,u-boot-fdt-dummy";
1518 reg = <1 0x100 0x1000>;
1519
1520 };
1521
1522 dev@2,200 {
1523 compatible = "denx,u-boot-fdt-dummy";
1524 reg = <2 0x200 0x1000>;
1525 };
1526
1527
1528 noxlatebus@3,300 {
1529 compatible = "simple-bus";
1530 reg = <3 0x300 0x1000>;
1531
1532 #address-cells = <0x1>;
1533 #size-cells = <0x0>;
1534
1535 dev@42 {
1536 compatible = "denx,u-boot-fdt-dummy";
1537 reg = <0x42>;
1538 };
1539 };
1540 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001541
Dzmitry Sankouski54f4c832023-01-22 18:21:23 +03001542 ofnode-foreach {
1543 compatible = "foreach";
1544
1545 first {
1546 prop1 = <1>;
1547 prop2 = <2>;
1548 };
1549
1550 second {
1551 prop1 = <1>;
1552 prop2 = <2>;
1553 };
1554 };
1555
Mario Six02ad6fb2018-09-27 09:19:31 +02001556 osd {
1557 compatible = "sandbox,sandbox_osd";
1558 };
Tom Rinib93eea72018-09-30 18:16:51 -04001559
Jens Wiklander86afaa62018-09-25 16:40:16 +02001560 sandbox_tee {
1561 compatible = "sandbox,tee";
1562 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001563
1564 sandbox_virtio1 {
1565 compatible = "sandbox,virtio1";
Simon Glass8de5a542023-01-17 10:47:51 -07001566 virtio-type = <4>; /* rng */
Bin Meng1bb290d2018-10-15 02:21:26 -07001567 };
1568
1569 sandbox_virtio2 {
1570 compatible = "sandbox,virtio2";
1571 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001572
Simon Glass8de5a542023-01-17 10:47:51 -07001573 sandbox-virtio-blk {
1574 compatible = "sandbox,virtio1";
1575 virtio-type = <2>; /* block */
1576 };
1577
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001578 sandbox_scmi {
1579 compatible = "sandbox,scmi-devices";
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001580 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001581 resets = <&reset_scmi 3>;
1582 regul0-supply = <&regul0_scmi>;
1583 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001584 };
1585
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001586 pinctrl {
1587 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001588
Sean Anderson3438e3b2020-09-14 11:01:57 -04001589 pinctrl-names = "default", "alternate";
1590 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1591 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001592
Sean Anderson3438e3b2020-09-14 11:01:57 -04001593 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001594 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001595 pins = "P5";
1596 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001597 bias-pull-up;
1598 input-disable;
1599 };
1600 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001601 pins = "P6";
1602 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001603 output-high;
1604 drive-open-drain;
1605 };
1606 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001607 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001608 bias-pull-down;
1609 input-enable;
1610 };
1611 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001612 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001613 bias-disable;
1614 };
1615 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001616
1617 pinctrl_i2c: i2c {
1618 groups {
1619 groups = "I2C_UART";
1620 function = "I2C";
1621 };
1622
1623 pins {
1624 pins = "P0", "P1";
1625 drive-open-drain;
1626 };
1627 };
1628
1629 pinctrl_i2s: i2s {
1630 groups = "SPI_I2S";
1631 function = "I2S";
1632 };
1633
1634 pinctrl_spi: spi {
1635 groups = "SPI_I2S";
1636 function = "SPI";
1637
1638 cs {
1639 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1640 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1641 };
1642 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001643 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001644
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001645 pinctrl-single-no-width {
1646 compatible = "pinctrl-single";
1647 reg = <0x0000 0x238>;
1648 #pinctrl-cells = <1>;
1649 pinctrl-single,function-mask = <0x7f>;
1650 };
1651
1652 pinctrl-single-pins {
1653 compatible = "pinctrl-single";
1654 reg = <0x0000 0x238>;
1655 #pinctrl-cells = <1>;
1656 pinctrl-single,register-width = <32>;
1657 pinctrl-single,function-mask = <0x7f>;
1658
1659 pinmux_pwm_pins: pinmux_pwm_pins {
1660 pinctrl-single,pins = < 0x48 0x06 >;
1661 };
1662
1663 pinmux_spi0_pins: pinmux_spi0_pins {
1664 pinctrl-single,pins = <
1665 0x190 0x0c
1666 0x194 0x0c
1667 0x198 0x23
1668 0x19c 0x0c
1669 >;
1670 };
1671
1672 pinmux_uart0_pins: pinmux_uart0_pins {
1673 pinctrl-single,pins = <
1674 0x70 0x30
1675 0x74 0x00
1676 >;
1677 };
1678 };
1679
1680 pinctrl-single-bits {
1681 compatible = "pinctrl-single";
1682 reg = <0x0000 0x50>;
1683 #pinctrl-cells = <2>;
1684 pinctrl-single,bit-per-mux;
1685 pinctrl-single,register-width = <32>;
1686 pinctrl-single,function-mask = <0xf>;
1687
1688 pinmux_i2c0_pins: pinmux_i2c0_pins {
1689 pinctrl-single,bits = <
1690 0x10 0x00002200 0x0000ff00
1691 >;
1692 };
1693
1694 pinmux_lcd_pins: pinmux_lcd_pins {
1695 pinctrl-single,bits = <
1696 0x40 0x22222200 0xffffff00
1697 0x44 0x22222222 0xffffffff
1698 0x48 0x00000022 0x000000ff
1699 0x48 0x02000000 0x0f000000
1700 0x4c 0x02000022 0x0f0000ff
1701 >;
1702 };
1703 };
1704
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001705 hwspinlock@0 {
1706 compatible = "sandbox,hwspinlock";
1707 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001708
1709 dma: dma {
1710 compatible = "sandbox,dma";
1711 #dma-cells = <1>;
1712
1713 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1714 dma-names = "m2m", "tx0", "rx0";
1715 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001716
Alex Marginean0649be52019-07-12 10:13:53 +03001717 /*
1718 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1719 * end of the test. If parent mdio is removed first, clean-up of the
1720 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1721 * active at the end of the test. That it turn doesn't allow the mdio
1722 * class to be destroyed, triggering an error.
1723 */
1724 mdio-mux-test {
1725 compatible = "sandbox,mdio-mux";
1726 #address-cells = <1>;
1727 #size-cells = <0>;
1728 mdio-parent-bus = <&mdio>;
1729
1730 mdio-ch-test@0 {
1731 reg = <0>;
1732 };
1733 mdio-ch-test@1 {
1734 reg = <1>;
1735 };
1736 };
1737
1738 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001739 compatible = "sandbox,mdio";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +02001740 #address-cells = <1>;
1741 #size-cells = <0>;
1742
1743 ethphy1: ethernet-phy@1 {
1744 reg = <1>;
1745 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001746 };
Sean Andersonb7860542020-06-24 06:41:12 -04001747
1748 pm-bus-test {
1749 compatible = "simple-pm-bus";
1750 clocks = <&clk_sandbox 4>;
1751 power-domains = <&pwrdom 1>;
1752 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001753
1754 resetc2: syscon-reset {
1755 compatible = "syscon-reset";
1756 #reset-cells = <1>;
1757 regmap = <&syscon0>;
1758 offset = <1>;
1759 mask = <0x27FFFFFF>;
1760 assert-high = <0>;
1761 };
1762
1763 syscon-reset-test {
1764 compatible = "sandbox,misc_sandbox";
1765 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1766 reset-names = "valid", "no_mask", "out_of_range";
1767 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301768
Simon Glass458b66a2020-11-05 06:32:05 -07001769 sysinfo {
1770 compatible = "sandbox,sysinfo-sandbox";
1771 };
1772
Sean Anderson1c830672021-04-20 10:50:58 -04001773 sysinfo-gpio {
1774 compatible = "gpio-sysinfo";
1775 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1776 revisions = <19>, <5>;
1777 names = "rev_a", "foo";
1778 };
1779
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301780 some_regmapped-bus {
1781 #address-cells = <0x1>;
1782 #size-cells = <0x1>;
1783
1784 ranges = <0x0 0x0 0x10>;
1785 compatible = "simple-bus";
1786
1787 regmap-test_0 {
1788 reg = <0 0x10>;
1789 compatible = "sandbox,regmap_test";
1790 };
1791 };
Robert Marko9cf87122022-09-06 13:30:35 +02001792
1793 thermal {
1794 compatible = "sandbox,thermal";
1795 };
Sughosh Ganu77079e72022-10-21 18:16:05 +05301796
1797 fwu-mdata {
1798 compatible = "u-boot,fwu-mdata-gpt";
1799 fwu-mdata-store = <&mmc0>;
1800 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001801};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001802
1803#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001804#include "cros-ec-keyboard.dtsi"
Simon Glass5e135d32022-10-20 18:23:15 -06001805
1806#ifdef CONFIG_SANDBOX_VPL
1807#include "sandbox_vpl.dtsi"
1808#endif