Blame - arch/arm/cpu/armv7/ls102xa/Kconfig - filogic/uboot

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York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	1	config ARCH_LS1021A
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	2	bool
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	3	select SYS_FSL_ERRATUM_A008378
				4	select SYS_FSL_ERRATUM_A008407
Ran Wang	1509c8a	2017-09-04 18:46:52 +0800	[diff] [blame^]	5	select SYS_FSL_ERRATUM_A009008
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	6	select SYS_FSL_ERRATUM_A009663
				7	select SYS_FSL_ERRATUM_A009942
York Sun	149eb33	2016-09-26 08:09:27 -0700	[diff] [blame]	8	select SYS_FSL_ERRATUM_A010315
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	9	select SYS_FSL_HAS_CCI400
York Sun	6b62ef0	2016-10-04 18:01:34 -0700	[diff] [blame]	10	select SYS_FSL_SRDS_1
				11	select SYS_HAS_SERDES
York Sun	d297d39	2016-12-28 08:43:40 -0800	[diff] [blame]	12	select SYS_FSL_DDR_BE if SYS_FSL_DDR
				13	select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
				14	select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
				15	select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
York Sun	92c36e2	2016-12-28 08:43:30 -0800	[diff] [blame]	16	select SYS_FSL_HAS_SEC
				17	select SYS_FSL_SEC_COMPAT_5
York Sun	fa419942	2016-12-28 08:43:31 -0800	[diff] [blame]	18	select SYS_FSL_SEC_LE
Simon Glass	0e5faf0	2017-06-14 21:28:21 -0600	[diff] [blame]	19	imply SCSI
Simon Glass	c88a09a	2017-08-04 16:34:34 -0600	[diff] [blame]	20	imply CMD_PCI
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	21
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	22	menu "LS102xA architecture"
				23	depends on ARCH_LS1021A
				24
Hou Zhiqiang	d553bf2	2016-12-13 14:54:24 +0800	[diff] [blame]	25	config FSL_PCIE_COMPAT
				26	string "PCIe compatible of Kernel DT"
				27	depends on PCIE_LAYERSCAPE
				28	default "fsl,ls1021a-pcie" if ARCH_LS1021A
				29	help
				30	This compatible is used to find pci controller node in Kernel DT
				31	to complete fixup.
				32
York Sun	4de7e93	2016-09-26 08:09:29 -0700	[diff] [blame]	33	config LS1_DEEP_SLEEP
York Sun	fcd0e74	2016-10-04 14:31:47 -0700	[diff] [blame]	34	bool "Deep sleep"
				35	depends on ARCH_LS1021A
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	36
York Sun	f188d22	2016-10-04 14:45:01 -0700	[diff] [blame]	37	config MAX_CPUS
				38	int "Maximum number of CPUs permitted for LS102xA"
				39	depends on ARCH_LS1021A
				40	default 2
				41	help
				42	Set this number to the maximum number of possible CPUs in the SoC.
				43	SoCs may have multiple clusters with each cluster may have multiple
				44	ports. If some ports are reserved but higher ports are used for
				45	cores, count the reserved ports. This will allocate enough memory
				46	in spin table to properly handle all cores.
				47
York Sun	dfa93a9	2016-12-02 09:31:43 -0800	[diff] [blame]	48	config SECURE_BOOT
				49	bool "Secure Boot"
				50	help
				51	Enable Freescale Secure Boot feature. Normally selected
				52	by defconfig. If unsure, do not change.
				53
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	54	config SYS_CCI400_OFFSET
				55	hex "Offset for CCI400 base"
				56	depends on SYS_FSL_HAS_CCI400
				57	default 0x180000
				58	help
				59	Offset for CCI400 base.
				60	CCI400 base addr = CCSRBAR + CCI400_OFFSET
				61
Ran Wang	1509c8a	2017-09-04 18:46:52 +0800	[diff] [blame^]	62	config SYS_FSL_ERRATUM_A009008
				63	bool
				64	help
				65	Workaround for USB PHY erratum A009008
				66
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	67	config SYS_FSL_ERRATUM_A010315
				68	bool "Workaround for PCIe erratum A010315"
				69
Ashish Kumar	1123406	2017-08-11 11:09:14 +0530	[diff] [blame]	70	config SYS_FSL_HAS_CCI400
				71	bool
				72
York Sun	6b62ef0	2016-10-04 18:01:34 -0700	[diff] [blame]	73	config SYS_FSL_SRDS_1
				74	bool
				75
				76	config SYS_FSL_SRDS_2
				77	bool
				78
				79	config SYS_HAS_SERDES
				80	bool
York Sun	f64fc5c	2016-10-04 18:04:37 -0700	[diff] [blame]	81
York Sun	e7310a3	2016-10-04 14:45:54 -0700	[diff] [blame]	82	config SYS_FSL_IFC_BANK_COUNT
				83	int "Maximum banks of Integrated flash controller"
				84	depends on ARCH_LS1021A
				85	default 8
				86
York Sun	1dc61ca	2016-12-28 08:43:41 -0800	[diff] [blame]	87	config SYS_FSL_ERRATUM_A008407
				88	bool
				89
York Sun	4dd8c61	2016-10-04 14:31:48 -0700	[diff] [blame]	90	endmenu