blob: 2761588f0dadb0a0c1663fbd873edecf05efcd24 [file] [log] [blame]
Simon Glass4cc43bf2021-08-18 21:40:25 -06001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Devicetree file for running sandbox tests
4 *
5 * This includes lots of extra devices used by various tests.
6 *
7 * Note that SPL use the main sandbox.dts file
8 */
9
Simon Glassb2c1cac2014-02-26 15:59:21 -070010/dts-v1/;
11
Patrick Delaunay23aee612020-01-13 11:35:13 +010012#include <dt-bindings/gpio/gpio.h>
13#include <dt-bindings/gpio/sandbox-gpio.h>
Marek Szyprowskiad398592021-02-18 11:33:18 +010014#include <dt-bindings/input/input.h>
Sean Anderson3438e3b2020-09-14 11:01:57 -040015#include <dt-bindings/pinctrl/sandbox-pinmux.h>
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +053016#include <dt-bindings/mux/mux.h>
Patrick Delaunay23aee612020-01-13 11:35:13 +010017
Simon Glassb2c1cac2014-02-26 15:59:21 -070018/ {
19 model = "sandbox";
20 compatible = "sandbox";
21 #address-cells = <1>;
Simon Glasscf61f742015-07-06 12:54:36 -060022 #size-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -070023
Simon Glassfef72b72014-07-23 06:55:03 -060024 aliases {
25 console = &uart0;
Michael Walle7efcdfd2021-02-25 16:51:11 +010026 ethernet0 = "/eth@10002000";
27 ethernet2 = &swp_0;
28 ethernet3 = &eth_3;
29 ethernet4 = &dsa_eth0;
30 ethernet5 = &eth_5;
Sean Anderson67d93a42022-05-05 13:11:30 -040031 ethernet6 = "/eth@10004000";
32 ethernet7 = &swp_1;
33 ethernet8 = &phy_eth0;
Simon Glass5620cf82018-10-01 12:22:40 -060034 gpio1 = &gpio_a;
35 gpio2 = &gpio_b;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +010036 gpio3 = &gpio_c;
Simon Glass0ccb0972015-01-25 08:27:05 -070037 i2c0 = "/i2c@0";
Simon Glasse4fef742017-04-23 20:02:07 -060038 mmc0 = "/mmc0";
39 mmc1 = "/mmc1";
Bin Meng408e5902018-08-03 01:14:41 -070040 pci0 = &pci0;
41 pci1 = &pci1;
Bin Meng510dddb2018-08-03 01:14:50 -070042 pci2 = &pci2;
Michael Walle7c41a222020-06-02 01:47:09 +020043 remoteproc0 = &rproc_1;
44 remoteproc1 = &rproc_2;
Simon Glass336b2952015-05-22 15:42:17 -060045 rtc0 = &rtc_0;
46 rtc1 = &rtc_1;
Simon Glass5b968632015-05-22 15:42:15 -060047 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +020048 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -070049 testbus3 = "/some-bus";
50 testfdt0 = "/some-bus/c-test@0";
Simon Glass7d5e4112020-12-16 21:20:26 -070051 testfdt12 = "/some-bus/c-test@1";
Simon Glass0ccb0972015-01-25 08:27:05 -070052 testfdt3 = "/b-test";
53 testfdt5 = "/some-bus/c-test@5";
54 testfdt8 = "/a-test";
Simon Glass791a17f2020-12-16 21:20:27 -070055 testfdtm1 = &testfdtm1;
Eugeniu Rosca5ba71e52018-05-19 14:13:55 +020056 fdt-dummy0 = "/translation-test@8000/dev@0,0";
57 fdt-dummy1 = "/translation-test@8000/dev@1,100";
58 fdt-dummy2 = "/translation-test@8000/dev@2,200";
59 fdt-dummy3 = "/translation-test@8000/noxlatebus@3,300/dev@42";
Simon Glass31680482015-03-25 12:23:05 -060060 usb0 = &usb_0;
61 usb1 = &usb_1;
62 usb2 = &usb_2;
Mario Six95922152018-08-09 14:51:19 +020063 axi0 = &axi;
Mario Six02ad6fb2018-09-27 09:19:31 +020064 osd0 = "/osd";
Simon Glassfef72b72014-07-23 06:55:03 -060065 };
66
Philippe Reynes462d1632022-03-28 22:56:53 +020067 binman {
68 };
69
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020070 config {
Simon Glass0034d962021-08-07 07:24:01 -060071 testing-bool;
72 testing-int = <123>;
73 testing-str = "testing";
Rasmus Villemoes30d4d2b2021-04-21 11:06:55 +020074 environment {
75 from_fdt = "yes";
76 fdt_env_path = "";
77 };
78 };
79
Simon Glassb255efc2022-04-24 23:31:24 -060080 bootstd {
81 compatible = "u-boot,boot-std";
82
83 filename-prefixes = "/", "/boot/";
84 bootdev-order = "mmc2", "mmc1";
85
86 syslinux {
87 compatible = "u-boot,distro-syslinux";
88 };
89
90 efi {
91 compatible = "u-boot,distro-efi";
92 };
93 };
94
Andrew Scull451b8b12022-05-30 10:00:12 +000095 fuzzing-engine {
96 compatible = "sandbox,fuzzing-engine";
97 };
98
Nandor Han6521e5d2021-06-10 16:56:44 +030099 reboot-mode0 {
100 compatible = "reboot-mode-gpio";
101 gpios = <&gpio_c 0 GPIO_ACTIVE_HIGH>, <&gpio_c 1 GPIO_ACTIVE_HIGH>;
102 u-boot,env-variable = "bootstatus";
103 mode-test = <0x01>;
104 mode-download = <0x03>;
105 };
106
Nandor Han7e4067a2021-06-10 16:56:45 +0300107 reboot_mode1: reboot-mode@14 {
108 compatible = "reboot-mode-rtc";
109 rtc = <&rtc_0>;
110 reg = <0x30 4>;
111 u-boot,env-variable = "bootstatus";
112 big-endian;
113 mode-test = <0x21969147>;
114 mode-download = <0x51939147>;
115 };
116
Simon Glassed96cde2018-12-10 10:37:33 -0700117 audio: audio-codec {
118 compatible = "sandbox,audio-codec";
119 #sound-dai-cells = <1>;
120 };
121
Philippe Reynes1ee26482020-07-24 18:19:51 +0200122 buttons {
123 compatible = "gpio-keys";
124
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200125 btn1 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200126 gpios = <&gpio_a 3 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200127 label = "button1";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200128 };
129
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200130 btn2 {
Philippe Reynes1ee26482020-07-24 18:19:51 +0200131 gpios = <&gpio_a 4 0>;
Heinrich Schuchardt57c2fc62020-09-14 12:50:54 +0200132 label = "button2";
Philippe Reynes1ee26482020-07-24 18:19:51 +0200133 };
134 };
135
Marek Szyprowskiad398592021-02-18 11:33:18 +0100136 buttons2 {
137 compatible = "adc-keys";
138 io-channels = <&adc 3>;
139 keyup-threshold-microvolt = <3000000>;
140
141 button-up {
142 label = "button3";
143 linux,code = <KEY_F3>;
144 press-threshold-microvolt = <1500000>;
145 };
146
147 button-down {
148 label = "button4";
149 linux,code = <KEY_F4>;
150 press-threshold-microvolt = <1000000>;
151 };
152
153 button-enter {
154 label = "button5";
155 linux,code = <KEY_F5>;
156 press-threshold-microvolt = <500000>;
157 };
158 };
159
Simon Glassc953aaf2018-12-10 10:37:34 -0700160 cros_ec: cros-ec {
Simon Glass699c9ca2018-10-01 12:22:08 -0600161 reg = <0 0>;
162 compatible = "google,cros-ec-sandbox";
163
164 /*
165 * This describes the flash memory within the EC. Note
166 * that the STM32L flash erases to 0, not 0xff.
167 */
168 flash {
169 image-pos = <0x08000000>;
170 size = <0x20000>;
171 erase-value = <0>;
172
173 /* Information for sandbox */
174 ro {
175 image-pos = <0>;
176 size = <0xf000>;
177 };
178 wp-ro {
179 image-pos = <0xf000>;
180 size = <0x1000>;
Simon Glassbf0a6922021-01-21 13:57:14 -0700181 used = <0x884>;
182 compress = "lz4";
183 uncomp-size = <0xcf8>;
184 hash {
185 algo = "sha256";
186 value = [00 01 02 03 04 05 06 07
187 08 09 0a 0b 0c 0d 0e 0f
188 10 11 12 13 14 15 16 17
189 18 19 1a 1b 1c 1d 1e 1f];
190 };
Simon Glass699c9ca2018-10-01 12:22:08 -0600191 };
192 rw {
193 image-pos = <0x10000>;
194 size = <0x10000>;
195 };
196 };
Alper Nebi Yasak8a8cd4f2021-05-19 19:33:31 +0300197
198 cros_ec_pwm: cros-ec-pwm {
199 compatible = "google,cros-ec-pwm";
200 #pwm-cells = <1>;
201 };
202
Simon Glass699c9ca2018-10-01 12:22:08 -0600203 };
204
Yannick Fertré9712c822019-10-07 15:29:05 +0200205 dsi_host: dsi_host {
206 compatible = "sandbox,dsi-host";
207 };
208
Simon Glassb2c1cac2014-02-26 15:59:21 -0700209 a-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600210 reg = <0 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700211 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600212 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700213 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600214 u-boot,dm-pre-reloc;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100215 test-gpios = <&gpio_a 1>, <&gpio_a 4>,
216 <&gpio_b 5 GPIO_ACTIVE_HIGH 3 2 1>,
Simon Glass16e10402015-01-05 20:05:29 -0700217 <0>, <&gpio_a 12>;
Patrick Delaunay23aee612020-01-13 11:35:13 +0100218 test2-gpios = <&gpio_a 1>, <&gpio_a 4>,
219 <&gpio_b 6 GPIO_ACTIVE_LOW 3 2 1>,
220 <&gpio_b 7 GPIO_IN 3 2 1>,
221 <&gpio_b 8 GPIO_OUT 3 2 1>,
222 <&gpio_b 9 (GPIO_OUT|GPIO_OUT_ACTIVE) 3 2 1>;
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100223 test3-gpios =
224 <&gpio_c 0 (GPIO_OUT|GPIO_OPEN_DRAIN)>,
225 <&gpio_c 1 (GPIO_OUT|GPIO_OPEN_SOURCE)>,
226 <&gpio_c 2 GPIO_OUT>,
227 <&gpio_c 3 (GPIO_IN|GPIO_PULL_UP)>,
228 <&gpio_c 4 (GPIO_IN|GPIO_PULL_DOWN)>,
Neil Armstrong643778b2020-05-05 10:43:18 +0200229 <&gpio_c 5 GPIO_IN>,
230 <&gpio_c 6 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_DRAIN)>,
231 <&gpio_c 7 (GPIO_ACTIVE_LOW|GPIO_OUT|GPIO_OPEN_SOURCE)>;
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530232 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
233 test5-gpios = <&gpio_a 19>;
234
Simon Glass73025392021-10-23 17:26:04 -0600235 bool-value;
Simon Glass6df01f92018-12-10 10:37:37 -0700236 int-value = <1234>;
237 uint-value = <(-1234)>;
Dario Binacchi421e81e2020-03-29 18:04:40 +0200238 int64-value = /bits/ 64 <0x1111222233334444>;
Dario Binacchi81d80b52020-03-29 18:04:41 +0200239 int-array = <5678 9123 4567>;
Simon Glassdd0ed902020-07-07 13:11:58 -0600240 str-value = "test string";
Simon Glass515dcff2020-02-06 09:55:00 -0700241 interrupts-extended = <&irq 3 0>;
Simon Glass09642392020-07-07 13:12:11 -0600242 acpi,name = "GHIJ";
Patrick Delaunay8cd28012020-09-25 09:41:16 +0200243 phandle-value = <&gpio_c 10>, <0xFFFFFFFF 20>, <&gpio_a 30>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530244
245 mux-controls = <&muxcontroller0 0>, <&muxcontroller0 1>,
246 <&muxcontroller0 2>, <&muxcontroller0 3>,
247 <&muxcontroller1>;
248 mux-control-names = "mux0", "mux1", "mux2", "mux3", "mux4";
249 mux-syscon = <&syscon3>;
Dario Binacchi836cc9d2020-12-30 00:16:26 +0100250 display-timings {
251 timing0: 240x320 {
252 clock-frequency = <6500000>;
253 hactive = <240>;
254 vactive = <320>;
255 hfront-porch = <6>;
256 hback-porch = <7>;
257 hsync-len = <1>;
258 vback-porch = <5>;
259 vfront-porch = <8>;
260 vsync-len = <2>;
261 hsync-active = <1>;
262 vsync-active = <0>;
263 de-active = <1>;
264 pixelclk-active = <1>;
265 interlaced;
266 doublescan;
267 doubleclk;
268 };
269 timing1: 480x800 {
270 clock-frequency = <9000000>;
271 hactive = <480>;
272 vactive = <800>;
273 hfront-porch = <10>;
274 hback-porch = <59>;
275 hsync-len = <12>;
276 vback-porch = <15>;
277 vfront-porch = <17>;
278 vsync-len = <16>;
279 hsync-active = <0>;
280 vsync-active = <1>;
281 de-active = <0>;
282 pixelclk-active = <0>;
283 };
284 timing2: 800x480 {
285 clock-frequency = <33500000>;
286 hactive = <800>;
287 vactive = <480>;
288 hback-porch = <89>;
289 hfront-porch = <164>;
290 vback-porch = <23>;
291 vfront-porch = <10>;
292 hsync-len = <11>;
293 vsync-len = <13>;
294 };
295 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700296 };
297
298 junk {
Simon Glasscf61f742015-07-06 12:54:36 -0600299 reg = <1 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700300 compatible = "not,compatible";
301 };
302
303 no-compatible {
Simon Glasscf61f742015-07-06 12:54:36 -0600304 reg = <2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700305 };
306
Simon Glass5620cf82018-10-01 12:22:40 -0600307 backlight: backlight {
308 compatible = "pwm-backlight";
309 enable-gpios = <&gpio_a 1>;
310 power-supply = <&ldo_1>;
311 pwms = <&pwm 0 1000>;
312 default-brightness-level = <5>;
313 brightness-levels = <0 16 32 64 128 170 202 234 255>;
314 };
315
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200316 bind-test {
Patrice Chotard7b7f9392020-07-28 09:13:33 +0200317 compatible = "simple-bus";
Jean-Jacques Hiblote83a31b2018-08-09 16:17:46 +0200318 bind-test-child1 {
319 compatible = "sandbox,phy";
320 #phy-cells = <1>;
321 };
322
323 bind-test-child2 {
324 compatible = "simple-bus";
325 };
326 };
327
Simon Glassb2c1cac2014-02-26 15:59:21 -0700328 b-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600329 reg = <3 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700330 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600331 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700332 ping-add = <3>;
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +0530333
334 mux-controls = <&muxcontroller0 0>;
335 mux-control-names = "mux0";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700336 };
337
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200338 phy_provider0: gen_phy@0 {
339 compatible = "sandbox,phy";
340 #phy-cells = <1>;
341 };
342
343 phy_provider1: gen_phy@1 {
344 compatible = "sandbox,phy";
345 #phy-cells = <0>;
346 broken;
347 };
348
developer71092972020-05-02 11:35:12 +0200349 phy_provider2: gen_phy@2 {
350 compatible = "sandbox,phy";
351 #phy-cells = <0>;
352 };
353
Jean-Jacques Hiblot7e9db022017-04-24 11:51:28 +0200354 gen_phy_user: gen_phy_user {
355 compatible = "simple-bus";
356 phys = <&phy_provider0 0>, <&phy_provider0 1>, <&phy_provider1>;
357 phy-names = "phy1", "phy2", "phy3";
358 };
359
developer71092972020-05-02 11:35:12 +0200360 gen_phy_user1: gen_phy_user1 {
361 compatible = "simple-bus";
362 phys = <&phy_provider0 0>, <&phy_provider2>;
363 phy-names = "phy1", "phy2";
364 };
365
Simon Glassb2c1cac2014-02-26 15:59:21 -0700366 some-bus {
367 #address-cells = <1>;
368 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600369 compatible = "denx,u-boot-test-bus";
Simon Glasscf61f742015-07-06 12:54:36 -0600370 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600371 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700372 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600373 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700374 compatible = "denx,u-boot-fdt-test";
375 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600376 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700377 ping-add = <5>;
378 };
Simon Glass40717422014-07-23 06:55:18 -0600379 c-test@0 {
380 compatible = "denx,u-boot-fdt-test";
381 reg = <0>;
382 ping-expect = <6>;
383 ping-add = <6>;
384 };
385 c-test@1 {
386 compatible = "denx,u-boot-fdt-test";
387 reg = <1>;
388 ping-expect = <7>;
389 ping-add = <7>;
390 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700391 };
392
393 d-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600394 reg = <3 1>;
Simon Glassdb6f0202014-07-23 06:55:12 -0600395 ping-expect = <6>;
396 ping-add = <6>;
397 compatible = "google,another-fdt-test";
398 };
399
400 e-test {
Simon Glasscf61f742015-07-06 12:54:36 -0600401 reg = <3 1>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600402 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700403 ping-add = <6>;
404 compatible = "google,another-fdt-test";
405 };
406
Simon Glass0ccb0972015-01-25 08:27:05 -0700407 f-test {
408 compatible = "denx,u-boot-fdt-test";
409 };
410
411 g-test {
412 compatible = "denx,u-boot-fdt-test";
413 };
414
Bin Mengd9d24782018-10-10 22:07:01 -0700415 h-test {
416 compatible = "denx,u-boot-fdt-test1";
417 };
418
developercf8bc132020-05-02 11:35:10 +0200419 i-test {
420 compatible = "mediatek,u-boot-fdt-test";
421 #address-cells = <1>;
422 #size-cells = <0>;
423
424 subnode@0 {
425 reg = <0>;
426 };
427
428 subnode@1 {
429 reg = <1>;
430 };
431
432 subnode@2 {
433 reg = <2>;
434 };
435 };
436
Simon Glass204675c2019-12-29 21:19:25 -0700437 devres-test {
438 compatible = "denx,u-boot-devres-test";
439 };
440
Jean-Jacques Hiblot73873402020-09-11 13:43:35 +0530441 another-test {
442 reg = <0 2>;
443 compatible = "denx,u-boot-fdt-test";
444 test4-gpios = <&gpio_a 14>, <&gpio_b 4 1 3 2 1>;
445 test5-gpios = <&gpio_a 19>;
446 };
447
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100448 mmio-bus@0 {
449 #address-cells = <1>;
450 #size-cells = <1>;
451 compatible = "denx,u-boot-test-bus";
452 dma-ranges = <0x10000000 0x00000000 0x00040000>;
453
454 subnode@0 {
455 compatible = "denx,u-boot-fdt-test";
456 };
457 };
458
459 mmio-bus@1 {
460 #address-cells = <1>;
461 #size-cells = <1>;
462 compatible = "denx,u-boot-test-bus";
Nicolas Saenz Julienne892e9b42021-01-12 13:55:25 +0100463
464 subnode@0 {
465 compatible = "denx,u-boot-fdt-test";
466 };
Nicolas Saenz Julienne22b7f7e2021-01-12 13:55:23 +0100467 };
468
Simon Glass3c601b12020-07-07 13:12:06 -0600469 acpi_test1: acpi-test {
Simon Glass2d67fdf2020-04-08 16:57:34 -0600470 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600471 acpi-ssdt-test-data = "ab";
Simon Glass990cd5b2020-07-07 13:12:08 -0600472 acpi-dsdt-test-data = "hi";
Simon Glassebb2e832020-07-07 13:11:39 -0600473 child {
474 compatible = "denx,u-boot-acpi-test";
475 };
Simon Glass2d67fdf2020-04-08 16:57:34 -0600476 };
477
Simon Glass3c601b12020-07-07 13:12:06 -0600478 acpi_test2: acpi-test2 {
Simon Glass17968c32020-04-26 09:19:46 -0600479 compatible = "denx,u-boot-acpi-test";
Simon Glassd43e0ba2020-07-07 13:12:03 -0600480 acpi-ssdt-test-data = "cd";
Simon Glass990cd5b2020-07-07 13:12:08 -0600481 acpi-dsdt-test-data = "jk";
Simon Glass17968c32020-04-26 09:19:46 -0600482 };
483
Patrice Chotard9cc2d142017-09-04 14:55:57 +0200484 clocks {
485 clk_fixed: clk-fixed {
486 compatible = "fixed-clock";
487 #clock-cells = <0>;
488 clock-frequency = <1234>;
489 };
Anup Patel8d28c3c2019-02-25 08:14:55 +0000490
491 clk_fixed_factor: clk-fixed-factor {
492 compatible = "fixed-factor-clock";
493 #clock-cells = <0>;
494 clock-div = <3>;
495 clock-mult = <2>;
496 clocks = <&clk_fixed>;
497 };
Lukasz Majewskiccafcdd2019-06-24 15:50:47 +0200498
499 osc {
500 compatible = "fixed-clock";
501 #clock-cells = <0>;
502 clock-frequency = <20000000>;
503 };
Stephen Warrena9622432016-06-17 09:44:00 -0600504 };
505
506 clk_sandbox: clk-sbox {
Simon Glass8cc4d822015-07-06 12:54:24 -0600507 compatible = "sandbox,clk";
Stephen Warrena9622432016-06-17 09:44:00 -0600508 #clock-cells = <1>;
Jean-Jacques Hiblotc1e9c942019-10-22 14:00:07 +0200509 assigned-clocks = <&clk_sandbox 3>;
510 assigned-clock-rates = <321>;
Stephen Warrena9622432016-06-17 09:44:00 -0600511 };
512
513 clk-test {
514 compatible = "sandbox,clk-test";
515 clocks = <&clk_fixed>,
516 <&clk_sandbox 1>,
Jean-Jacques Hiblot98e84182019-10-22 14:00:05 +0200517 <&clk_sandbox 0>,
518 <&clk_sandbox 3>,
519 <&clk_sandbox 2>;
520 clock-names = "fixed", "i2c", "spi", "uart2", "uart1";
Simon Glass8cc4d822015-07-06 12:54:24 -0600521 };
522
Lukasz Majewski8c0709b2019-06-24 15:50:50 +0200523 ccf: clk-ccf {
524 compatible = "sandbox,clk-ccf";
525 };
526
Simon Glass507ab962021-12-04 08:56:31 -0700527 efi-media {
528 compatible = "sandbox,efi-media";
529 };
530
Simon Glass5b968632015-05-22 15:42:15 -0600531 eth@10002000 {
532 compatible = "sandbox,eth";
533 reg = <0x10002000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600534 };
535
536 eth_5: eth@10003000 {
537 compatible = "sandbox,eth";
538 reg = <0x10003000 0x1000>;
Sean Anderson13652b82022-05-05 13:11:44 -0400539 nvmem-cells = <&eth5_addr>;
540 nvmem-cell-names = "mac-address";
Simon Glass5b968632015-05-22 15:42:15 -0600541 };
542
Bin Meng04a11cb2015-08-27 22:25:53 -0700543 eth_3: sbe5 {
544 compatible = "sandbox,eth";
545 reg = <0x10005000 0x1000>;
Sean Andersone2dc0e62022-05-05 13:11:42 -0400546 nvmem-cells = <&eth3_addr>;
547 nvmem-cell-names = "mac-address";
Bin Meng04a11cb2015-08-27 22:25:53 -0700548 };
549
Simon Glass5b968632015-05-22 15:42:15 -0600550 eth@10004000 {
551 compatible = "sandbox,eth";
552 reg = <0x10004000 0x1000>;
Simon Glass5b968632015-05-22 15:42:15 -0600553 };
554
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200555 phy_eth0: phy-test-eth {
556 compatible = "sandbox,eth";
557 reg = <0x10007000 0x1000>;
Sean Anderson24b1b8d2022-05-05 13:11:35 -0400558 mac-address = [ 02 00 11 22 33 49 ];
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200559 phy-handle = <&ethphy1>;
Marek BehĂșnbc194772022-04-07 00:33:01 +0200560 phy-mode = "2500base-x";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +0200561 };
562
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800563 dsa_eth0: dsa-test-eth {
564 compatible = "sandbox,eth";
565 reg = <0x10006000 0x1000>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400566 nvmem-cells = <&eth4_addr>;
567 nvmem-cell-names = "mac-address";
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800568 };
569
570 dsa-test {
571 compatible = "sandbox,dsa";
572
573 ports {
574 #address-cells = <1>;
575 #size-cells = <0>;
576 swp_0: port@0 {
577 reg = <0>;
578 label = "lan0";
579 phy-mode = "rgmii-rxid";
580
581 fixed-link {
582 speed = <100>;
583 full-duplex;
584 };
585 };
586
587 swp_1: port@1 {
588 reg = <1>;
589 label = "lan1";
590 phy-mode = "rgmii-txid";
Bin Meng381ed972021-03-14 20:14:58 +0800591 fixed-link = <0 1 100 0 0>;
Claudiu Manoild9eaa922021-03-14 20:14:57 +0800592 };
593
594 port@2 {
595 reg = <2>;
596 ethernet = <&dsa_eth0>;
597
598 fixed-link {
599 speed = <1000>;
600 full-duplex;
601 };
602 };
603 };
604 };
605
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700606 firmware {
607 sandbox_firmware: sandbox-firmware {
608 compatible = "sandbox,firmware";
609 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200610
Etienne Carriere09665cb2022-02-21 09:22:39 +0100611 scmi {
Etienne Carriere02fd1262020-09-09 18:44:00 +0200612 compatible = "sandbox,scmi-agent";
613 #address-cells = <1>;
614 #size-cells = <0>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200615
Etienne Carriere09665cb2022-02-21 09:22:39 +0100616 protocol@10 {
617 reg = <0x10>;
618 };
619
620 clk_scmi: protocol@14 {
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +0200621 reg = <0x14>;
622 #clock-cells = <1>;
623 };
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200624
Etienne Carriere09665cb2022-02-21 09:22:39 +0100625 reset_scmi: protocol@16 {
Etienne Carriere8b9b6892020-09-09 18:44:07 +0200626 reg = <0x16>;
627 #reset-cells = <1>;
628 };
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100629
630 protocol@17 {
631 reg = <0x17>;
632
633 regulators {
634 #address-cells = <1>;
635 #size-cells = <0>;
636
Etienne Carriere09665cb2022-02-21 09:22:39 +0100637 regul0_scmi: reg@0 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100638 reg = <0>;
639 regulator-name = "sandbox-voltd0";
640 regulator-min-microvolt = <1100000>;
641 regulator-max-microvolt = <3300000>;
642 };
Etienne Carriere09665cb2022-02-21 09:22:39 +0100643 regul1_scmi: reg@1 {
Etienne Carriereb8f15cd2021-03-08 22:38:07 +0100644 reg = <0x1>;
645 regulator-name = "sandbox-voltd1";
646 regulator-min-microvolt = <1800000>;
647 };
648 };
649 };
Etienne Carriere02fd1262020-09-09 18:44:00 +0200650 };
Rajan Vajab3b2ddb2018-09-19 03:43:46 -0700651 };
652
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100653 pinctrl-gpio {
654 compatible = "sandbox,pinctrl-gpio";
Simon Glassb2c1cac2014-02-26 15:59:21 -0700655
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100656 gpio_a: base-gpios {
657 compatible = "sandbox,gpio";
658 gpio-controller;
659 #gpio-cells = <1>;
660 gpio-bank-name = "a";
661 sandbox,gpio-count = <20>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200662 hog_input_active_low {
663 gpio-hog;
664 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200665 gpios = <10 GPIO_ACTIVE_LOW>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200666 };
667 hog_input_active_high {
668 gpio-hog;
669 input;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200670 gpios = <11 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200671 };
672 hog_output_low {
673 gpio-hog;
674 output-low;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200675 gpios = <12 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200676 };
677 hog_output_high {
678 gpio-hog;
679 output-high;
Philippe Reynesb25a5b32020-07-24 15:51:53 +0200680 gpios = <13 GPIO_ACTIVE_HIGH>;
Heiko Schocher4508abf2020-05-22 11:08:58 +0200681 };
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100682 };
683
684 gpio_b: extra-gpios {
685 compatible = "sandbox,gpio";
686 gpio-controller;
687 #gpio-cells = <5>;
688 gpio-bank-name = "b";
689 sandbox,gpio-count = <10>;
690 };
Simon Glass25348a42014-10-13 23:42:11 -0600691
Patrick Delaunay1b4a22f2020-01-13 11:35:15 +0100692 gpio_c: pinmux-gpios {
693 compatible = "sandbox,gpio";
694 gpio-controller;
695 #gpio-cells = <2>;
696 gpio-bank-name = "c";
697 sandbox,gpio-count = <10>;
698 };
Patrick Delaunay28bdaa52020-01-13 11:35:14 +0100699 };
700
Simon Glass7df766e2014-12-10 08:55:55 -0700701 i2c@0 {
702 #address-cells = <1>;
703 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -0600704 reg = <0 1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700705 compatible = "sandbox,i2c";
706 clock-frequency = <100000>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200707 pinctrl-names = "default";
708 pinctrl-0 = <&pinmux_i2c0_pins>;
709
Simon Glass7df766e2014-12-10 08:55:55 -0700710 eeprom@2c {
Sean Andersone2dc0e62022-05-05 13:11:42 -0400711 #address-cells = <1>;
712 #size-cells = <1>;
Simon Glass7df766e2014-12-10 08:55:55 -0700713 reg = <0x2c>;
714 compatible = "i2c-eeprom";
Simon Glass17b56f62018-11-18 08:14:34 -0700715 sandbox,emul = <&emul_eeprom>;
Michal Simek4f18f922020-05-28 11:48:55 +0200716 partitions {
717 compatible = "fixed-partitions";
718 #address-cells = <1>;
719 #size-cells = <1>;
720 bootcount_i2c: bootcount@10 {
721 reg = <10 2>;
722 };
723 };
Sean Andersone2dc0e62022-05-05 13:11:42 -0400724
725 eth3_addr: mac-address@24 {
726 reg = <24 6>;
727 };
Simon Glass7df766e2014-12-10 08:55:55 -0700728 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200729
Simon Glass336b2952015-05-22 15:42:17 -0600730 rtc_0: rtc@43 {
Sean Anderson5768e8b2022-05-05 13:11:43 -0400731 #address-cells = <1>;
732 #size-cells = <1>;
Simon Glass336b2952015-05-22 15:42:17 -0600733 reg = <0x43>;
734 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700735 sandbox,emul = <&emul0>;
Sean Anderson5768e8b2022-05-05 13:11:43 -0400736
737 eth4_addr: mac-address@40 {
738 reg = <0x40 6>;
739 };
Simon Glass336b2952015-05-22 15:42:17 -0600740 };
741
742 rtc_1: rtc@61 {
743 reg = <0x61>;
744 compatible = "sandbox-rtc";
Simon Glass17b56f62018-11-18 08:14:34 -0700745 sandbox,emul = <&emul1>;
746 };
747
748 i2c_emul: emul {
749 reg = <0xff>;
750 compatible = "sandbox,i2c-emul-parent";
751 emul_eeprom: emul-eeprom {
752 compatible = "sandbox,i2c-eeprom";
753 sandbox,filename = "i2c.bin";
754 sandbox,size = <256>;
755 };
756 emul0: emul0 {
Simon Glass98af3742021-02-03 06:01:17 -0700757 compatible = "sandbox,i2c-rtc-emul";
Simon Glass17b56f62018-11-18 08:14:34 -0700758 };
759 emul1: emull {
Simon Glass98af3742021-02-03 06:01:17 -0700760 compatible = "sandbox,i2c-rtc-emul";
Simon Glass336b2952015-05-22 15:42:17 -0600761 };
762 };
763
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200764 sandbox_pmic: sandbox_pmic {
765 reg = <0x40>;
Simon Glass17b56f62018-11-18 08:14:34 -0700766 sandbox,emul = <&emul_pmic0>;
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200767 };
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200768
769 mc34708: pmic@41 {
770 reg = <0x41>;
Simon Glass17b56f62018-11-18 08:14:34 -0700771 sandbox,emul = <&emul_pmic1>;
Lukasz Majewskia4d82972018-05-15 16:26:40 +0200772 };
Simon Glass7df766e2014-12-10 08:55:55 -0700773 };
774
Philipp Tomsich1fc53302018-12-14 21:14:29 +0100775 bootcount@0 {
776 compatible = "u-boot,bootcount-rtc";
777 rtc = <&rtc_1>;
778 offset = <0x13>;
779 };
780
Michal Simek4f18f922020-05-28 11:48:55 +0200781 bootcount {
782 compatible = "u-boot,bootcount-i2c-eeprom";
783 i2c-eeprom = <&bootcount_i2c>;
784 };
785
Nandor Han88895812021-06-10 15:40:38 +0300786 bootcount_4@0 {
787 compatible = "u-boot,bootcount-syscon";
788 syscon = <&syscon0>;
789 reg = <0x0 0x04>, <0x0 0x04>;
790 reg-names = "syscon_reg", "offset";
791 };
792
793 bootcount_2@0 {
794 compatible = "u-boot,bootcount-syscon";
795 syscon = <&syscon0>;
796 reg = <0x0 0x04>, <0x0 0x02> ;
797 reg-names = "syscon_reg", "offset";
798 };
799
Marek Szyprowskiad398592021-02-18 11:33:18 +0100800 adc: adc@0 {
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100801 compatible = "sandbox,adc";
Marek Szyprowskiad398592021-02-18 11:33:18 +0100802 #io-channel-cells = <1>;
Przemyslaw Marczak1bc7f232015-10-27 13:08:06 +0100803 vdd-supply = <&buck2>;
804 vss-microvolts = <0>;
805 };
806
Mark Kettenis67748ee2021-10-23 16:58:02 +0200807 iommu: iommu@0 {
808 compatible = "sandbox,iommu";
809 #iommu-cells = <0>;
810 };
811
Simon Glass515dcff2020-02-06 09:55:00 -0700812 irq: irq {
Simon Glass54028bc2019-12-06 21:41:59 -0700813 compatible = "sandbox,irq";
Simon Glass515dcff2020-02-06 09:55:00 -0700814 interrupt-controller;
815 #interrupt-cells = <2>;
Simon Glass54028bc2019-12-06 21:41:59 -0700816 };
817
Simon Glass90b6fef2016-01-18 19:52:26 -0700818 lcd {
819 u-boot,dm-pre-reloc;
820 compatible = "sandbox,lcd-sdl";
Dario Binacchi20dd9e12021-04-11 09:39:50 +0200821 pinctrl-names = "default";
822 pinctrl-0 = <&pinmux_lcd_pins>;
Simon Glass90b6fef2016-01-18 19:52:26 -0700823 xres = <1366>;
824 yres = <768>;
825 };
826
Simon Glassd783eb32015-07-06 12:54:34 -0600827 leds {
828 compatible = "gpio-leds";
829
830 iracibble {
831 gpios = <&gpio_a 1 0>;
832 label = "sandbox:red";
833 };
834
835 martinet {
836 gpios = <&gpio_a 2 0>;
837 label = "sandbox:green";
838 };
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200839
840 default_on {
841 gpios = <&gpio_a 5 0>;
842 label = "sandbox:default_on";
843 default-state = "on";
844 };
845
846 default_off {
847 gpios = <&gpio_a 6 0>;
Sean Andersonfbf8d652020-09-14 11:02:03 -0400848 /* label intentionally omitted */
Patrick Bruennb58adfe2018-04-11 11:16:29 +0200849 default-state = "off";
850 };
Simon Glassd783eb32015-07-06 12:54:34 -0600851 };
852
Paul Doelle709f0372022-07-04 09:00:25 +0000853 wdt-gpio-toggle {
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200854 gpios = <&gpio_a 7 0>;
855 compatible = "linux,wdt-gpio";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +0200856 hw_margin_ms = <100>;
Paul Doelle709f0372022-07-04 09:00:25 +0000857 hw_algo = "toggle";
858 always-running;
859 };
860
861 wdt-gpio-level {
862 gpios = <&gpio_a 7 0>;
863 compatible = "linux,wdt-gpio";
864 hw_margin_ms = <100>;
865 hw_algo = "level";
Rasmus Villemoes2b673872021-08-19 11:57:05 +0200866 always-running;
867 };
868
Stephen Warren62f2c902016-05-16 17:41:37 -0600869 mbox: mbox {
870 compatible = "sandbox,mbox";
871 #mbox-cells = <1>;
872 };
873
874 mbox-test {
875 compatible = "sandbox,mbox-test";
876 mboxes = <&mbox 100>, <&mbox 1>;
877 mbox-names = "other", "test";
878 };
879
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900880 cpus {
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200881 #address-cells = <1>;
882 #size-cells = <0>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400883 timebase-frequency = <2000000>;
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200884 cpu1: cpu@1 {
885 device_type = "cpu";
886 reg = <0x1>;
Sean Anderson79d3bba2020-09-28 10:52:23 -0400887 timebase-frequency = <3000000>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900888 compatible = "sandbox,cpu_sandbox";
889 u-boot,dm-pre-reloc;
890 };
Mario Sixdea5df72018-08-06 10:23:44 +0200891
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200892 cpu2: cpu@2 {
893 device_type = "cpu";
894 reg = <0x2>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900895 compatible = "sandbox,cpu_sandbox";
896 u-boot,dm-pre-reloc;
897 };
Mario Sixdea5df72018-08-06 10:23:44 +0200898
Heinrich Schuchardt20f9d3d2021-08-28 11:42:08 +0200899 cpu3: cpu@3 {
900 device_type = "cpu";
901 reg = <0x3>;
AKASHI Takahiro8fb963a2019-08-27 17:17:03 +0900902 compatible = "sandbox,cpu_sandbox";
903 u-boot,dm-pre-reloc;
904 };
Mario Sixdea5df72018-08-06 10:23:44 +0200905 };
906
Dave Gerlach75dbdfc2020-07-15 23:39:58 -0500907 chipid: chipid {
908 compatible = "sandbox,soc";
909 };
910
Simon Glassc953aaf2018-12-10 10:37:34 -0700911 i2s: i2s {
912 compatible = "sandbox,i2s";
913 #sound-dai-cells = <1>;
Simon Glass4d5814c2019-02-16 20:24:56 -0700914 sandbox,silent; /* Don't emit sounds while testing */
Simon Glassc953aaf2018-12-10 10:37:34 -0700915 };
916
Jean-Jacques Hiblotdb97c7f2019-07-05 09:33:57 +0200917 nop-test_0 {
918 compatible = "sandbox,nop_sandbox1";
919 nop-test_1 {
920 compatible = "sandbox,nop_sandbox2";
921 bind = "True";
922 };
923 nop-test_2 {
924 compatible = "sandbox,nop_sandbox2";
925 bind = "False";
926 };
927 };
928
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200929 misc-test {
Sean Anderson13652b82022-05-05 13:11:44 -0400930 #address-cells = <1>;
931 #size-cells = <1>;
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200932 compatible = "sandbox,misc_sandbox";
Sean Anderson13652b82022-05-05 13:11:44 -0400933
934 eth5_addr: mac-address@10 {
935 reg = <0x10 6>;
936 };
Mario Sixa8ce0ee2018-07-31 14:24:14 +0200937 };
938
Simon Glasse4fef742017-04-23 20:02:07 -0600939 mmc2 {
940 compatible = "sandbox,mmc";
Simon Glass965cd402021-07-05 16:32:58 -0600941 non-removable;
Simon Glasse4fef742017-04-23 20:02:07 -0600942 };
943
Simon Glassb255efc2022-04-24 23:31:24 -0600944 /* This is used for the bootdev tests */
Simon Glasse4fef742017-04-23 20:02:07 -0600945 mmc1 {
946 compatible = "sandbox,mmc";
Simon Glassb255efc2022-04-24 23:31:24 -0600947 filename = "mmc1.img";
Simon Glasse4fef742017-04-23 20:02:07 -0600948 };
949
Simon Glassb255efc2022-04-24 23:31:24 -0600950 /* This is used for the fastboot tests */
Simon Glasse4fef742017-04-23 20:02:07 -0600951 mmc0 {
Simon Glassd3e58e42015-07-06 12:54:32 -0600952 compatible = "sandbox,mmc";
953 };
954
Simon Glass53a68b32019-02-16 20:24:50 -0700955 pch {
956 compatible = "sandbox,pch";
957 };
958
Tom Rini4a3ca482020-02-11 12:41:23 -0500959 pci0: pci@0 {
Simon Glass3a6eae62015-03-05 12:25:34 -0700960 compatible = "sandbox,pci";
961 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -0500962 bus-range = <0x00 0xff>;
Simon Glass3a6eae62015-03-05 12:25:34 -0700963 #address-cells = <3>;
964 #size-cells = <2>;
Simon Glass35464f72019-09-25 08:56:08 -0600965 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000000
Simon Glass3a6eae62015-03-05 12:25:34 -0700966 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700967 pci@0,0 {
968 compatible = "pci-generic";
969 reg = <0x0000 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600970 sandbox,emul = <&swap_case_emul0_0>;
Bin Mengcbf071b2018-08-03 01:14:39 -0700971 };
Alex Margineanf1274432019-06-07 11:24:24 +0300972 pci@1,0 {
973 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -0600974 /* reg 0 is at 0x14, using FDT_PCI_SPACE_MEM32 */
975 reg = <0x02000814 0 0 0 0
976 0x01000810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -0600977 sandbox,emul = <&swap_case_emul0_1>;
Alex Margineanf1274432019-06-07 11:24:24 +0300978 };
Simon Glass937bb472019-12-06 21:41:57 -0700979 p2sb-pci@2,0 {
980 compatible = "sandbox,p2sb";
981 reg = <0x02001010 0 0 0 0>;
982 sandbox,emul = <&p2sb_emul>;
983
984 adder {
985 intel,p2sb-port-id = <3>;
986 compatible = "sandbox,adder";
987 };
988 };
Simon Glass8c501022019-12-06 21:41:54 -0700989 pci@1e,0 {
990 compatible = "sandbox,pmc";
991 reg = <0xf000 0 0 0 0>;
992 sandbox,emul = <&pmc_emul1e>;
993 acpi-base = <0x400>;
994 gpe0-dwx-mask = <0xf>;
995 gpe0-dwx-shift-base = <4>;
996 gpe0-dw = <6 7 9>;
997 gpe0-sts = <0x20>;
998 gpe0-en = <0x30>;
999 };
Simon Glass3a6eae62015-03-05 12:25:34 -07001000 pci@1f,0 {
1001 compatible = "pci-generic";
Simon Glass23b27592019-09-15 12:08:58 -06001002 /* reg 0 is at 0x10, using FDT_PCI_SPACE_IO */
1003 reg = <0x0100f810 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001004 sandbox,emul = <&swap_case_emul0_1f>;
Simon Glass3a6eae62015-03-05 12:25:34 -07001005 };
1006 };
1007
Simon Glassb98ba4c2019-09-25 08:56:10 -06001008 pci-emul0 {
1009 compatible = "sandbox,pci-emul-parent";
1010 swap_case_emul0_0: emul0@0,0 {
1011 compatible = "sandbox,swap-case";
1012 };
1013 swap_case_emul0_1: emul0@1,0 {
1014 compatible = "sandbox,swap-case";
1015 use-ea;
1016 };
1017 swap_case_emul0_1f: emul0@1f,0 {
1018 compatible = "sandbox,swap-case";
1019 };
Simon Glass937bb472019-12-06 21:41:57 -07001020 p2sb_emul: emul@2,0 {
1021 compatible = "sandbox,p2sb-emul";
1022 };
Simon Glass8c501022019-12-06 21:41:54 -07001023 pmc_emul1e: emul@1e,0 {
1024 compatible = "sandbox,pmc-emul";
1025 };
Simon Glassb98ba4c2019-09-25 08:56:10 -06001026 };
1027
Tom Rini4a3ca482020-02-11 12:41:23 -05001028 pci1: pci@1 {
Bin Meng408e5902018-08-03 01:14:41 -07001029 compatible = "sandbox,pci";
1030 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001031 bus-range = <0x00 0xff>;
Bin Meng408e5902018-08-03 01:14:41 -07001032 #address-cells = <3>;
1033 #size-cells = <2>;
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001034 ranges = <0x02000000 0 0x30000000 0x30000000 0 0x2000 // MEM0
Andrew Scullc7456a42022-04-21 16:11:09 +00001035 0x02000000 0 0x31000000 0x3e000000 0 0x2000 // MEM1
Suneel Garapati3ac3aec2019-10-19 17:10:20 -07001036 0x01000000 0 0x40000000 0x40000000 0 0x2000>;
Bin Meng5fed5362018-08-03 01:14:47 -07001037 sandbox,dev-info = <0x08 0x00 0x1234 0x5678
Marek Vasute5733222018-10-10 21:27:08 +02001038 0x0c 0x00 0x1234 0x5678
1039 0x10 0x00 0x1234 0x5678>;
1040 pci@10,0 {
1041 reg = <0x8000 0 0 0 0>;
1042 };
Bin Meng408e5902018-08-03 01:14:41 -07001043 };
1044
Tom Rini4a3ca482020-02-11 12:41:23 -05001045 pci2: pci@2 {
Bin Meng510dddb2018-08-03 01:14:50 -07001046 compatible = "sandbox,pci";
1047 device_type = "pci";
Tom Rini4a3ca482020-02-11 12:41:23 -05001048 bus-range = <0x00 0xff>;
Bin Meng510dddb2018-08-03 01:14:50 -07001049 #address-cells = <3>;
1050 #size-cells = <2>;
1051 ranges = <0x02000000 0 0x50000000 0x50000000 0 0x2000
1052 0x01000000 0 0x60000000 0x60000000 0 0x2000>;
1053 sandbox,dev-info = <0x08 0x00 0x1234 0x5678>;
1054 pci@1f,0 {
1055 compatible = "pci-generic";
1056 reg = <0xf800 0 0 0 0>;
Simon Glassb98ba4c2019-09-25 08:56:10 -06001057 sandbox,emul = <&swap_case_emul2_1f>;
1058 };
1059 };
1060
1061 pci-emul2 {
1062 compatible = "sandbox,pci-emul-parent";
1063 swap_case_emul2_1f: emul2@1f,0 {
1064 compatible = "sandbox,swap-case";
Bin Meng510dddb2018-08-03 01:14:50 -07001065 };
1066 };
1067
Ramon Friedc64f19b2019-04-27 11:15:23 +03001068 pci_ep: pci_ep {
1069 compatible = "sandbox,pci_ep";
1070 };
1071
Simon Glass9c433fe2017-04-23 20:10:44 -06001072 probing {
1073 compatible = "simple-bus";
1074 test1 {
1075 compatible = "denx,u-boot-probe-test";
1076 };
1077
1078 test2 {
1079 compatible = "denx,u-boot-probe-test";
1080 };
1081
1082 test3 {
1083 compatible = "denx,u-boot-probe-test";
1084 };
1085
1086 test4 {
1087 compatible = "denx,u-boot-probe-test";
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001088 first-syscon = <&syscon0>;
1089 second-sys-ctrl = <&another_system_controller>;
Patrick Delaunayee010432019-03-07 09:57:13 +01001090 third-syscon = <&syscon2>;
Simon Glass9c433fe2017-04-23 20:10:44 -06001091 };
1092 };
1093
Stephen Warren92c67fa2016-07-13 13:45:31 -06001094 pwrdom: power-domain {
1095 compatible = "sandbox,power-domain";
1096 #power-domain-cells = <1>;
1097 };
1098
1099 power-domain-test {
1100 compatible = "sandbox,power-domain-test";
1101 power-domains = <&pwrdom 2>;
1102 };
1103
Simon Glass5620cf82018-10-01 12:22:40 -06001104 pwm: pwm {
Simon Glasse62f4be2017-04-16 21:01:11 -06001105 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001106 #pwm-cells = <2>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001107 pinctrl-names = "default";
1108 pinctrl-0 = <&pinmux_pwm_pins>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001109 };
1110
1111 pwm2 {
1112 compatible = "sandbox,pwm";
Simon Glass5620cf82018-10-01 12:22:40 -06001113 #pwm-cells = <2>;
Simon Glasse62f4be2017-04-16 21:01:11 -06001114 };
1115
Simon Glass3d355e62015-07-06 12:54:31 -06001116 ram {
1117 compatible = "sandbox,ram";
1118 };
1119
Simon Glassd860f222015-07-06 12:54:29 -06001120 reset@0 {
1121 compatible = "sandbox,warm-reset";
1122 };
1123
1124 reset@1 {
1125 compatible = "sandbox,reset";
1126 };
1127
Stephen Warren6488e642016-06-17 09:43:59 -06001128 resetc: reset-ctl {
1129 compatible = "sandbox,reset-ctl";
1130 #reset-cells = <1>;
1131 };
1132
1133 reset-ctl-test {
1134 compatible = "sandbox,reset-ctl-test";
Neil Armstrong9b4cdef2021-04-20 10:42:25 +02001135 resets = <&resetc 100>, <&resetc 2>, <&resetc 20>, <&resetc 40>;
1136 reset-names = "other", "test", "test2", "test3";
Stephen Warren6488e642016-06-17 09:43:59 -06001137 };
1138
Sughosh Ganu23e37512019-12-28 23:58:31 +05301139 rng {
1140 compatible = "sandbox,sandbox-rng";
1141 };
1142
Nishanth Menonedf85812015-09-17 15:42:41 -05001143 rproc_1: rproc@1 {
1144 compatible = "sandbox,test-processor";
1145 remoteproc-name = "remoteproc-test-dev1";
1146 };
1147
1148 rproc_2: rproc@2 {
1149 compatible = "sandbox,test-processor";
1150 internal-memory-mapped;
1151 remoteproc-name = "remoteproc-test-dev2";
1152 };
1153
Simon Glass5620cf82018-10-01 12:22:40 -06001154 panel {
1155 compatible = "simple-panel";
1156 backlight = <&backlight 0 100>;
1157 };
1158
Ramon Fried26ed32e2018-07-02 02:57:59 +03001159 smem@0 {
1160 compatible = "sandbox,smem";
1161 };
1162
Simon Glass76072ac2018-12-10 10:37:36 -07001163 sound {
1164 compatible = "sandbox,sound";
1165 cpu {
1166 sound-dai = <&i2s 0>;
1167 };
1168
1169 codec {
1170 sound-dai = <&audio 0>;
1171 };
1172 };
1173
Simon Glass25348a42014-10-13 23:42:11 -06001174 spi@0 {
1175 #address-cells = <1>;
1176 #size-cells = <0>;
Simon Glasscf61f742015-07-06 12:54:36 -06001177 reg = <0 1>;
Simon Glass25348a42014-10-13 23:42:11 -06001178 compatible = "sandbox,spi";
Ovidiu Panaitae734732020-12-14 19:06:47 +02001179 cs-gpios = <0>, <0>, <&gpio_a 0>;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001180 pinctrl-names = "default";
1181 pinctrl-0 = <&pinmux_spi0_pins>;
1182
Simon Glass25348a42014-10-13 23:42:11 -06001183 spi.bin@0 {
1184 reg = <0>;
Neil Armstronga009fa72019-02-10 10:16:20 +00001185 compatible = "spansion,m25p16", "jedec,spi-nor";
Simon Glass25348a42014-10-13 23:42:11 -06001186 spi-max-frequency = <40000000>;
1187 sandbox,filename = "spi.bin";
1188 };
Ovidiu Panaitae734732020-12-14 19:06:47 +02001189 spi.bin@1 {
1190 reg = <1>;
1191 compatible = "spansion,m25p16", "jedec,spi-nor";
1192 spi-max-frequency = <50000000>;
1193 sandbox,filename = "spi.bin";
1194 spi-cpol;
1195 spi-cpha;
1196 };
Simon Glass25348a42014-10-13 23:42:11 -06001197 };
1198
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001199 syscon0: syscon@0 {
Simon Glasscd556522015-07-06 12:54:35 -06001200 compatible = "sandbox,syscon0";
Mario Sixe3f59f42018-10-04 09:00:40 +02001201 reg = <0x10 16>;
Simon Glasscd556522015-07-06 12:54:35 -06001202 };
1203
Jean-Jacques Hiblotdc44ea42018-11-29 10:57:37 +01001204 another_system_controller: syscon@1 {
Simon Glasscd556522015-07-06 12:54:35 -06001205 compatible = "sandbox,syscon1";
Simon Glasscf61f742015-07-06 12:54:36 -06001206 reg = <0x20 5
1207 0x28 6
1208 0x30 7
1209 0x38 8>;
Simon Glasscd556522015-07-06 12:54:35 -06001210 };
1211
Patrick Delaunayee010432019-03-07 09:57:13 +01001212 syscon2: syscon@2 {
Masahiro Yamada42ab1072018-04-23 13:26:53 +09001213 compatible = "simple-mfd", "syscon";
1214 reg = <0x40 5
1215 0x48 6
1216 0x50 7
1217 0x58 8>;
1218 };
1219
Jean-Jacques Hiblota94b6972020-10-16 16:16:34 +05301220 syscon3: syscon@3 {
1221 compatible = "simple-mfd", "syscon";
1222 reg = <0x000100 0x10>;
1223
1224 muxcontroller0: a-mux-controller {
1225 compatible = "mmio-mux";
1226 #mux-control-cells = <1>;
1227
1228 mux-reg-masks = <0x0 0x30>, /* 0: reg 0x0, bits 5:4 */
1229 <0xc 0x1E>, /* 1: reg 0xc, bits 4:1 */
1230 <0x4 0xFF>; /* 2: reg 0x4, bits 7:0 */
1231 idle-states = <MUX_IDLE_AS_IS>, <0x02>, <0x73>;
1232 u-boot,mux-autoprobe;
1233 };
1234 };
1235
1236 muxcontroller1: emul-mux-controller {
1237 compatible = "mux-emul";
1238 #mux-control-cells = <0>;
1239 u-boot,mux-autoprobe;
1240 idle-state = <0xabcd>;
1241 };
1242
Simon Glass791a17f2020-12-16 21:20:27 -07001243 testfdtm0 {
1244 compatible = "denx,u-boot-fdtm-test";
1245 };
1246
1247 testfdtm1: testfdtm1 {
1248 compatible = "denx,u-boot-fdtm-test";
1249 };
1250
1251 testfdtm2 {
1252 compatible = "denx,u-boot-fdtm-test";
1253 };
1254
Sean Anderson79d3bba2020-09-28 10:52:23 -04001255 timer@0 {
Thomas Chou6f2cfbf2015-12-11 16:27:34 +08001256 compatible = "sandbox,timer";
1257 clock-frequency = <1000000>;
1258 };
1259
Sean Anderson79d3bba2020-09-28 10:52:23 -04001260 timer@1 {
1261 compatible = "sandbox,timer";
1262 sandbox,timebase-frequency-fallback;
1263 };
1264
Miquel Raynal80938c12018-05-15 11:57:27 +02001265 tpm2 {
1266 compatible = "sandbox,tpm2";
1267 };
1268
Simon Glass5b968632015-05-22 15:42:15 -06001269 uart0: serial {
1270 compatible = "sandbox,serial";
1271 u-boot,dm-pre-reloc;
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001272 pinctrl-names = "default";
1273 pinctrl-0 = <&pinmux_uart0_pins>;
Joe Hershberger4c197242015-03-22 17:09:15 -05001274 };
1275
Simon Glass31680482015-03-25 12:23:05 -06001276 usb_0: usb@0 {
1277 compatible = "sandbox,usb";
1278 status = "disabled";
1279 hub {
1280 compatible = "sandbox,usb-hub";
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1283 flash-stick {
1284 reg = <0>;
1285 compatible = "sandbox,usb-flash";
1286 };
1287 };
1288 };
1289
1290 usb_1: usb@1 {
1291 compatible = "sandbox,usb";
Mark Kettenis67748ee2021-10-23 16:58:02 +02001292 iommus = <&iommu>;
Simon Glass31680482015-03-25 12:23:05 -06001293 hub {
1294 compatible = "usb-hub";
1295 usb,device-class = <9>;
Michael Walle7c961322020-06-02 01:47:07 +02001296 #address-cells = <1>;
1297 #size-cells = <0>;
Simon Glass31680482015-03-25 12:23:05 -06001298 hub-emul {
1299 compatible = "sandbox,usb-hub";
1300 #address-cells = <1>;
1301 #size-cells = <0>;
Simon Glass4700fe52015-11-08 23:48:01 -07001302 flash-stick@0 {
Simon Glass31680482015-03-25 12:23:05 -06001303 reg = <0>;
1304 compatible = "sandbox,usb-flash";
1305 sandbox,filepath = "testflash.bin";
1306 };
1307
Simon Glass4700fe52015-11-08 23:48:01 -07001308 flash-stick@1 {
1309 reg = <1>;
1310 compatible = "sandbox,usb-flash";
1311 sandbox,filepath = "testflash1.bin";
1312 };
1313
1314 flash-stick@2 {
1315 reg = <2>;
1316 compatible = "sandbox,usb-flash";
1317 sandbox,filepath = "testflash2.bin";
1318 };
1319
Simon Glassc0ccc722015-11-08 23:48:08 -07001320 keyb@3 {
1321 reg = <3>;
1322 compatible = "sandbox,usb-keyb";
1323 };
1324
Simon Glass31680482015-03-25 12:23:05 -06001325 };
Michael Walle7c961322020-06-02 01:47:07 +02001326
1327 usbstor@1 {
1328 reg = <1>;
1329 };
1330 usbstor@3 {
1331 reg = <3>;
1332 };
Simon Glass31680482015-03-25 12:23:05 -06001333 };
1334 };
1335
1336 usb_2: usb@2 {
1337 compatible = "sandbox,usb";
1338 status = "disabled";
1339 };
1340
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001341 spmi: spmi@0 {
1342 compatible = "sandbox,spmi";
1343 #address-cells = <0x1>;
1344 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001345 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001346 pm8916@0 {
1347 compatible = "qcom,spmi-pmic";
1348 reg = <0x0 0x1>;
1349 #address-cells = <0x1>;
1350 #size-cells = <0x1>;
Simon Glass95139972019-09-25 08:55:59 -06001351 ranges;
Mateusz Kulikowskic7e4fbb2016-03-31 23:12:28 +02001352
1353 spmi_gpios: gpios@c000 {
1354 compatible = "qcom,pm8916-gpio";
1355 reg = <0xc000 0x400>;
1356 gpio-controller;
1357 gpio-count = <4>;
1358 #gpio-cells = <2>;
1359 gpio-bank-name="spmi";
1360 };
1361 };
1362 };
maxims@google.comdaea6d42017-04-17 12:00:21 -07001363
1364 wdt0: wdt@0 {
1365 compatible = "sandbox,wdt";
Rasmus Villemoesf91ff5a2021-08-19 11:57:06 +02001366 hw_margin_ms = <200>;
maxims@google.comdaea6d42017-04-17 12:00:21 -07001367 };
Rob Clarka471b672018-01-10 11:33:30 +01001368
Mario Six95922152018-08-09 14:51:19 +02001369 axi: axi@0 {
1370 compatible = "sandbox,axi";
1371 #address-cells = <0x1>;
1372 #size-cells = <0x1>;
1373 store@0 {
1374 compatible = "sandbox,sandbox_store";
1375 reg = <0x0 0x400>;
1376 };
1377 };
1378
Rob Clarka471b672018-01-10 11:33:30 +01001379 chosen {
Simon Glass305ac9a2018-02-03 10:36:58 -07001380 #address-cells = <1>;
1381 #size-cells = <1>;
Simon Glassf3455962020-01-27 08:49:43 -07001382 setting = "sunrise ohoka";
1383 other-node = "/some-bus/c-test@5";
Simon Glasse09223c2020-01-27 08:49:46 -07001384 int-values = <0x1937 72993>;
Simon Glass3c601b12020-07-07 13:12:06 -06001385 u-boot,acpi-ssdt-order = <&acpi_test2 &acpi_test1>;
Rob Clarka471b672018-01-10 11:33:30 +01001386 chosen-test {
1387 compatible = "denx,u-boot-fdt-test";
1388 reg = <9 1>;
1389 };
Simon Glassc8d37212022-07-30 15:52:34 -06001390
1391 fwupd {
1392 compatible = "simple-bus";
1393 firmware0 {
1394 compatible = "fwupd,vbe-simple";
1395 storage = "mmc1";
1396 area-start = <0x400>;
1397 area-size = <0x1000>;
1398 skip-offset = <0x200>;
1399 state-offset = <0x400>;
1400 state-size = <0x40>;
1401 version-offset = <0x800>;
1402 version-size = <0x100>;
1403 };
1404 };
Rob Clarka471b672018-01-10 11:33:30 +01001405 };
Mario Six35616ef2018-03-12 14:53:33 +01001406
1407 translation-test@8000 {
1408 compatible = "simple-bus";
1409 reg = <0x8000 0x4000>;
1410
1411 #address-cells = <0x2>;
1412 #size-cells = <0x1>;
1413
1414 ranges = <0 0x0 0x8000 0x1000
1415 1 0x100 0x9000 0x1000
1416 2 0x200 0xA000 0x1000
1417 3 0x300 0xB000 0x1000
1418 >;
1419
Fabien Dessenne22236e02019-05-31 15:11:30 +02001420 dma-ranges = <0 0x000 0x10000000 0x1000
1421 1 0x100 0x20000000 0x1000
1422 >;
1423
Mario Six35616ef2018-03-12 14:53:33 +01001424 dev@0,0 {
1425 compatible = "denx,u-boot-fdt-dummy";
1426 reg = <0 0x0 0x1000>;
Álvaro Fernåndez Rojasa3181152018-12-03 19:37:09 +01001427 reg-names = "sandbox-dummy-0";
Mario Six35616ef2018-03-12 14:53:33 +01001428 };
1429
1430 dev@1,100 {
1431 compatible = "denx,u-boot-fdt-dummy";
1432 reg = <1 0x100 0x1000>;
1433
1434 };
1435
1436 dev@2,200 {
1437 compatible = "denx,u-boot-fdt-dummy";
1438 reg = <2 0x200 0x1000>;
1439 };
1440
1441
1442 noxlatebus@3,300 {
1443 compatible = "simple-bus";
1444 reg = <3 0x300 0x1000>;
1445
1446 #address-cells = <0x1>;
1447 #size-cells = <0x0>;
1448
1449 dev@42 {
1450 compatible = "denx,u-boot-fdt-dummy";
1451 reg = <0x42>;
1452 };
1453 };
1454 };
Mario Six02ad6fb2018-09-27 09:19:31 +02001455
1456 osd {
1457 compatible = "sandbox,sandbox_osd";
1458 };
Tom Rinib93eea72018-09-30 18:16:51 -04001459
Jens Wiklander86afaa62018-09-25 16:40:16 +02001460 sandbox_tee {
1461 compatible = "sandbox,tee";
1462 };
Bin Meng1bb290d2018-10-15 02:21:26 -07001463
1464 sandbox_virtio1 {
1465 compatible = "sandbox,virtio1";
1466 };
1467
1468 sandbox_virtio2 {
1469 compatible = "sandbox,virtio2";
1470 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001471
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001472 sandbox_scmi {
1473 compatible = "sandbox,scmi-devices";
Etienne Carrierebf1f1322022-02-21 09:22:41 +01001474 clocks = <&clk_scmi 2>, <&clk_scmi 0>;
Etienne Carriere09665cb2022-02-21 09:22:39 +01001475 resets = <&reset_scmi 3>;
1476 regul0-supply = <&regul0_scmi>;
1477 regul1-supply = <&regul1_scmi>;
Etienne Carriere2d94c08fa2020-09-09 18:44:05 +02001478 };
1479
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001480 pinctrl {
1481 compatible = "sandbox,pinctrl";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001482
Sean Anderson3438e3b2020-09-14 11:01:57 -04001483 pinctrl-names = "default", "alternate";
1484 pinctrl-0 = <&pinctrl_gpios>, <&pinctrl_i2s>;
1485 pinctrl-1 = <&pinctrl_spi>, <&pinctrl_i2c>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001486
Sean Anderson3438e3b2020-09-14 11:01:57 -04001487 pinctrl_gpios: gpios {
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001488 gpio0 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001489 pins = "P5";
1490 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001491 bias-pull-up;
1492 input-disable;
1493 };
1494 gpio1 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001495 pins = "P6";
1496 function = "GPIO";
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001497 output-high;
1498 drive-open-drain;
1499 };
1500 gpio2 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001501 pinmux = <SANDBOX_PINMUX(7, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001502 bias-pull-down;
1503 input-enable;
1504 };
1505 gpio3 {
Sean Anderson3438e3b2020-09-14 11:01:57 -04001506 pinmux = <SANDBOX_PINMUX(8, SANDBOX_PINMUX_GPIO)>;
Patrick Delaunay939cbe92020-01-13 11:35:12 +01001507 bias-disable;
1508 };
1509 };
Sean Anderson3438e3b2020-09-14 11:01:57 -04001510
1511 pinctrl_i2c: i2c {
1512 groups {
1513 groups = "I2C_UART";
1514 function = "I2C";
1515 };
1516
1517 pins {
1518 pins = "P0", "P1";
1519 drive-open-drain;
1520 };
1521 };
1522
1523 pinctrl_i2s: i2s {
1524 groups = "SPI_I2S";
1525 function = "I2S";
1526 };
1527
1528 pinctrl_spi: spi {
1529 groups = "SPI_I2S";
1530 function = "SPI";
1531
1532 cs {
1533 pinmux = <SANDBOX_PINMUX(5, SANDBOX_PINMUX_CS)>,
1534 <SANDBOX_PINMUX(6, SANDBOX_PINMUX_CS)>;
1535 };
1536 };
Patrice Chotard0fc8afc2018-10-24 14:10:23 +02001537 };
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001538
Dario Binacchi20dd9e12021-04-11 09:39:50 +02001539 pinctrl-single-no-width {
1540 compatible = "pinctrl-single";
1541 reg = <0x0000 0x238>;
1542 #pinctrl-cells = <1>;
1543 pinctrl-single,function-mask = <0x7f>;
1544 };
1545
1546 pinctrl-single-pins {
1547 compatible = "pinctrl-single";
1548 reg = <0x0000 0x238>;
1549 #pinctrl-cells = <1>;
1550 pinctrl-single,register-width = <32>;
1551 pinctrl-single,function-mask = <0x7f>;
1552
1553 pinmux_pwm_pins: pinmux_pwm_pins {
1554 pinctrl-single,pins = < 0x48 0x06 >;
1555 };
1556
1557 pinmux_spi0_pins: pinmux_spi0_pins {
1558 pinctrl-single,pins = <
1559 0x190 0x0c
1560 0x194 0x0c
1561 0x198 0x23
1562 0x19c 0x0c
1563 >;
1564 };
1565
1566 pinmux_uart0_pins: pinmux_uart0_pins {
1567 pinctrl-single,pins = <
1568 0x70 0x30
1569 0x74 0x00
1570 >;
1571 };
1572 };
1573
1574 pinctrl-single-bits {
1575 compatible = "pinctrl-single";
1576 reg = <0x0000 0x50>;
1577 #pinctrl-cells = <2>;
1578 pinctrl-single,bit-per-mux;
1579 pinctrl-single,register-width = <32>;
1580 pinctrl-single,function-mask = <0xf>;
1581
1582 pinmux_i2c0_pins: pinmux_i2c0_pins {
1583 pinctrl-single,bits = <
1584 0x10 0x00002200 0x0000ff00
1585 >;
1586 };
1587
1588 pinmux_lcd_pins: pinmux_lcd_pins {
1589 pinctrl-single,bits = <
1590 0x40 0x22222200 0xffffff00
1591 0x44 0x22222222 0xffffffff
1592 0x48 0x00000022 0x000000ff
1593 0x48 0x02000000 0x0f000000
1594 0x4c 0x02000022 0x0f0000ff
1595 >;
1596 };
1597 };
1598
Benjamin Gaignarda550b542018-11-27 13:49:50 +01001599 hwspinlock@0 {
1600 compatible = "sandbox,hwspinlock";
1601 };
Grygorii Strashko19ebf0b2018-11-28 19:17:51 +01001602
1603 dma: dma {
1604 compatible = "sandbox,dma";
1605 #dma-cells = <1>;
1606
1607 dmas = <&dma 0>, <&dma 1>, <&dma 2>;
1608 dma-names = "m2m", "tx0", "rx0";
1609 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001610
Alex Marginean0649be52019-07-12 10:13:53 +03001611 /*
1612 * keep mdio-mux ahead of mdio so that the mux is removed first at the
1613 * end of the test. If parent mdio is removed first, clean-up of the
1614 * mux will trigger a 2nd probe of parent-mdio, leaving parent-mdio
1615 * active at the end of the test. That it turn doesn't allow the mdio
1616 * class to be destroyed, triggering an error.
1617 */
1618 mdio-mux-test {
1619 compatible = "sandbox,mdio-mux";
1620 #address-cells = <1>;
1621 #size-cells = <0>;
1622 mdio-parent-bus = <&mdio>;
1623
1624 mdio-ch-test@0 {
1625 reg = <0>;
1626 };
1627 mdio-ch-test@1 {
1628 reg = <1>;
1629 };
1630 };
1631
1632 mdio: mdio-test {
Alex Marginean0daa53a2019-06-03 19:12:28 +03001633 compatible = "sandbox,mdio";
Marek BehĂșnf4f1ddc2022-04-07 00:32:57 +02001634 #address-cells = <1>;
1635 #size-cells = <0>;
1636
1637 ethphy1: ethernet-phy@1 {
1638 reg = <1>;
1639 };
Alex Marginean0daa53a2019-06-03 19:12:28 +03001640 };
Sean Andersonb7860542020-06-24 06:41:12 -04001641
1642 pm-bus-test {
1643 compatible = "simple-pm-bus";
1644 clocks = <&clk_sandbox 4>;
1645 power-domains = <&pwrdom 1>;
1646 };
Sean Anderson0c1f6bf2020-06-24 06:41:14 -04001647
1648 resetc2: syscon-reset {
1649 compatible = "syscon-reset";
1650 #reset-cells = <1>;
1651 regmap = <&syscon0>;
1652 offset = <1>;
1653 mask = <0x27FFFFFF>;
1654 assert-high = <0>;
1655 };
1656
1657 syscon-reset-test {
1658 compatible = "sandbox,misc_sandbox";
1659 resets = <&resetc2 15>, <&resetc2 30>, <&resetc2 60>;
1660 reset-names = "valid", "no_mask", "out_of_range";
1661 };
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301662
Simon Glass458b66a2020-11-05 06:32:05 -07001663 sysinfo {
1664 compatible = "sandbox,sysinfo-sandbox";
1665 };
1666
Sean Anderson1c830672021-04-20 10:50:58 -04001667 sysinfo-gpio {
1668 compatible = "gpio-sysinfo";
1669 gpios = <&gpio_a 15>, <&gpio_a 16>, <&gpio_a 17>;
1670 revisions = <19>, <5>;
1671 names = "rev_a", "foo";
1672 };
1673
Jean-Jacques Hiblot0b89fc52020-09-24 10:04:18 +05301674 some_regmapped-bus {
1675 #address-cells = <0x1>;
1676 #size-cells = <0x1>;
1677
1678 ranges = <0x0 0x0 0x10>;
1679 compatible = "simple-bus";
1680
1681 regmap-test_0 {
1682 reg = <0 0x10>;
1683 compatible = "sandbox,regmap_test";
1684 };
1685 };
Simon Glassb2c1cac2014-02-26 15:59:21 -07001686};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +02001687
1688#include "sandbox_pmic.dtsi"
Heinrich Schuchardte24fdef2021-02-18 13:01:35 +01001689#include "cros-ec-keyboard.dtsi"